SU1464292A2 - Series-to-parallel code converter - Google Patents

Abstract

The invention relates to computing and can be used in digital channel data transmission systems to convert serial codes to parallel ones. The invention allows, by introducing multi-speed information reception, to expand the range of application of the converter. The sequential code to parallel converter contains a shift register 1, a buffer register 2, a block of 3; control unit; block 4; pause; and frequency control block 5, which contains a pulse shaper, a pulse counter, a depigrator register, a switch, a frequency divider, an AND element, and a pulse generator. 2 з.п, ф-л, 3 Il.

Description

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The invention relates to computing and can be used in data transmission systems over digital channels for converting serial codes into parallel ones and is an improvement of the converter by author. St. No. 1262732.

The aim of the invention is to expand the field of application of the converter.

FIG. 1 is a functional block diagram of a converter; in fig. 2 is a functional block diagram of frequency control block I; in fig. 3 - timing diagrams characterizing the operation of the frequency control unit.

The serial-to-parallel-to-parallel converter contains a shift register 1, a buffer register 2, {control block 3, block 4 for i-pause allocation and block 5 for frequency control,

as well as the input of 6 sync pulses of the code: information input 7, output 8 and additional converter code 9.

The frequency control unit 5 contains: a pulse driver 10, a pulse counter 11, a decoder 12, a register 13, a switch 14, a divider 15 of the I frequency, an AND element 16 and a pulse generator 17.

FIG. 3 corresponding indices denote: a - signal at the input I of block 5; b signal at output i of element 16j; c - signal at output: generator 17; g is the signal at the first output of the imager 10; d is the signal at the second output of the imager 10; e is the signal at the output of the decoder 12.

The Converter operates as follows.

At the fath of the frequency control unit 5, the code clock pulses are received. Element And 16 transmits to the counting input of the counter 11 pulses of the generator 17 at the time of the presence of the signal of the sync pulse code and does not pass the pulses of the generator 17 at the time of the absence of the sync pulses of the code. The sync pulses of the code also go to the driver 10, at the output of which a signal is generated for the initial installation of counter 11 and a signal for recording information into the register 13. Counter 11 calculates the number of generator pulses 17 that passed to its counting input during the operation of the sync pulse

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Sa code, and at its outputs a code of the number n is formed, proportional to the number of pulses transmitted to its counting input. The code of the number n is fed to the decoder 12, which converts the code of the number n to the code of the number m according to the following principle: the number m corresponds to the code falling in the interval between the threshold values N, ": n N, the code proportional to the normalized speed m transfer code. At normalized code transmission rates, there are also normalized durations of the code clock, and a trace of preferably, and the corresponding number of pulses of the generator 17, transmitted to the counting input of the counter 11 N; ff, oBM). The value of N is chosen as the average distance between two values of N; (corresponding to two adjacent transmission rates.

Thus, the entire range of code rate transmissions is assigned to codes t, each of which corresponds to its code rate, i.e. when transmitting a code of five speeds, respectively, there are also five values of code m.

At the end of each conversion cycle, the number in the register 13 is recorded from the output of the decoder 12 and stored there until the end of the next cycle. The code from the register 13 output goes to the control inputs of the switch 14.

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The pulses of the generator 17 are fed to a frequency divider 15, made for example in the form of a counter, at the outputs of which frequencies are generated that correspond to code transmission rates, and the switch 14 passes to the output of block 5 that frequency which corresponds to the frequency the duration of the sync pulse signal, i.e. The converter should analyze the pulse duration, compare with threshold values, memorize this value and output a signal at frequency control unit 5 with a frequency close to the frequency that determines the information transmission rate over the channel. The shaper 10 signals are used to set the counter 11 to the initial state at the start of the code clock and write the converted number m to the register 13 after the code sync pulse ends.

Thus, at the first input of the block 4 in the pause output from the frequency control block 5, reference clock pulses are received with a frequency close to the frequency of the clock pulses of the code received from the converter 6 and the switch 6. If there are no sync pulses, which corresponds to a pause in the reception of a sequential code, a pause pulse is generated. If the sync pulse is present, which corresponds to the reception of a sequential code, then no pause pulses are generated. The pause pulse overwrites the bits of information from register 1: shift to buffer register 2.

The impulse of the initial installation from the output of the control unit 3 is fed to the input of the initial installation of the shift register 1 and makes its initial installation. As the sequential code and clock pulses arrive at the shift register 1, information on input 7 is received. The use of the received information from output 8 is performed only on the impulse end of the transformation generated on. Inlet 9.

The converter provides for high-speed data reception in multi-channel information transmission systems with a serial code.

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Claims (2)

Claims 1. Serial code to parallel converter by author. St. g No. 1262732, characterized in that, in order to expand the field of application of the converter, a frequency control unit is inserted in it, the code of which is connected to the first input of the 10 pause block, and the input of the frequency control block is connected to the second input of the pause block. 2. The Converter according to claim 1 ,. o t - characterized in that frequency control unit 15 contains a pulse shaper, a pulse counter, a decoder, a register, a switch, a frequency divider, an And element and a pulse generator, the output of which is connected to the input of the frequency divider and the first input of the And element whose outputs connected respectively to the information inputs of the switch and to the counting input of the pulse counter, the outputs of which are connected to the inputs of the section, the outputs of which are connected to the information input of the register, the first and second outputs of the driver and The pulses are connected respectively to the pulse counter installation input and to the register recording input, the outputs of which are connected to the control inputs of the switch, the output of which is the output of the control unit, the second input of the AND element, is combined with the input of the pulse generator and is the input of the control unit. five 15 M1ShShShShShSh iiinmniiiiiiiiHiiiiiiiiiiiiiniiiiiiiiiitniiiiiiiiiiiiiiiiiiiiiiiiiii I. / -1-ii Fig.Z