JP2000124778A - Image reading device and method and computer readable storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the influence of moise by multiplying the outputted 1st clock by a prescribed multiple, generating a 3rd clock based on the outputted 2nd clock and in the prescribed timing, driving an image reader by the 3rd clock to read the images and to output the image signals and keeping a specific relation between the 1st and 3rd clock frequencies. SOLUTION: This circuit contains the double-pixel periodic noise filters 101 and 102 which detect the double-pixel periodic noises. The digital data corresponding to the odd numbered pixel output of a CCD linear image sensor 1000 which are outputted from the A/D converters 1009 and 1035 are inputted to an image processing circuit 1010 and also to both filters 101 and 102. The sensor 1000 is driven by the 3rd frequency of 25 MHz. The oscillation frequency of a crystal oscillator 1017, i.e., the 1st frequency is 12.5 MHz, and the dividing ratio of a frequency divider 1021 is set at 1/8 by a CPU 103.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image reading apparatus, an image reading method, and a computer readable storage medium used in the image reading apparatus, and more particularly to an image reading apparatus having a timing generation circuit having a multiplication function using a PLL circuit. It is suitable.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram of a conventional image reading apparatus using a timing generating circuit having a multiplying function. In FIG. 6, a timing generation circuit 1016 is configured by a gate array, an FPGA, or the like.
7. Phase comparison circuit (hereinafter, PC circuit) 1018, voltage controlled oscillation circuit (hereinafter, VCO circuit) 1017, and frequency divider 1
021 constitutes a PLL circuit.

The oscillation output of the crystal oscillator 1017 is PC
Input to one input terminal of the circuit 1018 and the PC circuit 1
The DC output of 018 is input to the VCO circuit 1019.
The VCO circuit 1019 controls the oscillation frequency according to the DC voltage from the PC circuit 1018. Divider 1021 divides the output frequency of VCO circuit 1019 by a predetermined dividing ratio. The frequency division ratio is set by a CPU (not shown) according to the circuit system.

The frequency-divided output of the frequency divider 1021 is supplied to the PC circuit 10
18 is input to the other input terminal. PC circuit 1018
Now, the output frequency of the crystal oscillator 1017 and the frequency divider 1021
A DC voltage for controlling the VCO circuit 1019 is output so that the output frequency matches the output frequency. For example, crystal oscillator 101
7 is 12.5 MHz and the frequency division ratio of the frequency divider 1021 is 1/8, the oscillation frequency of the VCO circuit 1019 is 12.5 MHz × 8 = 100 MHz. It is possible to generate a higher-speed internal clock by multiplying such a low-frequency input.

[0005] The output clock of the VCO circuit 1019 is used as an internal clock of the timing generation circuit 1016. This internal clock is input to the counter 1020,
The output of the counter 1020 is the φ1 pulse generation block 1
022, φ2 pulse generation block 1023, φ1B pulse generation block 1024, RS pulse generation block 10
25, and are input to the SH pulse generation block 1026 to generate φ1, φ2, φ1B, RS, and SH pulses, respectively.

Since each pulse generation block has the same configuration, the internal description will be made only for the φ1 pulse generation block 1022. Inside the φ1 pulse generation block 1022, the output of the counter 1020 is input to the decoder 1027,
The pulse is decoded according to the predetermined count value set by the CPU. The decoder 1027 can perform pulse shaping of the oscillation frequency of the VCO circuit 1019 in units of one clock. When the oscillation frequency of the VCO circuit 1019 is 100 MHz, one cycle thereof is 10 ns.
Waveform control in c units is possible.

[0007] The output of the decoder 1027 is input to a first input terminal of a selector 1030 via 1 nsec delay elements 1028 and 1029 connected in series. The output of the 1 nsec delay element 1028 is provided to a second input terminal of the selector 1030, and the decoder 1 is provided to a third input terminal.
027 is directly input. The selector 1030 is
One of the three inputs is appropriately selected and output under the control of the CPU. The initial setting value of this selector 1030 is
This is a state in which the second input terminal for selecting the output of the 1 nsec delay element 1028 is selected, thereby enabling the delay control of ± 1 nsec with respect to the initial value.

The output of selector 1030 is output buffer 10
31 is input. The output buffer 1031 is a driver for driving an external load of the timing generation circuit 1016. The pulses φ1, φ2, φ1B, RS, and SH generated by the timing generation circuit 1016 are supplied to the pulse driver 1 via external wiring (substrate wiring, bundled wiring, etc.).
011, 1012, 1013, 1014, and 1015, respectively. Pulse drivers 1011 to 1015
Is a driver for driving the CCD linear image sensor 1000.

The CCD linear image sensor 1000 is regarded as a capacitive load. In particular, a transfer register driven by φ1 and φ2 pulses has the largest capacity among them, and a pulse driver 1 for driving φ1 and φ2 pulses.
For 011, 1012, those having particularly high ability are used.
The CCD linear image sensor 1000 has different image signal outputs for even-numbered pixels and odd-numbered pixels.

The output of odd-numbered pixels output from the CCD linear image sensor 1000 will be described. The odd-numbered pixel output output from the CCD linear image sensor 1000 is impedance-converted by the emitter follower 1001, then the DC component is removed by the capacitor 1002, and input to the sample-hold circuits 1003 and 1004 (hereinafter, SH circuit). The SH circuit 1004 samples a signal component, and the SH circuit 1003 samples a feedthrough level. Subsequently, the SH circuit 1005
At the same phase as the SH circuit 1004. The outputs of the SH circuits 1004 and 1005 are input to a differential amplifier 1006 and subjected to a subtraction process, whereby 1 /
f Noise removal is performed.

The output of the differential amplifier 1006 is
7, and an amplification process is performed so as to be at a predetermined level. The output of the amplifier 1007 is a clamp circuit 1008
(Hereinafter referred to as a CP circuit), and after being clamped to a predetermined DC level, is converted into digital data by an A / D converter 1009.

The output of the other even-numbered pixel output from the CCD linear image sensor 1000 is also determined by the emitter follower 1027, the capacitor 1028, and the SH circuit 102.
9, 1030, 1031, a differential amplifier 1032, an amplifier 1033, a CP circuit 1034, and an A / D converter 1035 perform the same processing as described above. A / D converter 100
Each of the image signals converted into digital data in steps 9 and 1035 is input to an image processing circuit 1010 to perform predetermined digital image processing.

FIG. 7 shows a CCD linear image sensor 100.
FIG. In FIG. 7, the photodiode 1
301 (hereinafter, PD) is composed of 7500 pixels,
The charges accumulated in the even-numbered pixels are transferred to transfer registers 1303 and 1305 via shift gates 1302 and 1304 (hereinafter, SH gates). The transfer registers 1303 and 1305 sequentially transfer charges in the direction of the final stage transfer registers 1306 and 1310 by two-phase driving of φ1 and φ2 pulses.

Last stage transfer registers 1306 and 1310
Is a final gate for supplying the charges transferred to the charge-voltage conversion capacitors 1308 and 1312. Here, in order to facilitate the description of an output waveform described later, the gate is typically a SW (switch). It is shown. Also, reset gates (hereinafter, RS gates) 1307 and 1311
Is for resetting the capacitors 1308 and 1312 on a pixel-by-pixel basis, and is also schematically represented by SW to facilitate the description of the output waveform.

The charges converted into voltages by the capacitors 1308 and 1312 are output as odd-numbered pixel outputs and even-numbered pixel outputs via output buffers 1309 and 1313, respectively.

Next, the CCD linear image sensor 100
The waveform of the output signal of 0 will be described. FIG. 8 shows an ideal driving waveform of the CCD linear image sensor 1000. In FIG. 8, the φ1B pulse simultaneously controls the final stage registers 1306 and 1310, and the RS pulse simultaneously controls the RS gates 1307 and 1311. Here, it is assumed that the output waveform is the same for both the odd-numbered pixel output and the even-numbered pixel output.

At timing T1, φ1B pulse,
The RS pulses are both at the Hi level, and the SWs of the final stage transfer registers 1306 and 1310 are controlled to open and the SWs of the RS gates 1307 and 1311 are controlled to close.
The capacitors 1308 and 1312 are charged to Vrs by the constant voltage 1314. Next, at timing T2, the RS pulse goes to Lo level, and the RS gate 130
The switches 7 and 1311 are controlled to open, and the voltages of the capacitors 1308 and 1312 change to a stable voltage called a feed-through level.

Next, at a timing T3, the φ1B pulse becomes Lo level, and the final stage transfer register 1306,
The switch 1310 is controlled in the closing direction, and the capacitor 130 of the charge transferred by the transfer register is controlled.
8, 1312 is started. Here, since the charge is an electron having a negative charge, the output signal appears as a negative voltage. TD (OS) is a delay time until the output stabilizes, and this is the delay time of the capacitors 1308 and 131
2 is determined by the time for supplying the electric charge to the second.

Next, at a timing T4, the φ1B pulse becomes Hi level, and the final stage registers 1306, 13
10 SW is controlled to open. Capacitor 130
8, 1312 are held, and no change appears in the output signal. By repeating the cycle of the timings T1 to T4 for each pixel, a signal output for each pixel can be obtained.

FIG. 9 shows a crystal oscillator 1017, a VCO circuit 1019, and a frequency divider 1021 in the timing generation circuit 1016 when the output frequency of the crystal oscillator 1017 is 12.5 MHz and the frequency division ratio of the frequency divider 1021 is 1/8. And φ1
5 is a timing chart illustrating a relationship with a B pulse. Since the frequency division ratio of the frequency divider 1021 is 1/8 as described above, the oscillation frequency of the VCO circuit 1019 is
The frequency is 100 MHz, which is eight times the 017 oscillation frequency.

The PC circuit 1018 includes a crystal oscillator 1017
The loop control is performed so that the output of the frequency divider 1021 becomes equal to the output of the frequency divider 1021. Therefore, as shown in FIG.
The phase of the output of 017 and the output of frequency divider 1021 match. The rising edge of the output of the VCO circuit 1019 is locked to both the rising and falling edges of the output of the crystal oscillator 1017. The counter 1020 has a VCO
It is driven by the 100 MHz clock output from the circuit 1019, but the count starts when the power is turned on or when
Since the φ1B pulse generated by decoding the output of the counter 1020 differs from the output timing of the CO circuit 1019, as shown in (a) to (h), there are eight different phases with respect to the output of the crystal oscillator 1017. Have a relationship.

In FIG. 9, the output of the crystal oscillator 1017 and the timing generation circuit
Has been described, the same applies to the φ2 pulse, φ1B pulse, RS pulse, and SH pulse.

FIG. 10 shows the actual waveform of the φ1B pulse in each phase relationship described with reference to FIG. Here, in order to show the effect of the output of the crystal oscillator 1017 on the φ1B pulse, description will be made on the assumption that different differential noises are added to the φ1B pulse at the rising and falling edges. In FIG. 10, the noise component is exaggerated for easy understanding. Also, (A)
9 (a) to 9 (h) respectively correspond to the phase relationships shown in FIGS. 9 (a) to 9 (h), and show the φ1B pulse, RS pulse, and CCD output waveform for each type.

The output waveform described with reference to FIG. 8 is an ideal waveform, and actually, the final stage transfer registers 1306 and 1310
Are composed of MOS transistors, and the φ1B pulse is used as a gate control voltage, so that the φ1B pulse waveform affects the output waveform. FIG. 10 shows a case where it is assumed that the noise component of the φ1B pulse affects the output signal 1: 1. It can be seen that the effect on the output waveform is different for each phase type.

In each figure, points indicated by α, β, γ, and δ are SH circuits 1003, 1004, 1005, or 1
029, 1030, and 1031 indicate points sampled, and the signal output from the differential amplifier 1006 or 1032 is (1) β-α <2) δ-γ for each pixel.

FIG. 11 shows the differential amplifier output in each of the types (A) to (H). In FIG. 11, the reference level indicates a reference level for comparing each waveform, and (A),
In the cases of (D), (E), and (H), both β-α and δ-γ are equal to the reference level, and the influence of noise from the crystal oscillator 1017 is not seen. On the other hand, (B), (C), (F),
In the case of (G), the crystal oscillator 1 is set at the sampling point.
Since the noise from 017 exists, the levels of β-α and δ-γ are different, and the noise has a period of two pixels. Also, as you can see from the figure, the levels are also different.

As described above, the phase patterns (A) to (H) change when the power is turned on or the PC circuit 1018 is started. Further, since the two-pixel period noise appearing in the output waveform of the differential amplifier depends on the sampling point of the SH circuit, the generation level and pattern are different even in the phase setting of the sampling pulse.

The noise in the two-pixel cycle is expressed by (CCD linear image sensor 1000 driving frequency) ÷
(Oscillation frequency of crystal oscillator 1017), the oscillation frequency of crystal oscillator 1017 is 6.25 MHz, and the frequency division ratio of frequency divider 1021 is 1 /
16. When the driving frequency of the CCD linear image sensor 1000 is 25 MHz, noise occurs in a 4-pixel cycle.

[0029]

As described above,
In an image reading apparatus using a timing generation circuit having a multiplying function using a PLL circuit, 1/2 ⁿ two-pixel cycle noise is generated due to the influence of a crystal oscillator, and therefore, the output waveform of the CCD linear image sensor is distorted. There was a problem that occurs.

The present invention has been made to solve the above problem, and has as its object to reduce the influence of the two-pixel period noise.

[0031]

In order to achieve the above object, an image reading apparatus according to the present invention comprises:
Oscillating means for outputting a first clock having a frequency of, a frequency multiplying means for multiplying the first clock by a predetermined multiple and outputting a second clock having a second frequency; An image reading apparatus comprising: a generating unit that generates a third clock having a third frequency at a predetermined timing based on an image signal; and an imaging unit that is driven by the third clock to read an image and output an image signal. , First frequency = third frequency × 2 ⁿ (n
Is an integer of 0 or more).

In another image reading apparatus according to the present invention, an oscillating means for outputting a first clock having a first frequency, and a second frequency obtained by multiplying the first clock by a first multiple. Frequency multiplying means for outputting a second clock having: a third clock based on the second clock;
Generating means for generating a third clock having a predetermined frequency at a predetermined timing; imaging means driven by the third clock to read an image and outputting an image signal; and generating an image signal of the third frequency from the image signal. Detecting means for detecting a level of noise having a frequency of 1/2 ⁿ (n is an integer of 1 or more); comparing means for comparing the detection result of the detecting means with a predetermined level; Control means for switching the frequency multiplier of the frequency multiplier means to the second multiple and then switching to the first multiple again.

Further, in the image reading method according to the present invention, an oscillating procedure for outputting a first clock having a first frequency, and a second step of multiplying the first clock by a predetermined multiple and having a second frequency. And a third frequency that satisfies a relationship of first frequency = third frequency × 2 ⁿ (n is an integer of 0 or more) based on the frequency multiplication procedure of outputting the second clock and the second clock. A generation procedure for generating a third clock at a predetermined timing and a reading procedure for driving an imaging unit with the third clock to read an image and output an image signal are provided.

In another image reading method according to the present invention, an oscillating procedure of outputting a first clock having a first frequency, and a step of multiplying the first clock by a first multiple to obtain a second frequency A frequency multiplying procedure for outputting a second clock having: a third clock based on the second clock;
Generating a third clock having a predetermined frequency at a predetermined timing; driving the imaging means with the third clock to read an image and outputting an image signal; and generating the third clock from the image signal. 1/2 of the frequency of
a detection procedure for detecting a level of a noise having a frequency of ⁿ (n is an integer of 1 or more), a comparison procedure for comparing the detection result of the detection means with a predetermined level, and when the detection result is larger than the predetermined level. , A control procedure for switching the first multiple to the second multiple, and then performing a control for switching again to the first multiple.

In the storage medium according to the present invention,
An oscillation process for outputting a first clock having a first frequency, a frequency multiplication process for multiplying the first clock by a predetermined multiple, and outputting a second clock having a second frequency; The first frequency =
A generating process of generating a third clock having a third frequency satisfying a relationship of a third frequency × 2 ⁿ (n is an integer of 0 or more) at a predetermined timing, and driving the imaging unit with the third clock And a program for executing a reading process for reading an image and outputting an image signal.

As described above, in another storage medium according to the present invention, an oscillating process of outputting a first clock having a first frequency, and multiplying the first clock by a first multiple to obtain a second frequency A frequency multiplying process for outputting a second clock having the following, a generating process for generating a third clock having a third frequency at a predetermined timing based on the second clock, and imaging using the third clock. A reading procedure for driving the means to read an image and output an image signal;
From the image signal, 1/2 ^{n of} the third frequency (n is 1
A detection process for detecting a level of noise having a frequency of (the integer above), a comparison process for comparing the detection result of the detection process with a predetermined level, and the first process when the detection result is larger than the predetermined level. A program for executing a control process of switching the multiple to the second multiple and then performing a control to switch the multiple again to the first multiple is stored.

[0037]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of an image reading apparatus according to a first embodiment of the present invention, and portions corresponding to FIG. 6 are denoted by the same reference numerals, and redundant description will be omitted. FIG.
Is obtained by adding two-pixel period noise filters 101 and 102 for detecting two-pixel period noise to the conventional example of FIG. Further, the CPU 103 is illustrated.

In FIG. 1, A / D converters 1009, 1
CCD linear image sensor 10 output from 035
Digital data corresponding to the odd-numbered pixel output and the even-numbered pixel output of 00 are input to the image processing circuit 1010,
It is also input to the two-pixel periodic noise filters 101 and 102. The configuration and operation of the two-pixel periodic noise filter will be described later. The CPU 103 controls the entire circuit, and sets the frequency division ratio of the frequency divider 1021 of the timing generation circuit 1016, sets the waveform of each pulse, delays, and sets ON / OFF.

The CCD linear image sensor 1000 is
In the present embodiment, it is driven at 25 MHz (third frequency). The oscillation frequency (first frequency) of the crystal oscillator 1017 is 12.5 MHz, and the frequency divider 1021
Is set to 1/8 by the CPU 103, and VC
The oscillation frequency (second frequency) of the O circuit 1019 is 12.
5 MHz × 8 = 100 MHz. Further, as in the conventional example, the generation pattern of the two-pixel periodic noise is (A) to
There are eight patterns (H).

FIG. 2 is a block diagram showing a detailed configuration of a portion indicated by area X in FIG. In FIG. 2, an analog image signal is converted into 8-bit digital data by an A / D converter 1009, and is converted into a D-type flip-flop 20.
Data delayed by one clock at 1 (hereinafter, DFF) and data not delayed are input to the DFFs 202 and 203, respectively.

The A / D converter 1009 and the DFF 201
While driven at 25 MHz, which is equal to the driving frequency of the CD linear image sensor 1000, the DFF 202,
203 is latched at a frequency of 1/2 at 12.5 MHz. Accordingly, adjacent pixel signals are output from the DFFs 202 and 203 in the same phase. After the signals output from the DFFs 202 and 203 are subjected to a subtraction process in a subtractor 204, an absolute value is obtained in an absolute value detection circuit 205.
This absolute value corresponds to a two-pixel cycle noise level.

The output of the absolute value detection circuit 205 is
6 and is compared with reference data 207 for two-pixel cycle noise occurrence determination which is set in advance by the CPU 103, and the comparison result is sent to the CPU 103. The CPU 103 determines that the comparison result of the comparator 206 is 2
If it is determined that there is no pixel cycle noise, it is determined that the system is normal, and control for removing noise is not performed.

If the output of the absolute value detection circuit 205 is larger than the reference data 207 and it is determined that there is a two-pixel period noise, the pulse output from the timing generation circuit 1016 is destroyed on the side to which the pulse is supplied by latch-up or the like. So that there is no Hi level or Lo
After fixing to a level or controlling to a high impedance state, any one of the following four controls (1) to (4) or a combination of these controls is performed. The means for fixing the pulse is not limited in the present invention.

(1) The frequency division ratio of the frequency divider 1021 is switched to 1/4 or 1/2, and is again set to 1/8. (2) The frequency division ratio of the frequency divider 102 is switched to 1/16 or 1/32 and set again to 1/8. (3) Stop the oscillation of the VCO circuit 1019 and restart it. (4) Stop the counter 1020 and restart it.

The above (1) to (4) are all performed by the VCO circuit 10
19, or after the oscillation frequency is switched, that is, the CCD linear image sensor 100
After changing the substantial driving stop or driving frequency of 0,
This is the operation of setting the frequency again. By performing this operation, the start point of the counter 1020 is reset, and as a result, the
The phase relationship between the output frequency 17 and the φ1B pulse is switched.

In the state newly set as described above, the two-pixel cycle noise filters 101 and 102 are again used.
Is determined for the two-pixel cycle noise by the comparator 206.
The operation is repeated until the result of the comparison with the reference data 207 is OK.

In FIG. 1, a two-pixel period noise filter is provided for each of even-numbered pixel outputs and odd-numbered pixel outputs.
The determination of the presence / absence of two-pixel period noise is determined by the logical sum or logical product of both. The operation described above is
This is performed when the device is started.

Next, a second embodiment of the present invention will be described. 3 and 4 show the conventional example of FIG. 6 in which the driving frequency of the CCD linear image sensor 1000 is 25 MHz, the oscillation frequency of the crystal oscillator 1017 is 25 MHz, and the frequency divider 1
021, the output waveform of the CCD linear image sensor 1000 and the differential amplifiers 1006, 1001,
032 shows the output waveform.

FIG. 3 shows the output of the crystal oscillator 1017 and φ1B
The clock generation circuit 101 shows the phase relationship with the pulse.
Since the clock multiplication number of 6 is 4 times, there are four types of phase relationships (I) to (L). FIG. 4 (I)-
(L) shows the output waveform of the CCD linear image sensor 1000 corresponding to (I) to (L) in FIG. 3. The noise affecting the φ1B pulse from the crystal oscillator 1017 is equal to the driving frequency of the CCD linear image sensor 1000. Therefore, the waveform of each pixel output is equal in any type.

Therefore, the output of the differential amplifier shown in FIG. 5 does not generate two-pixel period noise in any type.
However, since the noise pattern for the CCD output waveform is different, each type has a difference in DC level with respect to the reference level.

Although not shown, the crystal oscillator 10
17 output is 50 MHz, and the frequency division ratio of the frequency divider 1021 is 1
/ 2, when the driving frequency of the CCD linear image sensor 1000 is 25 MHz, the noise exerted by the output of the crystal oscillator 1017 on the CCD output waveform is equal for each pixel, so that no two-pixel period noise is generated.

Therefore, according to the present embodiment, in general, if the relationship of first frequency = third frequency × 2 ⁿ (n is an integer of 0 or more) is satisfied, two-pixel periodic noise is generated. Will not do.

Next, a storage medium according to the present invention will be described. The system according to each embodiment shown in FIGS.
It may be configured as hardware, or may be configured as a computer system including the CPU 103 and a memory.
When configured in a computer system, the memory forms a storage medium according to the present invention. The storage medium stores a program for executing the processing for controlling the operation described above.

As the storage medium, ROM, R
Semiconductor memory such as AM, optical disk, magneto-optical disk,
A magnetic storage medium or the like may be used, and these may be a CD-ROM,
The present invention may be applied to an FD, a magnetic card, a magnetic tape, a nonvolatile memory card, or the like.

Therefore, this storage medium can be used in a system or apparatus other than the system according to each of the above-described embodiments, and the system or computer can read out and execute the program code stored in this storage medium to execute the above-described processing. The same functions as those of the embodiments described above can be realized, the same effects can be obtained, and the object of the present invention can be achieved.

An OS running on a computer
When performing part or all of the processing, or after the program code read from the storage medium is written to a memory provided in an extended function board or an extended function unit connected to the computer, Even when the CPU or the like provided in the above-mentioned extended function board or extended function unit performs a part or all of the processing based on the instruction of the program code, the same functions as those of the embodiments can be realized and the same effects can be obtained. Can be obtained, and the object of the present invention can be achieved.

[0057]

As described above, according to the present invention,
In an image reading apparatus having a timing generation circuit having a multiplying function using a PLL circuit or the like, it is possible to effectively suppress the generation of noise at a period of 2 ⁿ pixels.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an image reading device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a pixel period noise filter according to the first embodiment.

FIG. 3 is a timing chart showing a phase relationship between a φ1B pulse and a crystal oscillator output according to a second embodiment of the present invention.

FIG. 4 is an output waveform diagram of a CCD linear image sensor according to a second embodiment.

FIG. 5 is an output waveform diagram of the differential amplifier according to the second embodiment.

FIG. 6 is a configuration diagram of a conventional image reading device.

FIG. 7 is a configuration diagram of a CCD linear image sensor.

FIG. 8 is an ideal output waveform diagram of a CCD linear image sensor.

FIG. 9 is a timing chart showing a phase relationship between a φ1B pulse and a crystal oscillator output in a conventional example.

FIG. 10 is an output waveform diagram of a conventional CCD linear image sensor.

FIG. 11 is an output waveform diagram of a conventional differential amplifier.

[Explanation of symbols]

 101, 102 2-pixel periodic noise filter 103 CPU 201, 202, 203 DFF 204 Subtraction circuit 205 Absolute value detection circuit 206 Comparator 207 Reference data 1000 CCD linear image sensor 1016 Timing generation circuit 1017 Crystal oscillator 1018 PC circuit 1019 VCO circuit 1020 Counter 1021 frequency divider 1022 φ1 pulse generation block 1033 φ2 pulse generation block 1024 φ1B pulse generation block

Claims (18)

[Claims] An oscillator for outputting a first clock having a first frequency; and a frequency multiplier for multiplying the first clock by a predetermined multiple and outputting a second clock having a second frequency. Generating means for generating a third clock having a third frequency based on the second clock at a predetermined timing; and imaging means driven by the third clock to read an image and output an image signal An image reading apparatus comprising: a first frequency = a third frequency × 2 ⁿ (n is an integer of 0 or more). 2. An oscillating means for outputting a first clock having a first frequency, and a frequency multiplier for multiplying the first clock by a first multiple and outputting a second clock having a second frequency. Means, a generating means for generating a third clock having a third frequency at a predetermined timing based on the second clock, and an imaging device driven by the third clock to read an image and output an image signal Means, か らⁿ (n is 1) of the third frequency from the image signal.
Detecting means for detecting the level of noise having a frequency of (integer above); comparing means for comparing the detection result of the detecting means with a predetermined level; when the detection result is larger than the predetermined level, the frequency multiplying means An image reading apparatus, comprising: a control unit that controls the multiplication factor of the second multiple to a second multiple, and then switches to the first multiple again. 3. The image pickup means outputs a plurality of image signals for the read image, and the detection means and the comparison means perform the detection and comparison for each of the plurality of image signals, and 3. The image reading apparatus according to claim 2, wherein the means performs the control when at least one of the detection results is larger than the predetermined level. 4. An image reading apparatus according to claim 2, wherein said control means substantially stops said third clock prior to performing said control. 5. An image reading apparatus according to claim 2, wherein said control means repeatedly performs said control until said detection result becomes smaller than a predetermined level. 6. The image pickup device according to claim 1, wherein the image pickup means outputs two image signals for every other pixel of the image by being driven by the two third clocks having different phases. Item 3. The image reading device according to Item 3. 7. An oscillation procedure for outputting a first clock having a first frequency, and a frequency multiplication procedure for multiplying the first clock by a predetermined multiple and outputting a second clock having a second frequency. And a third clock having a third frequency satisfying a relationship of first frequency = third frequency × 2 ⁿ (n is an integer of 0 or more) based on the second clock at a predetermined timing. An image reading method, comprising: a generating step of generating an image; and a reading step of driving an image pickup unit with the third clock to read an image and output an image signal. 8. An oscillation procedure for outputting a first clock having a first frequency, and a frequency multiplication for multiplying the first clock by a first multiple and outputting a second clock having a second frequency. A generating procedure for generating a third clock having a third frequency based on the second clock at a predetermined timing; and driving an image pickup unit with the third clock to read an image and generate an image signal. A reading procedure for outputting, and か らⁿ (n is 1) of the third frequency from the image signal.
A detection procedure for detecting a level of noise having a frequency of the above integer), a comparison procedure for comparing the detection result of the detection procedure with a predetermined level, and when the detection result is larger than the predetermined level, the first A control procedure for switching the multiple to the second multiple, and then performing control to switch the multiple again to the first multiple. 9. The image pickup means outputs a plurality of image signals for a read image. The detecting step and the comparing step perform the detection and comparison for each of the plurality of image signals, and 9. The image reading method according to claim 8, wherein the control is performed when at least one of the detection results is larger than the predetermined level. 10. The image reading method according to claim 8, further comprising a step of substantially stopping the third clock prior to performing the control according to the control procedure. 11. The image reading method according to claim 8, wherein in the control procedure, the control is repeatedly performed until the detection result becomes smaller than a predetermined level. 12. The image pickup means according to claim 2, wherein the image pickup means outputs two image signals for every other pixel of the image by being driven by the two third clocks having different phases. Item 10. The image reading method according to Item 9. 13. An oscillation process for outputting a first clock having a first frequency, and a frequency multiplication process for multiplying the first clock by a predetermined multiple and outputting a second clock having a second frequency. And a third clock having a third frequency satisfying a relationship of first frequency = third frequency × 2 ⁿ (n is an integer of 0 or more) based on the second clock at a predetermined timing. A computer-readable storage medium storing a program for executing a generation process of generating, and a reading procedure of driving an imaging unit with the third clock to read an image and output an image signal. 14. An oscillation process for outputting a first clock having a first frequency, and a frequency multiplication for multiplying the first clock by a first multiple and outputting a second clock having a second frequency. Processing, generating a third clock having a third frequency at a predetermined timing based on the second clock, driving an imaging unit with the third clock to read an image, and generating an image signal. Reading processing to be output, and か らⁿ (n is 1) of the third frequency from the image signal.
A detection process for detecting a level of noise having a frequency of (the above integer), a comparison process for comparing the detection result of the detection process with a predetermined level, and when the detection result is larger than the predetermined level, the first A computer-readable storage medium storing a program for executing a control process of switching a multiple to a second multiple and then performing a control to switch the multiple again to the first multiple. 15. The image pickup means for outputting a plurality of image signals for a read image, wherein the detection processing and the comparison processing perform the detection and the comparison for each of the plurality of image signals. 15. The computer-readable storage medium according to claim 14, wherein the control is performed when at least one of the detection results is larger than the predetermined level. 16. The program according to claim 1, wherein a process of substantially stopping the third clock is provided in the program prior to performing the control by the control process.
4. The computer-readable storage medium according to claim 4. 17. The computer-readable storage medium according to claim 14, wherein the control process repeatedly performs the control until the detection result becomes smaller than a predetermined level. 18. The image pickup device according to claim 18, wherein the image pickup means outputs two image signals for every other pixel of the image by being driven by the two third clocks having different phases. Item 16. A computer-readable storage medium according to item 15.