KR0141783B1 - Sampling seed conversion circuit of digital tv - Google Patents

Abstract

The present invention relates to a sampling rate conversion circuit of a digital TV. In the conventional non-standard signal detection method, an analog function up to hardware demodulation and color demodulation according to standard / non-standard detection has to be added. The cost of manufacturing increases due to the addition of analog functions and a circuit for digitally converting each component signal.In addition, the analog sampling rate conversion method uses a plurality of A / D and D / As, resulting in a price increase problem and A / D, D. There is a problem that the degradation of the image quality due to the low pass filter used for / A processing is inevitable. To improve this point, the present invention repeatedly outputs digital data components processed by the burst lock clock whenever the line lock clock is one clock faster than the burst lock clock when the line lock clock is faster than the burst lock clock. When it is slower than the burst lock clock, it is configured to skip the digital data component processed by the burst lock clock whenever the burst lock clock is one clock faster than the line lock clock. The present invention can adjust the timing of the write clock and the read clock. The TV can be used when the clocks of the composite video signal processing circuit and the component signal processing circuit are different, and the simple structure can reduce the manufacturing cost.

Description

Digital TV's Sampling Rate Conversion Circuit

1 is a block diagram of a conventional digital TV standard / nonstandard signal detection circuit.

2 is a block diagram of a conventional analog / standard signal processing circuit.

3 is a block diagram of a sampling rate conversion circuit of the present invention.

4 is a circuit diagram of a write address generator in FIG.

5 is a circuit diagram of an address correction unit in FIG.

6 is a circuit diagram of a buffer memory in FIG.

FIG. 7 is an operational waveform diagram of FIG.

* Explanation of symbols for main parts of the drawings

One; Buffer memory 2; Write address generator

3; A read address generator 4; Address correction unit

11; Decoders 12-1 to 12-8, 14, 15, 47, 48; register

13; Multiplexers 21, 22, 44, 46, 50, 51, 54, 55; Deflip-flop

23, 43, 45, 52, 56; Inverters 24, 27, 41, 42; And gate

25; Oragates 26, 50, 54; counter

49; Comparators 53, 57; Nandgate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing adjustment technique of a burst lock clock / line lock clock for nonstandard TV signal processing. The present invention relates to a digital TV's sampling rate converting circuit which converts the number of pixels constant during one line period so as not to occur.

Current TV signals can be classified into standard NTSC signals with accurate NTSC format and non-standard NTSC signals such as VCR signals.

Here, in the non-standard signal, the frequency relationship between the horizontal synchronization signal and the color carrier signal does not satisfy the following equation (1).

fsc = 455/2 * f _H ...... (1)

fsc = 3.58 MHz (color carrier frequency)

f _H = 15.75KHz (scan line frequency)

Accordingly, in the case of non-standard signals, a large deterioration in image quality does not occur in an existing analog TV system, but in a digital TV performing digital signal processing, a large deterioration in image quality may occur depending on a clock used.

That is, the clock signal used for the TV is a burst lock clock (BL-CLK) fixed to the color burst signal and a line lock clock (LL-CLK) fixed to the horizontal synchronization signal. If you perform digital TV signal processing with (DOUBLER), etc., signal processing according to the burst lock clock (BL-CLK) will yield relatively good results in Y / C separation and color demodulation, but will be line doubling for non-standard signals. ), A large image quality deterioration occurs with the screen shaking.

On the other hand, if the signal processing is performed according to the line lock clock (LL-CLK), a good result is obtained in the line multiplexing process, but a large image quality deterioration occurs in which the color signal cannot be obtained in the luminance / color separation and the color demodulation processing for the non-standard signal. .

To solve this problem, the digital TV system changes the signal processing path to the non-standard signal detection result, and uses the burst lock clock (BL-CLK) in the luminance / color separation and color demodulation process, and the line lock clock after the color demodulation. (LL-CLK) and Burst Lock Clock (BL-CLK) to perform the sampling rate conversion (SRC) process that makes an association between the signal processed signal and the line lock clock (LL-CLK). use.

FIG. 1 is a block diagram of a conventional digital TV standard / non-standard signal processing circuit, and as shown therein, a standard / non-standard signal detector 101 for detecting a standard / non-standard signal by checking a composite video signal, and a composite video signal. A burst lock clock generator 102 for receiving a phase-corrected burst lock clock, a line lock clock generator 103 for receiving a composite video signal and outputting a phase-locked line lock clock, and the standard / non-standard detection unit ( A switching unit 104 which selects one of the outputs of the burst lock clock generator 102 and the line lock clock generator 103 according to the output of the output signal to the system clock SCLK, and a line delay of the composite video signal. The line comb filter 105 for outputting the non-standard signal by the application of the standard signal and the non-standard signal of the comb filter 105 according to the output of the standard / non-standard signal detector 101. A switching unit 106 for selecting me, a switching unit 107 for selecting one of the luminance signal and the output of the switching unit 106 according to the control signal CTL, and an output of the switching unit 107 An analog / digital converter 108 for converting, a luminance separator 109 for separating the luminance signal from the output of the analog / digital converter 108, and a line interpolator for line interpolating the output of the luminance separator 109 ( 110, a digital to analog converter 111 for converting the output of the line interpolator 110, and the output of the standard signal and the line comb filter 105 in accordance with the output of the standard / non-standard signal detector 101. A switching unit 112 for selecting one of the non-standard signals, a switching unit 118 for selecting one of the color signal and the output of the switching unit 112 according to a control signal, and a predetermined band of the output of the switching unit 118 A band pass filter 114 for passing only components and the band pass A modulator 115 for demodulating the output of the filter 114, an analog / digital converter 116 for digitally converting the output of the modulator 115, and a color signal for separating the color signal from the output of the analog / digital converter 116. A color signal separator 117, a line interpolator 118 for interpolating the output of the color signal separator 117, a digital-to-analog converter 119 for analog-converting the output of the line interpolator 118, and And a color signal processor 120 for processing the outputs of the digital / analog converters 111 and 119 to output the color signals R, G, and B.

Referring to the operation of the conventional circuit is as follows.

Standard / Non-standard signal detector when composite video signal is input so that burst lock clock generator 102 generates burst lock clock (BL-CLK) and line lock clock generator 103 generates line lock clock (LL-CLK) When the 101 checks the composite video signal and determines whether it is an input of a standard signal and a non-standard signal, and outputs a detection signal accordingly, the switching unit 104 outputs the burst lock clock generator 102 and the line lock clock generator. One of the outputs of the 103 is selected and output to the system clock SCLK.

At this time, if the line comb filter 105 outputs the non-standard signal by delaying the composite video signal, the switching unit 106 outputs the standard signal and the line comb filter 105 according to the output of the standard / non-standard signal detector 101. Select and output one of the non-standard signals of the < RTI ID = 0.0 >) < / RTI > and the switching unit 107 selects and outputs one of the luminance signal Y and the output of the switching unit 106 according to the control signal CTL. The output of is digitally converted via an analog / digital converter 108.

Accordingly, when the luminance separator 109 separates the luminance signal from the output of the analog / digital converter 108, the line interpolator 110 interpolates the line and the line interpolated signal is passed through the digital / analog converter 110. Analog conversion

When the line comb filter 105 outputs the non-standard signal, the switching unit 112 selects one of the standard signal and the non-standard signal of the line comb filter 105 according to the output of the standard / non-standard signal detector 101. The switching unit 113 selects and outputs one of the color signal C and the output of the switching unit 112 according to the control signal CTL, and the output of the switching unit 113 passes through the band pass filter 114. Only predetermined band components are output.

At this time, the output of the band pass filter 114 is demodulated to the original signal in the demodulator 115 and the output of the demodulator 115 is converted into a digital signal through the analog-to-digital converter 116.

Accordingly, when the color signal separator 117, which receives the output of the analog / digital converter 116, separates the color signal C, the line interpolation is performed through the line interpolator 119, and the line interpolated signal is converted into a digital / analog converter. 119) is converted into an analog signal.

Therefore, the color signals R, G, and B are output from the color signal processor 120 which has processed the outputs of the digital / analog converters 111 and 119 by image processing.

Here, the system clock (SCLK) provided to the analog / digital converters 108 and 116 and the digital / analog converters 111 and 119 is used as a burst lock clock (BL-CLK) in the case of a standard signal and is a non-standard signal. In this case, use the line lock clock (LL-CLK).

At this time, in the case of the standard signal, the input composite video signal is digitally converted to the burst lock clock (BL-CLK) and burst after signal processing using a memory such as moving adaptive luminance / color separation and moving adaptive scan line interpolation. Analog conversion is performed by the lock clock (BL-CLK).

In the case of non-standard signals, luminance / color separation and color demodulation are performed in an analog manner, and the component signals are digitally converted into a line lock clock (LL-CLK), followed by motion adaptive line interpolation, and then a line lock clock ( LL-CLK).

2 is a standard / non-standard signal processing circuit diagram of a conventional analog method, as shown therein, an analog-to-digital converter 121 for digitally converting an analog composite video signal according to the bus-lock clock BL-CLK, and the analog The video processor 122 performs color demodulation after performing luminance separation according to the burst lock clock BL-CLK of the digital converter 121, and outputs the video processor 122 to the burst lock clock BL-. A digital-to-analog converter 123 that performs analog conversion according to CLK), an analog-to-digital converter 124 that digitally converts the output of the digital / analog converter 123 according to the line lock clock (LL-CLK), and A memory 125 for temporarily storing the output of the analog / digital converter 124 according to the line lock clock LL-CLK to perform line interpolation, and a digital-to-analog converter for analog-converting the output of the memory 125 ( 126) It consists of.

The digital / analog converter 123 and the analog / digital converter 124 are configured by three and operate as analog sampling rate converters.

The operation of such a conventional circuit is described as follows.

First, when an analog composite video signal is input, the analog-to-digital converter 121 performs digital conversion according to the burst lock clock BL-CLK, and the digital signal is converted from the video processor 122 to the burst lock clock BL-CLK. After the luminance / color separation, a color demodulation process is performed.

Here, the luminance, I, and Q signals, which are the color demodulated component signals in the video processor 122, are converted into analog signals by the three digital / analog converters 123 according to the burst lock clock BL-CLK.

At this time, the output of the digital-to-analog converter 123 is digitally converted by the three analog / digital converters 124 according to the line lock clock (LL-CLK), and the digital signal is converted into the line lock clock (LL) in the memory 125. The line is doubled by being stored and output according to -CLK).

Accordingly, the output of the memory 125 is analog-converted by the digital-to-analog converter 126 according to the line lock clock LL-CLK and output.

However, conventionally, in the case of non-standard signal detection, an analog function up to hardware demodulation and color demodulation according to standard / non-standard detection has to be added. There is a problem that the manufacturing cost increases due to the complexity.

In addition, the analog sampling rate conversion method uses a plurality of A / Ds and D / As (for example, a circuit like FIG. 2 requires four A / Ds and six D / As), thereby increasing price and There was a problem that the image quality deterioration (resolution deterioration) of the signal due to the low pass filter used for / D, D / A processing is inevitable.

The present invention repeatedly outputs the digital data component processed by the burst lock clock whenever the line lock clock is one clock faster than the burst lock clock in order to improve the conventional problem as described above. To provide a digital TV sampling rate conversion circuit designed to skip digital data components processed by the burst lock clock whenever the line lock clock is one clock faster than the line lock clock. have.

The present invention provides write address generation means for generating a write address in accordance with the burst lock clock BL-CLK, and read address generation for generating a read address in accordance with the line lock clock LL-CLK. And address correction means for controlling the write address generating means and the read address generating means to correct the address, storing digital data of luminance / color separation and color demodulation according to the output of the write address generating means, and storing the read address. And a buffer memory for outputting the stored data in accordance with the output of the generating means.

Hereinafter, with reference to the accompanying drawings of the present invention will be described.

3 is a block diagram of an embodiment of the present invention. As shown in FIG. 3, the composite video signal is digitally converted, luminance separation and color demodulation are performed, and the digital video signal having timing adjustment is analog-converted, followed by color processing. In the digital TV outputted as a WB, a write address generator 2 for generating a write address in accordance with the burst lock clock BL-CLK and a read address generator for generating a read address in accordance with the line lock clock LL-CLK. (3), an address correcting unit 4 for controlling the write address generating unit 2 and the read address generating unit 3 to correct an address, and luminance / depending in accordance with the output of the write address generating unit 2; The buffer memory 1 stores color separated and color demodulated digital data and outputs stored data in accordance with the output of the read address generator 3.

As shown in FIG. 4, the write address generator 2 includes a de-flip flop 21 for outputting the reset signal RST latched in accordance with the burst lock clock BL-CLK, and the de-flip. An inverter 23 for inverting the output of the flop 21, a deflip-flop 22 for holding the output of the deflip-flop 21 in accordance with the burst lock clock BL-CLK, and the flip-flop (22) and an AND gate 24 for ANDing the output of the inverter 23, and enabled by an address correction pulse WA to perform a count operation in accordance with the burst lock column BL-CLK to perform a write address. The counter 26 is generated by ORing the counter 26 for generating BC0, the AND gate 27 for ANDing the output of the counter 26, and the outputs of the AND gates 24, 27. It consists of the orifice 25 to be reset.

The read address generator 3 is configured similarly to the write address generator 2 so as to generate the read address LC0 when calculating the line lock clock LL-CLK and the address correction pulse RA.

As shown in FIG. 5, the address correction section 4 includes an AND gate 41 for outputting the write enable signal LEN by ANDing the upper two bits of the read addresses LC0 [3: 0]. And AND gate 42 for outputting the write enable signal BEN by ANDing the upper two bits of the write address BC0 [3: 0], the burst lock clock BL-CLK and the line lock clock LL-. Inverters 45 and 43 for inverting CLK, respectively, and a deflip-flop for holding the read address LC0 [3] in accordance with the output of the inverter 45 to output the most significant bit address MSBBC0. 46, a deflip-flop 44 for holding the read address LC0 [3] according to the output of the inverter 43 and outputting the most significant bit addresser MSBLC0, and the deflip-flop 46. A register 47 for temporarily storing the write address BC0 [3: 0] in accordance with the output MSBBC0 of the read address, and a read address LC0 [in accordance with the output MSBCL0 of the deflip-flop 46. 3: 0]), the comparator 49 for comparing the output of the registers 47 and 48 and the output LEN of the AND gate 41 are temporarily enabled. A deflip-flop 50 for holding the output terminal AB signal of the comparator 49 in accordance with the line lock clock LL-CLK, and an output of the deflip-flop 50 for the line lock clock LL-CLK. The flip-flop 51 to be held according to the < RTI ID = 0.0 > and / or < / RTI > the inverter 52 for inverting the output of the flip-flop 51, the output of the inverter 52 and the output of the flip-flop 50 The NAND gate 53 for outputting the read address correction pulse RA in logical combination and the output BEN of the AND gate 42 are enabled, and the comparator 49 according to the burst lock clock BL-CLK. A deflip-flop 54 for holding an output terminal (AB) signal, a deflip-flop 55 for holding the output of the def-flop 54 in accordance with the burst lock clock BL-CLK, and the deflip The output of the flop 55 An inverter 56 for inverting, and a NAND gate 57 for logically combining the output of the inverter 56 and the output of the deflip-flop 54 and outputting them as write address correction pulses WA.

As shown in FIG. 6, the buffer memory 1 has a decoder 11 for decoding the write address BC0 [3: 0] and an output of the decoder 11 to enable the burst lock clock ( Registers 12-1 to 12-8 for storing digital input data according to BL-CLK) and the lower 3 bits of read address LC0 [3: 0] according to the line lock clock LL-CLK. Four three-bit registers 14, a multiplexer 13 for selecting a corresponding output among the registers 12-1 to 12-8 according to the output of the register 14, and a line lock clock (LL-CLK). ), And selects the output of the multiplexer 13 and outputs it as a digital signal.

The reason that the signal processing is possible with the above configuration is that the video signal has a high correlation in the horizontal direction, so even if the current pixel component is replaced or removed by a neighboring pixel component, the general viewer does not detect it and a non-standard signal such as a V-C signal. This is because the signal does not show a difference of more than three clocks in one scan period when the burst lock clock has a 4fsc frequency and the line lock clock has a 910f _H frequency.

Referring to the operation and effect of the present invention configured in this way in detail as follows.

The present invention will be described by taking an example where the length of the buffer memory 1 is '8'.

First, when an analog composite video signal is input to digital TV and digitally converted, the write address generator 2 counts the counters 26 enabled by the address correction pulse WA according to the burst lock clock BL-CLK. An operation is performed to output the write address BC0 to the buffer memory 1.

At this time, the write address generator 2 holds the reset signal RST in response to the burst lock clock BL-CLK and the de-flop flop 21 is inverted by the inverter 23. The flip-flop 22 holds the output of the de-flop 21 according to the burst lock clock BL-CLK.

Then, when the AND gate 24 ANDs the outputs of the inverter 23 and the flip-flop 22, or when the AND gate 27 ANDs the output of the counter 26, the oragate 25 is The output of the AND gates 24 and 27 is logic to output the reset signal to the counter 26.

Accordingly, when the reset pulse RST, which is a horizontal sync pulse, becomes high, or the write address BC0 becomes '15 (= 1111) ', the output of the AND gate 27 becomes high, Whenever the output of 25) becomes high and the output of this orifice 25 becomes high, the counter 26 which performs the counting operation from '0 to 15' is reset to zero.

Here, the counter 26 performs a normal counting operation when the light correction pulse WA connected to the clock enable stage is high, but maintains the previous output value when the light correction pulse WA is low.

Accordingly, the write address generator 2 outputs the write address BC0 to the buffer memory 1 by the counter operation by the counter 26 being enabled by the write address correction pulse WA. The counter 26 ) Is reset when the horizontal sync pulse becomes high or whenever the write address BC0 becomes 1111 to repeat the counting operation of the address.

Also, the read address generator 3 is configured in the same manner as the write address generator 2 so that the counter 26 enabled by the address correction pulse RA performs counting operation according to the line lock clock LL-CLK. The read address LC0 is output to the buffer memory 1 by performing the operation.

On the other hand, the address correction unit 4 corrects the timings of the write address BC0 and the read address LC0 respectively generated by the write address generator 2 and the read address generator 3, and the address LC0 [ 3: 2]) (BC0 [3: 2]) are ANDed through the AND gates 41 and 42, respectively, and output as an address enable signal LEN (BEN) and the write address LC0 [3]. Is held by the deflip-flops 44 and 46 which clock the output of the inverters 43 and 45 which invert the line lock clock LL-CLK and the burst lock clock BL-CLK, respectively. Output is made to the addresser MSBLC0 (MSBBC0).

Here, the write enable signal BEN becomes high only when the upper two bits of the write address BC0 have high values of '12 (= 1100) to 15 (= 1111) 'and the read enable signal LEN. ) Becomes high only when the upper two bits of the read address LC0 have a value of '12 (= 1100) to 15 (= 1111) 'which are all high, and the flip-flop 44 which is the most significant bit address MSBLC0. Is a value obtained by taking the most significant bit of the 4-bit output LC0 of the read address generator 3 at the falling edge of the line lock clock LL-CLK and outputting the flip-flop 46 which is the most significant bit address MSBBC0. Is a value obtained by taking the most significant bit of the 4-bit output BC0 of the write address generator 2 at the falling edge of the burst lock clock BL-CLK.

At this time, the register 47 selects the write address BC0 [3: 0] from the rising edge of the most significant bit address MSBBC0, outputs it to the comparator 49, and the register 48 raises the rising edge of the most significant bit address MSBLC0. Selects a read address LC0 [3: 0] and outputs the comparator 49 to the comparator 49, the comparator 49 compares the outputs of the registers 47 and 48 so that the output of the register 47 becomes a register ( If it is larger than the output of 48), the output terminal AB is made high and if it is small, the output terminal AB is made high.

For example, when the output of the register 47 is 9 and the output of the register 48 is 8, the comparator 49 has the output terminal AB high and the output terminal AB low.

In the above, the value of the output terminal AB (AB) of the comparator 49 is high and the meaning of low means that the value of the write address BC0 is larger than the read address LC0 if the output of the output terminal AB is high. Since the burst lock clock (BL-CLK) is one clock ahead of the line lock clock (LL-CLK), it means that the data processed by the burst lock clock (BL-CLK) should be skipped. If the output of is high, it means that the line lock clock (LL-CLK) is one or more clocks faster than the burst lock clock (BL-CLK), which means that the data processed by the burst lock clock (BL-CLK) must be repeated. do.

Accordingly, when the write enable signal BEN is applied, the deflip-flop 54 holds the output terminal AB signal of the comparator 49 according to the burst lock clock BL-CLK, and this signal is the burst lock. When the flip-flop 55 is held in accordance with the clock BL-CLK, the inverter 56 inverts the output of the flip-flop 55 and the output of the inverter 56 and the flip-flop 54. The outputs are combined at the NAND gate 57 and output as the write address correction signal WA.

Therefore, the write address generator 2 corrects the write address BC0 according to the write address correction signal WA of the address correction unit 4 to control the write operation of the buffer memory 1.

In addition, when the read enable signal LEN is applied, the flip-flop 50 holds the output terminal AB signal of the comparator 49 according to the line lock clock LL-CLK, and this signal is the line lock clock. Holding in the flip-flop 51 and inverted in the inverter 52 according to (LL-CLK), the output of the inverter 52 and the output of the flip-flop 50 is combined in the NAND gate 53 The read address correction signal RA is output.

The reason why the flip-flops 50 and 54 store the output of the comparator 49 only when the write enable signal BEN and the read enable signal LEN are high, respectively, is the comparator 49. In order to store the output value of the stable output signal interval which the output of the transition does not transition to the said flip-flop (50) (54).

Accordingly, the read address generation unit 3 corrects the timing of the read address LC0 by the read address correction signal RA output from the address correction unit 4 to control the read operation of the buffer memory 1. do.

For example, when the burst lock clock BL-CLK is one clock ahead of the line lock clock LL-CLK, as shown in FIG. 7, the address beam information 4 is output terminal AB of the comparator 49. As shown in FIG. This high becomes high and the output RA of the NAND gate 53 always becomes high and the output WA of the NAND gate 57 goes low for one clock period from the P point to the burst lock clock BL-CLK. The read address generator 3 performs a normal count between 0 and 15, but the write address generator 2 repeatedly outputs the previous write address BC0 while the write address correction pulse WA is low.

At this time, in the buffer memory 1 in which 8 bits of digital data are simultaneously input to the registers 12-1 to 12-8, the write address BC0 [3: where the decoder 11 is input from the write address generator 2 is used. 0]) and the corresponding registers among the registers 12-1 to 12-8 enabled for the decoded signal store the input data according to the burst lock clock BL-CLK. The decoder 11 If the lower 3 bits of the write address BC0 inputted to '010' are registered, the register 12-6 is enabled to store data of the corresponding bit.

For example, when the write address BC0 is sequentially counted from 0 to 7 and input to the decoder 11, the input data is sequentially stored in the registers 12-8 to 12-1.

In addition, when four three-bit registers 14 output only the upper three bits of the read addresses LC0 [3: 0] according to the line lock clock LL-CLK, the multiplexer 13 outputs the registers 14. The output of the registers 12-1 to 12-8 is selected accordingly, and the register 15 holds and outputs the output of the multiplexer 13 in accordance with the line lock clock LL-CLK.

At this time, the digital data output to the register 15 is a form in which one pixel data of the input data is skipped.

That is, when the burst lock clock BL-CLK is earlier than the line lock clock LL-CLK, the data signaled by the burst lock clock BL-CLK is converted to the line lock clock LL. By skipping every one clock ahead of -CLK, the number of data to be treated as the line lock clock (LL-CLK) per line is always kept constant.

As shown in FIG. 7, if the line lock clock LL-CLK is one clock ahead of the burst lock clock BL-CLK, the write address BC0 is repeatedly output as 13 (= 1101). The input digital data is stored repeatedly in the register 12-3.

The reason why the read address LC0 is delayed by four clocks with respect to the line lock clock LL-CLK is that the write address BC0 when the write address BC0 and the read address LC0 have the same value and the value changes at about the same time. ) Is prevented from damaging the output data of the multiplexer 13 due to the collision of the "

For example, if the write address BC0 [2: 0] is' 101 'and the read address LC0 [2: 0] is' 101', the read address LC0 [2: 0] before 4 clocks is' Since 001 ', new input data is input to the sixth register 12-4, and the output of the multiplexer 13 becomes the output value of the second register 12-7.

In general, NTSC signals can be separated into luminance (Y) and color signal components (I, Q). Since the luminance component (Y) has a higher resolution than the color components (I, Q), data sampling rates of Y, I, and Q are usually higher. Uses 4: 2: 2.

Therefore, the clock speed used for the luminance signal processing and the clock speed used for the chrominance signal also have a relationship of 2: 1. You can do it.

That is, the present invention operating as described above inputs the I and Q signals to two buffer memories having a size of 1/2 with respect to luminance Y when applied to the Y, I and Q paths, and writes the buffer memories. In the address and read address stages, the upper three bits of the output of the write address generator for the luminance signal and the four bits of the read address generator may be input.

As described in detail above, the present invention can adjust the timing of the write clock and the read clock, so that the clocks of the composite video signal processing circuit and the component signal processing circuit can be used for different digital TVs. It can be applied, and the structure is simple, there is an effect that can reduce the manufacturing cost.

Claims (4)

In the digital TV which digitally converts a composite video signal, performs luminance separation and color demodulation, and converts a digital video signal whose timing is adjusted by analog, and outputs it as a primary color signal through color processing, to a burst lock clock (BL-CLK). Write address generating means for generating write address BC0, read address generating means for generating read address LC0 in accordance with line lock clock LL-CLK, and write address generating means and read address generating means. Address correction means for controlling and correcting timing of write and read addresses BC0 and LC0, and storing digital data of luminance / color separation and color demodulation according to the output BC0 of the write address generating means and storing the read address. And a buffer memory for outputting digital data in accordance with the output LC0 of the generating means. Digital TV sampling rate conversion circuit. 2. The counter of claim 1, wherein the write address generating means includes a counter 26 that is enabled by the address correction pulse RA and generates a write address BC0 by performing a counting operation according to the burst lock clock BL-CLK. An AND gate 27 for logically multiplying the output of the counter 26, a deflip-flop 21 for holding the reset signal RST in accordance with the burst lock clock BL-CLK, and the flip-flop 21 An inverter 23 for inverting the output of the < RTI ID = 0.0 >) < / RTI > and a deflip-flop 22 for holding the output of the deflip-flop 21 in accordance with the burst lock clock BL-CLK. And an or gate 24 for logically multiplying the output of the inverter 23 and the or gate 25 for resetting the counter 26 by ORing the outputs of the AND gates 24 and 27. Digital TV sampling rate conversion circuit, characterized in that. The read address generating means is configured in the same manner as the write address generating means so as to generate the read address LC0 by calculating the line lock clock LL-CLK and the address correction pulse WA. Digital TV sampling rate conversion circuit. 2. The buffer memory according to claim 1, wherein the buffer memory is enabled by the decoder 11 that decodes the write address BC0 [3: 0] and the output of the decoder 11 in accordance with the burst lock clock BL-CLK. Registers 12-1 to 12-8 for storing digital input data and four three-bit registers for storing the lower 3 bits of the read address LC0 [3: 0] according to the line lock clock LL-CLK. (14), the multiplexer 13 for selecting a corresponding output among the outputs of the registers 12-1 to 12-8 according to the output of the register 14, and the line lock clock LL-CLK. A digital TV sampling rate converting circuit comprising: a register (15) for selecting an output of the multiplexer (13) and outputting a digital signal.