KR960013024A - Digital TV's Sampling Rate Conversion Circuit - Google Patents

Abstract

The present invention relates to a sampling rate conversion circuit of a digital TV. In the conventional non-standard signal detection method, an analog function up to hardware demodulation and color demodulation according to standard / non-standard detection has to be added. The cost of manufacturing increases due to the addition of analog functions and a circuit for digitally converting each component signal. Also, the analog sampling rate conversion method uses a plurality of A / D and D / A. There was a problem that the image degradation of the signal due to the low pass filter used for the D / A processing is inevitable. To improve this point, the present invention repeatedly outputs digital data components processed by the burst lock clock whenever the line lock clock is one clock faster than the burst lock clock when the line lock clock is faster than the burst lock clock. When it is slower than the burst lock clock, it is configured to receive digital data components processed by the burst lock clock whenever the burst lock clock is one clock faster than the line lock clock. The present invention can adjust the timing of the write clock and the read clock. The TV can be used when the clocks of the composite video signal processing circuit and the component signal processing circuit are different, and the simple structure can reduce the manufacturing cost.

Description

Digital TV's Sampling Rate Conversion Circuit

As this is a public information case, the full text was not included.

3 is a block diagram of a sampling rate converting circuit of the present invention.

4 is a circuit diagram of a write address generator in FIG.

5 is a circuit diagram of an address correction unit in FIG.

Claims (4)

In the digital TV which digitally converts a composite video signal, performs luminance separation and color demodulation, and converts a digital video signal whose timing is adjusted by analog, and outputs it as a primary color signal through color processing, to a burst lock clock (BL-CLK). The write address generating means for generating the write address BCO, the read address generating means for generating the read address LCO in accordance with the line lock clock LL-CLK, and the write address generating means and the read address generating means. Address correction means for controlling the timing of write and read address BCO LCO, and digital data according to luminance / color separation and color demodulated LCO according to the output BCO of the write address generating means. A digital TV sampling rate conversion circuit, comprising a buffer memory for outputting The counter of claim 1, wherein the write address generating means includes a counter (26) which is enabled by the address correction pulse (RA) and generates a write address (BCO) by performing a counting operation according to the burst lock clock (BL-CLK), An AND gate 27 multiplying the output of the counter 26, a deflip-flop 21 for holding the reset signal RST in accordance with the burst lock clock BL-CLK, and the deflip-flop ( An inverter 23 for inverting the output of the signal 21, a deflip-flop 22 for holding the output of the deflip-flop 21 in accordance with the burst lock clock BL-CLK, and the deflip-flop 22 And the AND gate 24 for ANDing the output of the inverter 23 and the OR gate 25 for resetting the counter 26 by ORing the outputs of the AND gates 24 and 27. A digital TV sampling rate conversion circuit, comprising: a digital TV. The read address generating means is configured in the same manner as the write address generating means to generate the read address LCO by calculating the line lock clock LL-CLK and the address correction pulse WA. Digital TV sampling rate conversion circuit. 4. The buffer memory according to claim 1, wherein the buffer memory is enabled at the decoder 11 for decoding the write address BCO [3: 0], and at the output of the decoder 11, in accordance with the burst lock clock BL-CLK. Registers 12-1 to 12-8 for storing input data and four 3-bit registers for storing the lower 3 bits of the read address LCO [3: 1] according to the line lock clock LL-CLK ( 14, a multiplexer 13 for selecting a corresponding output among the registers 12-1 to 12-8 in accordance with the output of the register 14, and the multiplexer 13 in accordance with the line lock clock LL-CLK. A digital TV sampling rate converting circuit comprising: a register (15) which selects an output of < RTI ID = 0.0 > ※ Note: The disclosure is based on the initial application.