JP2659268B2 - Image decoding device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image decoding apparatus in an image transmitting / receiving apparatus such as a video conference in which an image and a voice are transmitted simultaneously, and more particularly, to a method for converting a received digital coded signal into an image. 2. Related Art Regarding an image decoding device that performs efficient decoding on data (Prior art) A conventional image decoding device separates an image and a sound, and then fixedly adjusts the average delay time of the image calculated in advance. It was configured to delay the sound.

[Problems to be solved by the invention]

The above-described conventional image decoding apparatus is configured to separate the image and the audio and then delay the audio in a fixed manner in accordance with the average delay time of the image calculated in advance.
The amount of data that has been coded and transmitted changes due to the movement of the transmitted image, the size of the subject, and the fineness of the texture, etc., and the time required to decode the data into an image changes. There is a disadvantage that the delay time cannot be made equal to that of voice.

[Means for solving the problem]

An image decoding apparatus according to the present invention includes a separation circuit that receives a received signal and separates the digitally coded image data into digital audio data, and writes and temporarily stores the digitally coded image data at a predetermined constant speed. A buffer memory for inputting and delaying the digital audio data, a decoding circuit for efficiently decoding digital encoded image data output from the buffer memory and outputting digital image data, A read clock of the buffer memory, which generates a decoded frame from a memory, is input, and one of the decoded frames is input.
A delay amount calculation circuit for calculating and outputting a delay amount of the digitally encoded image data based on the number of the read clocks for each frame; and a delay amount of the digitally encoded image data from the delay amount calculation circuit. A delay control circuit that calculates an average delay amount for each of the decoding frames N (an integer of N1) times and controls the delay amount of the delay circuit based on the average delay amount.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a configuration of a delay amount calculating circuit in FIG. 1, and FIG. 3 is a delay control in FIG. FIG. 4 is a block diagram showing an example of the circuit configuration, FIG. 4 is a block diagram showing an example of the configuration of the delay circuit in FIG. 1, and FIG. 5 shows the time relationship of signals in the delay control circuit shown in FIG. FIG. 6 shows the fourth embodiment.
FIG. 7 is a diagram showing the time relationship of the signals in the delay circuit shown in FIG. 7, FIG. 7 is a diagram showing the time relationship of the signals for calculating the amount of delay in this embodiment, and FIG. FIG. 6 is a diagram showing an example of a conversion table of FIG.

Referring to FIG. 1, an image decoding apparatus according to the present embodiment receives a received signal a and separates it into digital encoded image data b and digital audio data e. A buffer memory 3 for writing and temporarily storing the digital audio data e, a delay circuit 4 for inputting and delaying the digital audio data e, and a buffer memory output data c output from the buffer memory 3 for highly efficient decoding to output digital image data d. A predictive decoding circuit 5, a buffer memory read clock g generated in a decoded frame from the buffer memory 3, a delay amount calculating circuit 6 for calculating and outputting a delay amount of the digitally encoded image data, The delay amount i of the digitally encoded image data is input from the calculation circuit 6 and the number of decoding frames N (an integer of N1) is calculated. Constitute and a delay control circuit 7 controlled by the delay control signal j average delay amount calculated from the average delay the amount of delay of the delay circuit 4 and.

Next, the operation of this embodiment will be described with reference to FIG.

In FIG. 1, a received signal a from an input terminal 1 is input to a separation circuit 2. The separation circuit 2 separates the received signal a into digital coded image data b and digital audio data e, and outputs the digital coded image data b to the buffer memory 3. Also, it outputs the digital audio data e to the delay circuit 4. The buffer memory 3 writes the digitally encoded image data b at a constant speed and temporarily stores it. At this time, a frame synchronization signal of an image is detected from the digitally encoded image data b, and when one frame of image data is accumulated, the buffer memory output data c is output to the predictive decoding circuit 5 and the decoded frame synchronization signal is output. The signal h is output to the delay amount calculation circuit 6 and the delay control circuit 7, and the read clock g of the buffer memory is output to the delay amount calculation circuit 6. The predictive decoding circuit 5 decodes the buffer memory output data C with high efficiency and outputs digital image data d to an output terminal 8. The delay amount calculation circuit 6 calculates the delay amount i of the image in units of one decoded frame, and outputs it to the delay control circuit 7. The delay control circuit 7 receives the image delay amount i and the decoded frame synchronization signal h, calculates the average value of the image delay amount i every N decoded frames, and creates a delay control signal j from the average value. And outputs it to the delay circuit 4. The digital audio data e from the separation circuit 2 is input to the delay circuit 4, and the delay circuit 4 outputs to the output terminal 9 delayed audio data f obtained by delaying the digital audio data e by the delay control signal j.

The delay amount calculating circuit 6 in FIG. 1 will be described in detail with reference to FIG.

In FIG. 2, the delay amount calculating circuit 6 includes a counter 61, a register 62, and a ROM 63. The method of calculating the delay amount i of the image of one decoded frame in this embodiment is the first
This will be described with reference to FIG. 2, FIG. 2 and FIG.

The range from one decoded frame to immediately before the next frame to be decoded is defined as one decoded frame. The amount of delay i of an image per decoded frame is determined by the predictive decoding circuit 5
Is added to the fixed delay time t and the delay time u which is variable for each decoding by the variable-length decoding and buffer memory 3. The delay time u is the time from when the digital coded image data b for one frame starts to be written into the buffer memory 3 until the reading starts. Therefore, in order to obtain the delay time u, it is sufficient to measure the amount of data read during one decoding frame and divide it by the transmission rate. From the above, the image delay amount i can be expressed by the following equation.

i = u + t = (S / R) + t (sec) (1) where, t: fixed delay time of predictive decoding circuit, R: transmission speed, S: data amount of decoded frame, 1 of decoded frame The data amount S is measured by the counter 61 and the register 62. The counter 61 is reset by the decoding frame synchronization signal h, and counts the number of buffer memory read clocks g. The register 62 takes in the count number of the counter 61 immediately before resetting and outputs this value to the ROM 63 as the data amount S between one decoding frame. The calculation result of the image delay amount by the equation (1) is written in the ROM 63, and the image delay amount i corresponding to the data amount S between one decoding frame input from the register 62 is output to the delay control circuit 7. I do.

The delay control circuit 7 in FIG. 1 will be described in detail with reference to FIG.

In FIG. 3, the delay control circuit 7 includes an adder 71, a register (A) 72, a counter 73, a divider 74, and a register (B) 75.
And the ROM 76. In this embodiment, the average value p of the image delay amount for every N decoding frames is obtained by the following equation.

Here, N: an arbitrary integer, i _x : the amount of image delay in the decoded frame, and in FIG. 3, an adder 71 and an amount of delay i of the image output from the amount of delay calculation circuit 6 and a register (A) 72 Is added to the delay amount of the image up to one decoded frame before, and the result is input to the register (A) 72 again. counter
At 73, the decoding frame synchronizing signal h output from the buffer memory 3 is counted N times, and a pulse 1 of N decoding frame periods is created, and the register (A) 72 and the register (B)
Output to 75. In the register (A) 72, the image delay amount i
Is held, and the held value is output to the divider 74. The register (A) 72 is reset by a pulse 1 of N decoding frame periods. The divider 74 divides the accumulated value of the image delay amount i from the register (A) 72 by N, and outputs an average value calculation result k of the image delay amount to the register (B) 75. Counter 73 in register (B) 75
Once per N-decoded frame by the pulse 1 from, the image delay amount calculation result k from the divider 74 is fetched,
This is output to the ROM 76 as the average delay amount p of the image. ROM
At 76, the delay amount average value p is converted into a delay control signal j according to a conversion table prepared in advance.

 FIG. 5 shows the time relationship of the signals in the delay control circuit 7.

In FIG. 5, the image delay amount i is parallel 8-bit data, and represents the value of the delay amount for each decoded frame. The average value calculation result k is an average value obtained by accumulating the image delay amount i between N decoded frames and 1 / N.

This average value calculation result k is held at the value immediately before the rise of the pulse l, and 165 is obtained as the delay amount average value p. Fig. 8 ROM
76 shows an example of the conversion table of 76. The delay control signal j is converted to a value of 2 according to this conversion table.

The delay circuit 4 in FIG. 1 will be described in detail with reference to FIG. 4 and FIG.

In FIG. 4, the delay circuit 4 includes an n-bit shift register 41 and an m-input / one-output selector 42. Digital audio data e is an n-bit shift register
The signal is divided into m outputs e1 to em having different delay amounts and output to an m-input / one-output selector. The m-input / one-output selector 42 selects one of the m pieces of delayed audio data e1 to em according to the delay control signal j and outputs the delayed audio data f to the output terminal 9.

FIG. 6 shows an n-bit shift register of the delay circuit 4 as a 16-bit shift register, and an m-input 1-output selector as 4-input 1
FIG. 9 is an operation waveform diagram when the output selector is configured as an output selector.
e1 to e4 are data delayed by 4 bits, 8 bits, 12 bits, and 16 bits with respect to the digital audio data e, respectively. One of the four is selected by the delay control signal j and becomes the delayed audio data f. As an example, when the delay control signal has a value of 0, e1 is selected, and when the delay control signal has a value of 2, e3 is selected.

〔The invention's effect〕

As described above, the present invention has a configuration in which the delay amount of the audio signal is controlled by the average value of the delay amount in the decoding of the image data, so that when the information amount of the transmitted image data increases or decreases, Can be made substantially equal to the delay time of the sound, and therefore, especially when the respective delay amounts of the received image data and the sound data become equal, the lip sync between the output image and the sound is obtained. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a configuration of a delay amount calculating circuit in FIG. 1, and FIG. 3 is a delay control in FIG. FIG. 4 is a block diagram showing an example of the circuit configuration, FIG. 4 is a block diagram showing an example of the configuration of the delay circuit in FIG. 1, and FIG. 5 shows the time relationship of signals in the delay control circuit shown in FIG. FIG. 6, FIG. 6 is a diagram showing the time relationship of the signals in the delay circuit shown in FIG. 4, FIG. 7 is a diagram showing the time relationship of the signals for calculating the delay amount in this embodiment, and FIG. FIG. 4 is a diagram illustrating an example of a ROM conversion table in the delay control circuit illustrated in FIG. 1: input terminal, 2: separation circuit, 3: buffer memory, 4: delay circuit, 5: predictive decoding circuit, 6: delay amount calculation circuit, 7: delay control circuit, 8: output terminal, 9: audio data input Terminals, 41: n-bit shift register, 42: m-bit input 1 output selector, 71:
Adder, 72: register (A), 73: counter, 75: register (B), 76: ROM, 74: divider, 61: counter, 62: register, 63: ROM. a: received signal, b: digital coded image data, c: buffer memory output data, d: digital image data, e: digital audio data, j: delay control signal, g: buffer memory read clock, h: decoding frame Synchronization signal, i: image delay amount, f: delayed audio data, k: average value calculation result, l: pulse, p: average delay amount.

Claims (1)

(57) [Claims] 1. A separation circuit for receiving a received signal and separating it into digitally encoded image data and digital audio data, and a buffer memory for writing the digitally encoded image data at a predetermined constant speed and temporarily storing the same. ,
A delay circuit for inputting and delaying the digital audio data, a decoding circuit for efficiently decoding digital encoded image data output from the buffer memory and outputting digital image data, and a decoding frame from the buffer memory. A delay calculation circuit that inputs a read clock of the buffer memory generated in the above, calculates a delay amount of the digitally encoded image data based on the number of the read clocks for each frame of the decoded frame, and outputs the calculated delay amount. The delay amount of the digitally encoded image data is input from the delay amount calculation circuit and the decoded frame N (N ≧
A delay control circuit for determining an average delay amount every (integer of 1) times and controlling the average delay amount of the delay circuit based on the average delay amount.