JPH0482433A - Image decoder - Google Patents

Abstract

PURPOSE:To set the delay time of an image equal to that of sound even when the information quantity of transmission image data is increased/decreased by employing such constitution that the delay quantity of an audio signal is controlled by the delay quantity in the decoding of the image. CONSTITUTION:A reception signal (a) is separated to digital coded image data (b) and digital sound data (e) at a separation circuit 2, and the digital coded image data (b) is outputted to buffer memory 3. The frame synchronizing signal of the image is detected from the digital coded image data (b), and buffer memory output data (c) is outputted to t predictive decoder circuit 5. The predictive decoder circuit 5 decodes the buffer memory output data (c) with high efficiency, and outputs images data (d) to an output terminal 8. The delay quantity (i) of the image in decoding frame unit is calculated at a delay quantity calculation circuit 6, and the mean value of the delay quantity (i) of the image at every N times of decoding frame is calculated from the delay quantity (i) of the image and the frame syncrhonizing signal (h) at a delay control circuit 7, and a control signal (j) is generated. Delayed sound data (f) in which data E is delayed is outputted from a delay circuit 4 to an output terminal 9 by the signal (j).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image decoding device in an image transmitting/receiving device such as a television conference where images and sounds are transmitted simultaneously, and particularly relates to an image decoding device that converts received digitally encoded signals into images. An image decoding device that performs high-efficiency decoding into data [Prior art] A conventional image decoding device separates images and audio, and then
The configuration was such that the audio was fixedly delayed in accordance with the pre-calculated average delay time of the image.

[Problem to be solved by the invention]

The conventional image decoding device described above separates the image and audio, and then decodes the image in accordance with the pre-calculated average delay time of the image.
Since the configuration is such that the audio is fixedly delayed, the amount of coded and transmitted data changes depending on the movement of the transmitted image, the size of the subject, the fineness of the image, etc., and the data is decoded into an image. Since the time it takes to change the image changes, the delay amount of the image is not constant and the delay time with the audio cannot be equalized, which is a drawback.

[Means to solve the problem]

The image decoding device of the present invention includes a separation circuit that inputs a received signal and separates it into digitally encoded image data and digital audio data, and a separate circuit that writes the digitally encoded image data at a predetermined constant speed and temporarily stores it. a delay circuit that inputs and delays the digital audio data; a decoding circuit that highly efficiently decodes the digitally encoded image data output from the buffer memory and outputs digital image data; - A delay amount calculation circuit that inputs the buffer memory read clock generated in the decoded frame from the sofa memory, calculates and outputs the delay amount of the digitally encoded image data, and outputs the digitally encoded image data from the delay amount calculation circuit. and a delay control circuit that inputs the delay amount of , calculates the average delay amount for each of the decoded frames N (N≧1 integer), and controls the delay amount of the delay circuit from this average delay amount.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the configuration of the delay amount calculation circuit in FIG. 1, and FIG. 3 is a block diagram showing an example of the configuration of the delay amount calculation circuit in FIG. 1. FIG. 4 is a block diagram showing an example of the configuration of the circuit, FIG. 4 is a block diagram showing an example of the configuration of the delay circuit in FIG. 1, and FIG. 5 shows the time relationship of the signals in the delay control circuit shown in FIG. 3. FIG. 6 is a diagram showing the time relationship of the signals in the delay circuit shown in FIG. 4, FIG. 7 is a diagram showing the time relationship of the signals for calculating the delay amount in this embodiment, and FIG. FIG. 3 is a diagram showing an example of a conversion table of a ROM in the delay control circuit shown in the figure.

In FIG. 1, the image decoding apparatus of this embodiment includes a separating circuit 2 which inputs a received signal a and separates it into digitally encoded image data b and digital audio data e, and a separating circuit 2 which inputs a received signal a and separates it into digitally encoded image data b and digital audio data e, and which converts the digitally encoded image data b at a constant speed. A buffer memory 3 for writing and temporarily storing digital audio data e, a delay circuit 4 for inputting and delaying digital audio data e, and highly efficient decoding of buffer memory output data C output from the buffer memory 3 to output digital image data d. Predictive decoding circuit 5
and a delay amount calculation circuit 6 which inputs the buffer memory read clock g generated in the decoded frame from the buffer memory 3 and calculates and outputs the delay amount of the digitally encoded image data, and the delay amount calculation circuit 6 inputs the buffer memory read clock g generated in the decoded frame. Input the delay amount i of encoded image data, and select the decoded frame N.
The delay control circuit 7 calculates an average delay amount for each (an integer of N≧1) times and controls the delay amount of the delay circuit 4 from this average delay amount using a delay control signal j.

Next, the operation of this embodiment will be explained using FIG. 1.

In FIG. 1, a received signal a from an input terminal 1 is input to a separation circuit 2. As shown in FIG. The separation circuit 2 separates the received signal a into digitally encoded image data b and digital audio data e, and outputs the digitally encoded image data b to the buffer memory 3. It also outputs digital audio data e to the delay circuit 4. In the buffer memory 3, digitally encoded image data b is written at a constant speed and temporarily stored. At this time, the frame synchronization signal of the image is detected from the digitally encoded image data b, and when the image data for one frame is accumulated, the buffer memory output data C is output to the predictive decoding circuit 5, and the decoding The frame synchronization signal is sent to the delay amount calculation circuit 6 and the delay control circuit 7, and the read clock g of the buffer memory is sent to the delay amount calculation circuit 6.
Output to. The predictive decoding circuit 5 decodes the buffer memory output data C with high efficiency and outputs digital image data d to an output terminal 8. The delay amount calculation circuit 6 calculates the delay amount i of the image in units of one decoded frame, and the delay control circuit 7
Output to. The delay control circuit 7 inputs the image delay amount i and the decoded frame synchronization signal h, calculates the average value of the image delay amount i for every N decoded frames, and creates a delay control signal j from the average value. and outputs it to the delay circuit 4. The digital audio data e from the separation circuit 2 is input to the delay circuit 4, and the delay circuit 4 outputs delayed audio data f, which is the digital audio data e delayed by the delay control signal j, to the output terminal 9.

The delay amount calculation circuit 6 in FIG. 1 will be explained in detail with reference to FIG.

In FIG. 2, the delay amount calculation circuit 6 is composed of a counter 61, a register 62, and a ROM 63. The method for calculating the delay amount i of an image of one decoded frame in this embodiment is shown in FIGS. This will be explained with reference to FIG.

The period from a certain decoded frame to immediately before the next decoded frame is defined as one decoded frame. The amount of image delay i per decoded frame is determined by the fixed delay time t of the predictive decoding circuit 5 and the variable length decoding and buffer memory 3.
This is the sum of the delay time U that varies for each decoding.

The delay time U is the time from the time when digitally encoded image data b for one frame starts to be written into the buffer memory 3 until the time when reading starts.

Therefore, in order to obtain the delay time U, it is sufficient to measure the amount of data read during one decoding frame and divide it by the transmission speed. From the above, the image delay amount i can be expressed by the following equation.

i=u+t= (S/R)+t (sec)-(1)
However, t: fixed delay time of the predictive decoding circuit, R: transmission speed, S: data amount of one decoded frame, and data amount S of one decoded frame is measured by a counter 61 and a register 62. The counter 61 is reset by the decoded frame synchronization signal and counts the buffer memory read clock g. The register 62 takes in the count number of the counter 61 immediately before being reset and stores this value in the ROM as the data amount S between l decoding frames.
Output to 63. The calculation result of the image delay amount according to equation (1) is written in the ROM 63, and the image delay amount i corresponding to the data amount S between one decoded frame inputted from the register 62 is output to the delay control circuit 7. do.

The delay control circuit 7 in FIG. 1 will be explained in detail with reference to FIG.

In FIG. 3, the delay control circuit 7 includes an adder 71.degree. register (A) 72. It is composed of a counter 731, a divider 74, a register (B) 75, and a ROM 76. In this embodiment, the average value p of the amount of image delay for every N decoded frames is calculated using the following equation.

p=Σi, (sec)
= 12) However, N: any integer, i,: the amount of image delay in the N decoded frame, In FIG. A) Adds the delay amount of the image up to one decoded frame before outputted from 72, and inputs the result to register (A) 72 again. The counter 73 counts the decoded frame synchronization signal outputted from the buffer memory 3 N times, creates a pulse p with N decoded frame periods, and outputs it to the register (A) 72 and register (B) 75. The register (A) 72 holds the accumulated sum value of the image delay amount i, and outputs the held value to the divider 74. Further, the register (A) 72 is reset by a pulse p of N decoding frame periods. The divider 74 divides the accumulated sum value of the image delay amount i from the register (A) 72 by N, and outputs the average value calculation result k of the image delay amount to the register (B) 75. Register (B)
At 75, the average value calculation result k of the image delay amount from the divider 74 is fetched once every N decoded frames by the pulse j from the counter 73, and is outputted to the ROM 76 as the average image delay amount p. The ROM 76 converts the average delay amount p into a delay control signal j according to a conversion table prepared internally in advance.

FIG. 5 shows the time relationship of the signals in the delay control port N17.

In FIG. 5, the image delay amount i is parallel 8-bit data, and represents the value of the delay amount in units of one decoded frame.
The average value calculation result includes the image delay amount i between N decoding frames.
This is the average value obtained by summing up the values.

The average value calculation result is held at the value immediately before the rise of pulse 1, and 165 is obtained as the delay amount average value p. R in Figure 8
The delay control signal j is converted to a value of 2 according to this conversion table, which is an example of a conversion table of OM76.

The delay circuit 4 in FIG. 1 will be explained in detail with reference to FIGS. 4 and 6.

In FIG. 4, the delay circuit 4 is composed of an n-bit shift register 41 and an m-input 1-output selector 42. Digital audio data e is input to an n-bit shift register 41, divided into m outputs from el to em having different amounts of delay, and output to an m input 1 output selector 42. m
The input 1 output selector 42 uses the delay control signal j to
Select one of the delayed audio data e1 to em,
The delayed audio data f is output to the output terminal 9.

Figure 6 shows that the n-bit shift register of the delay circuit 4 is a 16-bit shift register, and the m-input 1-output selector is 16-bit shift register.
FIG. 7 is an operation waveform diagram when configured as an output selector.

el to e4 are 4 bits and 8 bits, respectively, for digital audio data e.

This is data delayed by 12 bits or 16 bits.

One of these four is selected by the delay control signal j and becomes delayed audio data f. - For example, if the delay control signal is 0
When the value is 2, select el, and when the value is 2, select e3.

[Effects of the Invention] As explained above, the present invention has a configuration in which the amount of delay of an audio signal is controlled by the amount of delay in image decoding, so that when the amount of information of transmitted image data increases or decreases, Since the image delay time and the audio delay time can be made equal, it is possible to eliminate the overlap between the output image and audio, especially when the respective delay amounts of the received image data and audio data are equal. There is an effect that can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the configuration of the delay amount calculation circuit in FIG. 1, and FIG. 3 is a block diagram showing an example of the configuration of the delay amount calculation circuit in FIG. 1. FIG. 4 is a block diagram showing an example of the configuration of the circuit, FIG. 4 is a block diagram showing an example of the configuration of the delay circuit in FIG. 1, and FIG. 5 shows the time relationship of the signals in the delay control circuit shown in FIG. 3. FIG. 6 is a diagram showing the time relationship of the signals in the delay circuit shown in FIG. 4, FIG. 7 is a diagram showing the time relationship of the signals for calculating the delay amount in this embodiment, and FIG. FIG. 3 is a diagram showing an example of a conversion table of a ROM in the delay control circuit shown in the figure. 1: Input terminal, 2: Separation circuit, 3: Buffer memory, 4
: Delay circuit, 5: Predictive decoding circuit, 6: Delay amount calculation circuit, 7: Delay control circuit, 8: Output terminal, 9: Audio data input terminal, 41: n-bit shift register, 42: m-bit human power 1 output Selector, 71: Adder, 72: Register (A) 73: Counter, 75: Register (B), 76:
ROM, 74: Divider, 61: Counter, 62: Register, 63: ROM. a: Received signal, b: Digitally encoded image data, C:
Buffer memory output data, d: digital image data, e: digital audio data, j: delay control signal, g:
Buffer memory read tarokk, h: decoded frame synchronization signal, i: image delay amount, f: delayed audio data, k
: average value calculation result, l: pulse, p: delay amount average value.

Claims (1)

[Claims] a separation circuit that inputs a received signal and separates it into digitally encoded image data and digital audio data; a buffer memory that writes and temporarily stores the digitally encoded image data at a predetermined constant speed; and the digital audio data. a delay circuit that inputs and delays the digitally encoded image data, a decoding circuit that highly efficiently decodes the digitally encoded image data output from the buffer memory and outputs digital image data, and a buffer that generates a decoded frame from the buffer memory. a delay amount calculation circuit that inputs a memory read clock and calculates and outputs the delay amount of the digitally encoded image data; and a delay amount calculation circuit that inputs the delay amount of the digitally encoded image data from the delay amount calculation circuit and outputs the decoded frame N. An image decoding device comprising: a delay control circuit that calculates an average delay amount for each (an integer of N≧1) times and controls the delay amount of the delay circuit from this average delay amount.