JPS61147691A - Highly efficiency tv signal encoding device - Google Patents

Abstract

PURPOSE:To prevent the occurrence of folded distortion, error transmission, block distortion, etc. and to simplify the ware and to speed up the action, by judging the dynamic range from the plural bits (M-m) in upper level of the dynamic range, and by selecting the specific m-bit of the data inputted. CONSTITUTION:A dynamic range DR1 and picture element data DTI after eliminating the minimum level are supplied to an encoder block 5. The encoder block 5 outputs a dynamic range information DR2 from an output terminal 6, and at the same time, selects the code with less quantization bit number then the original bit number from the data DTI according to the dynamic range DR1, and outputs it as encoded code DT from an output terminal 8. Dynamic range information DR2 as addition data and the minimum level MIN are obtained from the output terminals 6 and 7 of the encoder, and the encoded code suppressed to 4-bit is obtained from the output terminal 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-efficiency encoding device using intra-field processing of digital television signals.

[Conventional technology]

As methods for encoding television signals through intra-field processing, several methods are known in which the average number of bits per pixel or sampling frequency is reduced in order to narrow the transmission band.

As an encoding method to lower the sampling frequency, image data is thinned out to 1/2 by subsampling, and the position of the subsampling point and the subsampling point used during interpolation is indicated (i.e., either above, below or to the left or right of the interpolation point). A method has been proposed that transmits a flag (indicating whether to use data at sub-sampling points).

One of the encoding methods that reduces the average number of bits per pixel is D PCM (differenti
alPCM) is known. DPCM focuses on the fact that the pixels of a television signal have a high correlation and the difference between adjacent pixels is small, and this difference signal is quantized and transmitted.

Another encoding method that reduces the average number of bits per pixel is to subdivide the L field screen into small blocks and calculate the deviation of the level distribution of the pixel at the representative point and the data within the block for each block. There is something to transmit.

[Problem that the invention seeks to solve]

The encoding method that attempts to reduce the sampling frequency using subsampling has a sampling frequency of 172
Therefore, there was a risk that aliasing distortion would occur.

DPCM has a problem in that coding errors propagate to subsequent coding.

The method of encoding in units of blocks has the disadvantage that block distortion occurs at the boundaries between blocks.

SUMMARY OF THE INVENTION An object of the present invention is to provide a highly efficient encoding device that does not suffer from the problems of the above-mentioned conventional techniques, such as generation of aliasing, error propagation, and block distortion.

Another object of the present invention is to provide a highly efficient encoding device that requires a simple configuration of encoding hardware and is capable of high-speed operation.

[Means for solving problems]

Means 41 to 48 for determining the maximum value MAX of a plurality of pixel data and the minimum value MIN of a plurality of pixel data included in a predetermined block of a digital television signal.
8, means 50 for subtracting the minimum value MIN from the values of the plurality of pixel data to form M-bit input data DTT after removing the minimum value, and calculating the dynamic range DPI for each block from the maximum value MAX and the minimum value MIN. A means for detecting 49 and an upper part of the detected dynamic range DRI data (
means 63 for selecting a range of m bits out of M bits of the input data DTI after minimum value removal according to the bit pattern of the M-m) bits, dynamic range information, and a maximum value M;
A highly efficient encoding device for a television signal, comprising: means for transmitting at least two additional codes of AX and a minimum value MIN and an m-bit encoding code DTI.

[Effect]

Since television signals have a correlation in the horizontal and vertical directions, the level of pixel data included in the same block varies little in the stationary portion. Therefore 1. Even if the dynamic range of the data DTI after removing the minimum level shared by pixel data in a block is quantized with a smaller number of quantization bits than the original number of quantization bits,
Almost no quantization distortion occurs. By reducing the number of quantization bits, the data transmission bandwidth can be made narrower than the original one.

When reducing the number of quantization bits from M bits to m bits, the upper bits of the dynamic range DRI (M
-m) The dynamic range DRI can be determined from the bits. Therefore, by selecting predetermined m bits of the data DTI according to the determination result, the encoded code DT can be formed.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 generally shows an encoder according to an embodiment of the present invention. For example, connect 1 to the input terminal indicated by 1.
An NTSC digital television signal whose samples are quantized to 8 bits is input. This digital television signal is supplied to a cascade of line delay circuits 2 and 3 and to a cascade of five sample delay circuits 11-15.

A cascade connection of five sample delay circuits 21 to 25 is connected to a connection point between line delay circuits 2 and 3.

A cascade connection of five sample delay circuits 31 to 35 is connected to the output terminal of the line delay circuit 3. Line delay circuits 2 and 3 having a delay amount of one line period, and sample delay circuits 11 to 15.21 to 25.3 having a delay amount equal to the sampling period of the input digital television signal.
1 to 35, it is possible to simultaneously obtain one block of pixel data from the output terminal of each delay circuit.

In FIG. 2, 10 indicates one block, and the solid line indicates the nth consecutive block of the current field, (n+1).
The dashed lines indicate the (n + 2)th and (n + 2)th lines.
Indicates lines for other fields.

Six pixels included in each of the three lines of the current field constitute one block of (3 lines x 6 pixels). When the pixel data of the (n+2)th line is supplied to the input terminal 1, the pixel data of the (n+1)th line is generated at the output of the line delay circuit 2, and the pixel data of the nth line is generated at the output of the line delay circuit 3. Pixel data is generated. The six pixel data of each line are taken out from the input terminal, the output terminal, and between each stage of the cascade connection of the sample delay circuit.

Six pixel data of the same line taken out by the cascade connection of sample delay circuits 11 to 15 are supplied two by two to selection circuits 16, 17, and 18.

Six pixel data of the same line extracted by the cascade connection of sample delay circuits 21 to 25 are supplied two by two to selection circuits 26, 27, and 28. Sample delay circuit 31
.about.35 pixel data of the same line taken out by the cascade connection are supplied two by two to selection circuits 36, 37, and 38. These selection circuits compare the levels of two input pixel data, output pixel data with a higher level to one output terminal, and output pixel data with a lower level to the other output terminal. This is a digital level comparison circuit configured as follows.

One output terminal of the selection circuits 16 and 17 is the selection circuit 41
The other output terminal of the selection circuits 16 and 17 is connected to the input terminal of the selection circuit 51. One output terminal of selection circuits 18 and 26 is connected to an input terminal of selection circuit 42, and the other output terminal of selection circuits 18 and 26 is connected to an input terminal of selection circuit 52. One output terminal of the selection circuits 27 and 28 is connected to the input terminal of the selection circuit 43, and the other output terminal of the selection circuits 27 and 28 is connected to the input terminal of the selection circuit 53.

One output terminal of the selection circuits 36 and 37 is connected to the selection circuit 44.
The other output terminal of the selection circuits 36 and 37 is connected to the input terminal of the selection circuit 54.

The selection circuits 41 to 44 are digital level comparison circuits configured to compare the levels of two input pixel data and selectively output only the pixel data with the higher level. The selection circuits 51 to 54 select the input 2
This is a digital level comparison circuit configured to compare the levels of two pixel data and selectively output only the pixel data of the smaller level.

The outputs of the selection circuit 41 and the selection circuit 42 are supplied to the selection circuit 45. The outputs of the selection circuit 843 and the selection circuit 44 are supplied to the selection circuit 46. Selection circuit 45 and selection circuit 4
6 is supplied to the selection circuit 47. The output of the selection circuit 47 and the higher level output of the selection circuit 38 are supplied to the selection circuit 48. Selection circuit 45.46.47.4
Similarly to the selection circuits 41 to 44, 8 selectively outputs pixel data of a higher level. Therefore,
At the output terminal of the selection circuit 48, pixel data of the maximum level MAX among the 18 pixel data in the block IO is generated.

The outputs of the selection circuit 51 and the selection circuit 52 are supplied to the selection circuit 55. The outputs of the selection circuit 53 and the selection circuit 54 are supplied to the selection circuit 56. Selection circuit 55 and selection circuit 5
6 is supplied to the selection circuit 57. The output of the selection circuit 57 and the lower level output of the selection circuit 38 are supplied to the selection circuit 58. Selection circuit 55.56.57.5
Similarly to the selection circuits 51 to 54, 8 selectively outputs pixel data of a smaller level. Therefore,
At the output terminal of the selection circuit 58, the pixel data of the minimum level MIN among the 18 pixel data in the block IO resides.

The output of the selection circuit 48 and the output of the selection circuit 58 are supplied to a subtraction circuit 49. By the subtraction circuit 49 (maximum level M
AX−minimum level MIN) is calculated, and the subtraction circuit 4
An 8-bit dynamic range DRI is obtained at the output of 9. The minimum level MIN is taken out to the output terminal 7 and is also supplied to the subtraction circuit 50.

Pixel data PD generated at the output of the sample delay circuit 35 is supplied to the subtraction circuit 50 via the delay circuit 4. This delay circuit 4 has a maximum level MAX and a minimum level MI.
The amount of delay is equal to the delay caused to detect N as described above.

8-bit pixel data DTI from which the minimum level has been removed is obtained as the output of the subtraction circuit 50.

The dynamic range DRI and the pixel data DTI after minimum level removal are supplied to the encoder block 5. The encoder block 5 generates the dynamic range information DR2 (3 bits or 4 bits) to be transmitted at the output terminal 6, and also generates the number of quantized bits (in this example, 4 bits) smaller than the original number of bits according to the dynamic range DPI.
The code of bit) is selected from the data DTI and generated at the output terminal 8 as the encoded code DT.

The specific configuration of the encoder block 5 will be described later.

As described above, the dynamic range information DR2 and the minimum level MIN as additional data are obtained at the output terminals 6 and 7 of the encoder shown in FIG. Code DT is obtained.

One block of the original digital television signal is (3
x6 x 8 bits = 144 bits).

In this embodiment, the l block is (3 x 6 x 4 bits + 11 bits = 83 bits), and the number of bits to be transmitted can be reduced to approximately half. Although not shown, the encoded code DT and additional data DR2°MIN are subjected to error correction code encoding processing and are transmitted as serial data (or recorded on a recording medium).

Some examples of the format of transmission data are shown in FIG. Third
Diagram A shows the minimum level MIN, dynamic range DR2
and encoded code DT are encoded with independent error correction codes, and the parity of each error correction code is added and transmitted. In FIG. 3B, the minimum level MIN and dynamic range DR2 are each encoded with independent error correction codes, and the parity of each error correction code is added. In FIG. 3C, a common error correction code is applied to both the minimum level MIN and the dynamic range DR2, and the parity thereof is added.

The encoded code DT obtained at the output terminal 8 of the encoder is in the same order as the input television signal. Therefore,
Additional data M I N for each block.

DR2 occurs every 3 lines in terms of lines and every 6 samples in the sampling direction. When the transmission data is divided into predetermined amounts of encoded codes DT, sections that do not include additional data occur in the transmission data. Therefore, a buffer memory may be connected to the output of the encoder, and one block of additional data DR2, MIN and encoded code DT may be used as a unit of transmission. In this case, the length of the data portion consisting of the encoded code DT in FIG.
The length is 16 bits x 16).

As shown in Figure 4, the level of the television signal when the number of quantization bits is 8 bits is 25 of (0 to 255).
There are 6 possibilities. However, in a stationary area excluding non-stationary areas such as the outline of an object, the level distribution of pixels in one block is concentrated in a fairly narrow level range, as shown in FIG. Therefore, if the number of bits of the encoded code is set to 4 bits as in this embodiment, it is possible to prevent quantization distortion from increasing.

FIG. 5 shows an example of the configuration of the encoder block 5. As shown in FIG.

In FIG. 5, data DTI after minimum level removal is supplied to the input terminal 61, and this DTI is supplied to the register 6.
It can be stored in 2. The output of register 62 is supplied to the input terminal of bit selection circuit 63.

The dynamic range DRI from the subtraction circuit 49 is supplied to an input terminal 64 . This dynamic range DRI is supplied to the priority encoder 65, and according to the output of the priority encoder 6503 bits,
Bit selection circuit 63 is controlled. Bit selection circuit 63
Accordingly, 4 bits corresponding to the output of the priority encoder 65 are selected from among the 8 bits of the data DTI.

The output data of the priority encoder 65 is taken out as dynamic range data DR2 that is transmitted to the output terminal 6. The 4-bit output data of the bit selection circuit 63 is taken out to the output terminal 8 as an encoded code DT to be transmitted.

The priority encoder 65 generates a 3-bit output (C2, C1, Go) according to the bit pattern of the upper 4 bits of the dynamic range DRI. Based on the output of the priority encoder 65, the bit selection circuit 63 selects the 8 bits (
X7. In (7), 4 bits (Y
3. Y2°Yl, YO) is selected and output as the encoded code DT.

The output of the priority encoder 65 for the upper 4 bits of the dynamic range DRI and the bit selection circuit 6 selected by the output of the priority encoder 65
The relationship between the outputs of 4 bits of 3 is shown in the table below.

In other words, the size of the dynamic range DRI is
The smallest quantization unit is selected based on the size of this dynamic range DRI. 3Beaz) (C2°C1, CO) indicating this quantization unit is transmitted as dynamic range information DR2.

In FIG. 6, 71 indicates 4 bits selected when the most significant bit (MSB) of the dynamic range DPI is 1'. The minimum quantization unit in this case is 16. 7
2 is 2 when the MSB of dynamic range DPI is °O゛
It shows the 4 bits selected when the th most significant bit is "1", and the minimum quantization unit in this case is 8. 73 is
The MSB of the dynamic range DRI indicates 4 bits selected when the second high-order bit is 0'' and the third high-order bit is 1'', and the minimum quantization unit in this case is 4.

74 indicates the MSB of the dynamic range DRI, the 4 bits selected when the second and third upper bits are 0 and the fourth upper bit is 1, and is the minimum quantization unit in this case. becomes 2. 75 indicates 4 bits selected when all the upper 4 bits of the dynamic range DPI are "0", and the minimum quantization unit in this case is 1.

An example of a decoder block corresponding to the encoder block 5 described above is shown in FIG.

The received data DT is supplied to an input terminal 81, the received dynamic range information DR2 is supplied to an input terminal 82, and the received minimum level MIN is supplied to an input terminal 83.
is supplied. Data DT is supplied to selection circuit 84. This selection circuit 84 selects a total of 4 bits of °0 on the upper side or lower side of the 4-bit data DT.
It generates an 8-bit output selected from five types of 8-bit data to which bits ' are added based on the dynamic range information DR2.

The output data of this selection circuit 84 corresponds to the data DTI after minimum level removal. The output of selection circuit 84 is supplied to one input terminal of adder 85. The other input terminal of the adder 85 is supplied with the minimum level MIN. The output terminal 86 of this adder 85 receives pixel data PD.
is taken out.

In the above explanation, three items are transmitted: the encoded code DT, the dynamic range information DR2, and the minimum level MIN. However, the minimum level MIN and maximum level MAX may be transmitted as additional codes, or the dynamic range information DR2 and the minimum level MIN may be transmitted.

Furthermore, the present invention can be applied even when the block is one-dimensional. As shown in FIG. 9, one plot may consist of, for example, 16 consecutive pixels on the same line. An encoder for a one-dimensional block will be described with reference to FIG.

In FIG. 8, reference numeral 91 indicates an input terminal to which a digital television signal is input in 8-bit parallel. The input digital television signal is supplied to a subtraction circuit 94 via a delay circuit 93.

92 indicates an input terminal to which a sampling clock synchronized with the input digital television signal is supplied. This sampling clock is used by counter 99 and register 100.
and 101 as clock pulses. The counter 99 is a hexadecimal counter, and a block clock is generated at its output every 16 pixel data. This block clock is supplied to registers 100 and 101 as a pulse for initialization. In addition, the latch 105
and 106 as a latch pulse.

Registers 100 and 101 are capable of inputting and outputting 8-bit parallel data. One register 1
The output data of 00 is supplied to one input terminal of the selection circuit 102, and the output data of the other register 101 is supplied to one input terminal of the selection circuit 103. The other input terminals of these selection circuits 102 and 103 are supplied with an input digital television signal.

The selection circuit 102 is configured as a digital level comparison circuit that selects and outputs the one with the higher level from two pieces of input data. The selection circuit 103 is configured as a digital level comparison circuit that selects and outputs the one with the smaller level of the two input data. The output data of the selection circuit 102 is supplied to one input terminal of the subtraction circuit 104 and also to the input terminal of the register 100. The output data of the selection circuit 103 is supplied to the other input terminal of the subtraction circuit 104, and is also supplied to the input terminal of the register IO1.

In this example, one block is composed of 16 consecutive pixel data on the same line, as shown in FIG. At the beginning of each block, a block clock is generated from counter 99, and registers 100 and 101 are initialized. Register 100 is loaded with a bit code of all °0゛ as an initial value, and register 101
is loaded with a bit code of 0.1 as an initial value.

The first pixel data of one block is selected by selection circuits 102 and 1.
03 and stored in registers 100 and 101. The next pixel data is compared with the pixel data stored in the registers 100 and 101, and the data with the higher level is output from the selection circuit 102, and the data with the lower level is outputted from the selection circuit 102. data is output from the selection circuit 103. Thereafter, level comparisons are performed sequentially within the block, and the highest level among the 16 pixel data is taken out to the output terminal of the selection circuit 102, and the lowest level among the 16 pixel data is taken out to the output terminal of the selection circuit 102. It is taken out to the output terminal of the selection circuit 103.

The subtraction circuit 104 performs the calculation (maximum level - minimum level), and the dynamic range DPI of the block is detected at the output terminal of the subtraction circuit 104. Subtraction circuit 1
The dynamic range DRI outputted from the selector 04 is stored in the launch 105, and the minimum level MIN outputted from the selection circuit 103 is stored in the latch 106. latch 10
The dynamic range DRI stored in No. 5 is supplied to the encoder block 95. The minimum level MIN stored in the latch 106 is taken out to the output terminal 97 and is also supplied to the other input terminal of the subtraction circuit 94.

The subtraction circuit 94 is supplied with pixel data PD whose timing has been matched by the delay circuit 93 . Therefore, data DTI from which the minimum level MIN has been removed is generated at the output terminal of the subtraction circuit 94. This data DTI is supplied to encoder block 95. Like the encoder block 5 described above, the encoder block 95 selects 4 bit nodes at a predetermined position using the upper 4 bits of the dynamic range DPI, and converts these 4 bits into an encoded code D.
At the same time, 3-bit dynamic range information DR2 is generated at the output terminal 96.

〔Effect of the invention〕

According to this invention, the amount of data to be transmitted can be reduced to about half of the original data, and the transmission band can be narrowed. Further, according to the present invention, since the dynamic range is adaptively selected, good restored image quality can be obtained. Further, according to the present invention, since the configuration is such that the number of bits smaller than the original number of bits is selected, it is possible to simplify and speed up the configuration for compressing the number of quantization bits.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a route diagram used to explain blocks that are units of encoding processing, and Fig. 3 is used to explain multiple examples of the structure of transmission data. Route map, Figure 4 is a route map used to explain the level distribution of pixel data within one block, Figure 5 is a block diagram of an example of an encoder block, Figure 6 is a route map used to explain the encoder block, and Figure 7 is a route map used to explain the level distribution of pixel data within one block. This figure is a block diagram of a decoder, and FIGS. 8 and 9 are block diagrams of other embodiments of the present invention.゛1: Digital television signal input terminal, 2゜3-line delay circuit, 5: Encoder block, 6: Dynamic range information DR2 output terminal, 7: Minimum level M
Output terminal of IN, 8: Output terminal of encoded code DT, 1
0 Niblock, 11-15.21-25.31-35:
Sample delay circuit, 63: bit selection circuit, 65 nibble quality encoder.

Claims (1)

[Scope of Claims] Means for determining a maximum value of a plurality of pixel data and a minimum value of the plurality of pixel data included in a predetermined block of a digital television signal; means for subtracting from the maximum value and the minimum value to form M-bit input data after removing the minimum value; means for detecting the dynamic range for each block from the maximum value and the minimum value; and the upper part of the detected dynamic range data. (M
- m) means for selecting a range of m bits out of M bits of the input data after the minimum value has been removed according to a bit pattern of the bits; and at least among the dynamic range information, the maximum value, and the minimum value; A high-efficiency encoding device for a television signal, comprising two additional codes and means for transmitting the m-bit encoded code.