JPS62266924A - High efficient coding device - Google Patents

Abstract

PURPOSE:To obtain a high efficient coding device reducing a sent data quantity and preventing generation of loopback distortion by varying a period of sampling in response to a dynamic range DR at each block. CONSTITUTION:An input digital TV signal is converted into a consecutive signal at each two-dimension block by a blocking circuit 2 and fed to a DR detection circuit 3 and a variable smapling circuit 4. The circuit 3 detects the DR and a minimum value MIN at each block, a picture element data PD from the circuit 4 is fed to a subtraction circuit 5, where the minimum value is eliminated to form a picture element data PDI. Further, the DR is fed to the circuit 4 and sub sampling is applied in a prescribed interleaving rate corresponding to the DR. The picture element data PDI and the DR are fed to a quantization circuit 6, where quantization is applied and the code DT is fed to a framing circuit 7, which applies the error correction coding to the code DT and the additional code of the DR and the minimum value MIN, a synchronizing signal is added and the result is sent to a transmission line such as a digital line from a terminal 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-efficiency encoding device for compressing image data such as digital television signals.

[Summary of the invention]

The present invention is a high-efficiency encoding device applied when transmitting image data such as digital television signals, in which one screen is divided into a large number of two-dimensional or three-dimensional blocks, and pixels in each block are This method performs subsampling at a period that is adapted to the dynamic range narrowed due to the correlation between the two, and it is possible to increase the compression ratio without degrading the quality of the restored image on the receiving side.

[Conventional technology]

As a method of encoding television signals, the transmission band is narrow (
A method of lowering the sampling frequency is known for this purpose. For example, when image data is thinned out to 2 by subsampling, it indicates the subsampling point and the position of the subsampling point to be used during interpolation (i.e. indicates which subsampling point above, below, or to the left or right of the interpolation point is used). ) flag has been proposed.

[Problem that the invention seeks to solve]

The encoding method that attempts to reduce the sampling frequency using subsampling has a high degree of redundancy where the brightness level changes are small, but on the other hand, where the brightness level changes rapidly, the sampling frequency is reduced to 2. There was a risk that aliasing distortion would occur.

Therefore, an object of the present invention is to provide high-efficiency encoding that can both reduce the amount of data to be transmitted and prevent the occurrence of aliasing distortion by varying the subsampling period to adapt to the dynamic range of each block. The goal is to provide equipment.

[Means for solving problems]

The present invention includes a dynamic range detection circuit 3 that calculates the dynamic range DR for each block consisting of areas belonging to the same field or a plurality of consecutive fields of a digital image signal,
This is a high-efficiency encoding device comprising a variable subsampling circuit 4 that subsamples pixel data of a block at a period corresponding to .

[Effect]

When the dynamic range DR of a block is large, the image of this block changes rapidly, so subsampling is not performed. Furthermore, the smaller the dynamic range DR, the smaller the change in the image of the block, so the subsampling period is lengthened. - As an example, 1/2.1/4.1/80 according to Dynaminofreni/DiDR
One of three types of subsampling is used. , the second adaptive subsampling allows the sampling frequency to be lowered on average without producing aliasing distortion. Also, for the subsampling output,
By applying quantization adapted to the dynamic range DR, the average number of bits per pixel can be reduced, and the compression rate of data to be transmitted can be significantly increased.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. This invention is made in the following order of items.

a, Configuration of the transmitting side, Configuration of the receiving side C, Block and blocking circuit d, Dynamic range detection circuit e, Variable sub-sampling circuit f, Quantization circuit g, Modification a, Configuration of the transmitting side. , which shows the overall configuration of the transmitting side (recording side) of the present invention. For example, a digital television signal in which l samples are quantized to 8 pins is input to an input terminal indicated by 1. This digital television signal is supplied to the blocking circuit 2.

The blocking circuit 2 converts the input digital television signal into a continuous signal for each two-dimensional block, which is a unit of encoding. In this example, the ■ block is (8
The size of the line is 8'#J elements = 64 pixels). The output signal of the processing circuit 2 is supplied to a dynamic range detection circuit 3 and a variable subsampling circuit 4. The dynamic range detection circuit 3 detects the dynamic range DR and the minimum value M r N for each block.

The pixel data PD from the variable sub-sampling circuit 4 is supplied to the subtraction circuit 5, where the minimum value MI
Pixel data PDI from which N is removed is formed.

Further, the detected dynamic range DR is supplied to the variable sub-sampling circuit 4. The variable nub sampling circuit 4 performs subsampling at a period (thinning rate) corresponding to the dynamic range DR. -For example,
In the variable subsampling circuit 4, the thinning ratio (-number of images in one block after subsampling ÷ original number of pixels in one block (64)) is determined according to the dynamic range DR as follows. .

The quantization circuit 6 includes a subsampling circuit and a subtraction circuit 5.
The pixel data PDr and dynamic range DR after minimum value removal are supplied via the pixel data PDr and the dynamic range DR.

The quantization circuit 6 quantizes the pixel data PDI.

The encoded code DT from this quantization circuit 6 is supplied to a framing circuit 7. The framing circuit 7 is supplied with a dynamic range DR (8 bits) and a minimum value MIN (8 bits) as additional codes for each block. The framing circuit 7 performs error correction encoding processing on the encoded code DT and the above-mentioned additional code, and also adds a synchronization signal.

Transmission data is obtained at the output terminal 8 of the framing circuit 7,
This transmission data is sent out to a transmission path such as a digital line.

As described above, the encoded code DT has a variable number of bits for each block, but the bit length of the pixel data of the block is uniquely determined from the dynamic range DR in the additional code. Therefore, although variable length codes are used, there is an advantage that there is no need to insert redundant codes indicating data divisions into the transmitted data.

b. Receiving side configuration FIG. 2 shows the configuration of the receiving (or reproducing) side.

The received data from the input terminal 11 is sent to the frame decomposition circuit 1.
2. The frame decomposition circuit 12 separates the encoded code DT from the additional codes DR and MIN, and also performs error correction processing. The encoded code DT is supplied to the decoding circuit 13, and the dynamic range DR is supplied to the decoding circuit 13 and the interpolation circuit 15.

The decoding circuit 13 performs processing opposite to that of the quantization circuit 6 on the transmitting side. That is, the data after the 8-bit minimum level has been removed is decoded to a representative level, this data and the 8-bit minimum value MIN are added by the adder circuit 14, and the original pixel data is decoded.

The output data of the adder circuit 14 is supplied to the interpolator circuit 15. In the interpolation circuit 15, the thinned out pixel data is obtained by weighted averaging of surrounding pixel data. The output data of this interpolation circuit 15 is supplied to a block decomposition circuit 16. The block decomposition circuit 16 is a circuit for converting decoded data in the order of blocks into the same order as the scanning of the television signal, contrary to the blocking circuit 2 on the transmitting side.

A decoded television signal is obtained at the output terminal 17 of the block decomposition circuit 16.

C. Blocks and Blocking Circuits Blocks, which are units of encoding, will be explained with reference to FIG. In this example, by dividing the screen of one field, the image shown in Fig. 3 is obtained (8 lines x 8 pixels).
A large number of two-dimensional blocks are formed. In Figure 3,
Solid lines indicate lines for odd fields, and dashed lines indicate lines for even fields. Unlike this example, for example 4
The present invention can also be applied to a three-dimensional block composed of four two-dimensional regions belonging to each frame.

The blocking circuit 2 will be explained with reference to FIGS. 4, 5, and 6. For the sake of simplicity, it is assumed that the screen of one field has a configuration of (4 lines x 8 pixels) as shown in Figure 5, and this screen is divided into two vertically and horizontally as shown by the broken line. A case will be explained in which 8 blocks (2 lines x 2 pixels) are formed.

In FIG. 4, input data A consisting of four lines (The to Thff) as shown in FIG. Sampling clock B (Figure 6B)
is supplied. Numbers (1 to 8) indicate sample data of line Th0, numbers (11 to 18) indicate sample data of line Th, and numbers (21 to 2) indicate sample data of line Th0, respectively.
8) indicates sample data of line Th2, and numbers (31 to 38) indicate sample data of line Th, respectively. Input data A is supplied to a delay circuit 23 with a delay amount of Th and a delay circuit 24 with a delay amount of 2Ts (Ts: sampling period). Also, sampling clock B
7'l<A is supplied to the frequency dividing circuit 27.

The output signal C (FIG. 6C) of the delay circuit 24 is supplied to one input terminal of the switch circuits 25 and 26, respectively, and the output signal D (FIG. 6D) of the delay circuit 23 is supplied to the other input terminal of the switch circuits 25 and 26. are supplied to the input terminals of the respective input terminals. The switch circuit 25 is controlled by the output signal E (FIG. 6E) of the frequency divider 27, and the switch circuit 26 is controlled by the pulse signal E.
is controlled by a pulse signal inverted by an inverter 28. The switch circuits 25 and 26 alternately select the input signal (C or D) every 2Ts. switch circuit 2
The output signal F from switch circuit 26 is shown in FIG. 6F, and the output signal G from switch circuit 26 is shown in FIG. 6G.

The output signal F of the switch circuit 25 is connected to the first input terminal of the switch circuit 29 and the delay circuit 30 has a delay amount of 4Ts.
supplied to The output signal G of the switch circuit 26 is 2Ts
The signal is supplied to the delay circuit 31 having a delay amount of . The output signal H of the delay circuit 30 (H in FIG. 6) is supplied to the third input terminal of the switch circuit 29. Output signal of delay circuit 31 ■
(FIG. 6I) is supplied to the second input terminal of the switch circuit 29 and the delay circuit 32 which has a delay amount of 4Ts.

The output signal J (FIG. 6J) of the delay circuit 32 is supplied to the fourth input terminal of the switch circuit 29.

The output signal of the A frequency divider circuit 27 is supplied to the frequency divider circuit 33, and an output signal K (K in FIG. 6) is formed. The switch circuit 29 is controlled by this signal K, and the first . Second. The third and fourth input terminals are sequentially selected.

Therefore, the signal taken out from the switch circuit 29 to the output terminal 34 is as shown in FIG. 61. In other words,
The field-by-field order of data is converted into a block-by-block order (for example, 1-2-11-12). Of course, the actual number of pixels in one field is much larger than in the example shown in FIG.
It is converted into the order of each block shown in the figure.

d. Dynamic Range Detection Circuit FIG. 7 shows the configuration of an example of the dynamic range detection circuit 3. The input terminal indicated by 41 requires encoding for each block from the blocking circuit 2 as described above. Seven images of the area are sequentially supplied. Pixel data from this input terminal 41 is supplied to a selection circuit 42 and a selection circuit 43. One selection circuit 42 selects and outputs the one with a higher level between the pixel data of the input digital television signal and the output data of the latch 44. The other selection circuit 43 selects and outputs the one with a smaller level between the pixel data of the human-powered digital television signal and the output data of the lunch 45.

The output data of the selection circuit 42 is supplied to the subtraction circuit 46 and is also taken into the latch 44 . The output data of the selection circuit 43 is supplied to the subtraction circuit 46 and the latch 48, and is also taken into the latch 45. Latches 44 and 45
A latch pulse is supplied from the control section 49. The control unit 49 is supplied with timing signals such as a sampling crofter and a synchronization signal from a terminal 50 that are synchronized with the input digital television signal. The control unit 49 controls the latch 44
．． 45 and latches 47 and 48 at predetermined timing.

At the beginning of each block, the contents of latches 44 and 45 are initialized. The latch 44 is initialized with data of all '0', and the latch 45 is initialized with data of all '1°. Among the sequentially supplied pixel data of the same block, the maximum level is stored in the latch 44. Furthermore, among the pixel data of the same block that is sequentially supplied, the minimum level is stored in the latch 45.

When the maximum level and minimum level detection is completed for one block, the maximum level of the block appears at the output of the selection circuit 42. On the other hand, the output of the selection circuit 43 produces the minimum level of the block.

When the detection for one block is completed, latches 44 and 45 are initialized again.

The dynamic range DR of each block is obtained from the output of the subtraction circuit 46 by subtracting the maximum level MAX from the selection circuit 42 and the minimum level MIN from the selection circuit 43. These dynamic range DR and minimum level MIN are controlled by the latch pulse from the control block 49.
They are latched by latches 47 and 48, respectively. The dynamic range DR of each block is obtained at the output terminal 51 of the latch 47, and the minimum value M I N of each block is obtained at the output terminal 52 of the latch 48.

e. Variable subsampling circuit An example of the variable subsampling circuit 4 that performs subsampling adapted to the dynamic range DR will be described with reference to FIGS. 8, 9, 10, and 11.

In FIG. 8, pixel data PD from the blocking circuit 2 is supplied to an input terminal indicated by 60.

Further, the dynamic range DR from the dynamic range detection circuit 3 is supplied to an input terminal indicated by 61. The input terminal 60 includes sub-sampling circuits 62, 63, 64.
is connected.

The sub-sampling circuit 62, as shown in FIG. 9A,
Subsampling is performed to thin out the pixels in one block one by one. In FIG. 9, an x indicates a pixel that is not subsampled and therefore not transmitted, and a white dot indicates a pixel that is subsampled, in which case the phase of subsampling is shifted by sampling period between adjacent lines. The output data of this sub-sampling circuit 62 becomes A, which is the original number of pixels.

The sub-sampling circuit 63, as shown in FIG. 9B,
Subsampling is performed by thinning out three pixels in each block. In this case, the subsampling phase is shifted between adjacent lines by twice the sampling period. The number of pixels of the output data of this sub-sampling circuit 63 is 174, which is the original number of pixels.

The sub-sampling circuit 64, as shown in FIG. 9C,
Subsampling is performed by thinning out eight pixels on average in one block, that is, thinning out of three pixels and thinning out of 13 pixels are performed alternately. Therefore, the subsampling positions are shifted by twice the sampling period between lines separated by one line. The number of pixels of the output data of this sub-sampling circuit 64 is 1/8 of the original number of pixels.

Pixel data PD from input terminal 60 and output data of each of sub-sampling circuits 62, 63, and 64 are supplied to selector 65. A control signal is supplied to the selector 65 from the ROM 66 . The dynamic range DR is supplied to the ROM66 as an address signal, and the ROM66
A 2-bit control signal corresponding to the dynamic range DR is output from. An example of the relationship between the dynamic range DR and the control signal is shown below.

i. When the dynamic range DR is very small, for example (0≦DR≦8), the control signal becomes (00),
An output signal with a reduced number of pixels is selected in 178 of the sub-sampling circuit 64.

ii. When the dynamic range DR is small, for example (9
DR≦17), the control signal becomes (01), and an output signal with a reduced number of pixels is selected at 174 of the sub-sampling circuit 63.

iii. When the dynamic range DR is intermediate, for example (18≦DR≦35), the control signal becomes (10), and an output signal with a reduced number of pixels is selected for 172 of the sub-sampling circuit 62.

iv, when the dynamic range DR is large, for example (3
6≦DR), the control signal becomes (11), subsampling is not performed, and all pixel data from the blocking circuit 2 is output.

The threshold level for determining the size of the dynamic range DR described above matches the threshold level in variable length encoding adapted to the dynamic range, which will be described later. However, it is not necessary to set the threshold level once for both, and the optimal value is used for each.

FIG. 10 shows the configuration of an example of the sub-sampling circuit 62. In FIG. 10, input signal A (FIG. 11A) is supplied to an input terminal indicated at 68.

The basic block formed by the blocking circuit 2 is (8 lines x 8 pixels), and the input signal A is
, Thr, Thz, ..., and eight pixel data (1 to 8) 1 (11 to 18
), (21-28)... are included. 1st
In FIG. 0, a sampling clock B (FIG. 11B), which is the same as the human input signal A, is supplied to an input terminal indicated by 69.

Input signal A is supplied to a delay circuit 70 having a delay amount of sampling period Ts and a sample hold circuit 72. The output signal C (FIG. 11C) of the delay circuit 70 is supplied to a sample and hold circuit 71. The sampling clock B is supplied to a frequency dividing circuit 73 with a frequency division ratio of 2, and the output signal D of this frequency dividing circuit 73 (FIG. 11D) is supplied to an inverter 74. Output signal E of impark 74 (Fig. 11 E
) is supplied to sample and hold circuits 71 and 72 as a sampling pulse.

Signals C and A are sampled and held at the falling edge of sampling pulse E, for example. In this case, the sample may be held at the rising edge. Therefore, the sampling output F shown in FIG. 11F is obtained from the sample and hold circuit 71, and the sampling output G shown in FIG. 11G is obtained from the sample and hold circuit 72. These sampling outputs F and G are connected to the switch circuit 7.
5 input terminals, respectively.

The switch circuit 75 is controlled by the output signal H (H in FIG. 11) of the frequency dividing circuit 76 with a frequency division ratio of 1/8, and alternately selects the output signals of the sample and hold circuits 71 and 72.

Therefore, in the output signal l taken out from the switch circuit 75 to the output terminal 77, as shown in FIG. It becomes something.

The sub-sampling circuits 63 and 64 can be configured similarly to the sub-sampling circuit 62 described above.

f. Quantization Circuit The quantization circuit 6 performs variable length encoding adapted to the dynamic range DR. FIG. 12 shows an example of the quantization circuit 6. In FIG. 12, the ROM indicated by 55 stores a data conversion table for converting the pixel data PDr (8 bits) after the minimum value has been removed because it is a compressed bit.

The dynamic range DR from the input terminal 56 and the pixel data PDI from the input terminal 57 are supplied to the ROM 55 as address signals.

In the ROM 55, a data conversion table is selected depending on the size of the dynamic range DR, and 5-bit encoded data DT is taken out to the output terminal 58. Depending on the dynamic range DR, the number of bits of the encoded data DT is 0.
It varies in the range of 5 bits to 5 bits. Therefore, ROM5
The effective bit length in the code output from 5 changes. In the framing circuit 7, valid bits are selected.

FIG. 13 is used to explain the variable bit length encoding adapted to the dynamic range performed by the quantization circuit 6 described above. This encoding is a process of converting the pixel data PDI from which the minimum value has been removed to a representative level. The maximum value (referred to as maximum distortion) of the m-childization distortion that occurs during this quantization is set to a predetermined value, for example, 4.

FIG. 13A shows a case where the dynamic range DR is 8. In the case of (DR=8), the center level 4 is set as the representative level LO, and (maximum distortion E=4). In other words,(
When 0≦DR≦8), the center level of the dynamic range is taken as the representative level, and there is no need to transmit quantized data. Therefore, the required bit length is O.

On the receiving side, decoding is performed using the minimum value MIN and dynamic range DR of the block using the representative level LO as a restored value.

FIG. 13B shows the case where (DR=17), the representative levels are determined as (LO=4) and (L1=13), respectively, and the maximum distortion E is 4. Since there are two representative levels LO and Ll, the bit length is 1.

If (9≦DR≦17), the bit length is 1.

The maximum distortion E becomes smaller as the dynamic range DR becomes narrower. Figure 13C shows the case where (DR=35), and the representative level is (LO=4) (LL=13) (L2=22) ( L3
=31), and (E=4). Since there are four representative levels LO to L3, the bit length is two.

In the case of (18≦DR≦35), the bit length is set to 2.

In the case of (36≦DR≦71), eight representative levels (
LO to L7) are used. The 13th diagram is (DR=7
1), the representative level is (L O = 4) (L
1 = 13) (L 2 = 22) (L 3 =
31) (L4=40) (L5=49) (L6=58) (
L7=67). 8 representative level LOs
For the ~L7 distinction, the required bit length is 3.

In the case of (72≦DR≦143), 16 representative levels (LO-L15) are used. Figure 13E is (D
R=143), and the representative level is (L8-7
6) (L9=85) (L10=94) (L11=10
3) (L12-112) (L13=121) (L14=
130) (L15-139) (LO to L7 are the same as the above values). 16 representative levels (LO-L
15) requires 4 bits.

In the case of (144≦DR≦287), 32 representative levels (LO to L31) are used. Figure 13F is (
DR=287), and the representative level is (L16=
148) (L17=157) (L18=166) (L1
9=175)...(L27=247)(L2
8=256)(L29=265)(L30=274)(
L31=283) (LO to L15 are the same values as above)
It is determined that Five bits are required to distinguish among the 32 representative levels (LO to L31). Actually, since the input pixel data is quantized with 8 bits, the maximum value of the dynamic range DR is 255, and it is not quantized to the representative level (L28 to L31).

Television signals within one block are horizontal.

Since there is a two-dimensional correlation in the vertical direction and a three-dimensional correlation in the temporal direction, in the stationary part, the range of change in the level of pixel data included in the same block is small. The minimum level M shared by
Even if the dynamic range of the data DTI after removing IN is quantized using a smaller number of quantization bits than the original number of quantization bits, almost no quantization distortion occurs. By reducing the number of quantization bits, the data transmission bandwidth can be made narrower than the original one.

g. Modified Example When performing encoding adapted to the dynamic range, for example, when dividing the dynamic range into four and quantizing it into four representative levels, as shown in FIG. 14, the minimum value M I N is used as the representative level. In the case of variable length encoding, the representative level may be set to a fixed value for each bit length.

Furthermore, dynamic range adaptive encoding with a fixed bit length may be used. Furthermore, in the present invention, high-efficiency encoding methods other than the dynamic range adaptive encoding method may be combined.

〔Effect of the invention〕

In the stationary part where the variation width of the brightness level is small,
The subsampling thinning ratio is increased, and on the other hand, the subsampling thinning ratio is decreased in areas where the brightness level changes widely, so that the data to be transmitted can be reduced without deterioration of image quality such as aliasing distortion. The amount of data is sufficiently reduced compared to the original data, and the transmission band can be narrowed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the receiving side, FIG. 3 is a route diagram used to explain blocks that are units of encoding processing, and FIG. 4 , FIG. 5 and FIG. 6 are an example of the configuration of a blocking circuit, a route map and a timing chart for explaining the same, FIG. 7 is a block diagram of an example of a dynamic range detection circuit, and FIG. 8 is a variable subsampling circuit. Block diagram of an example, No. 9
The figure is a route diagram for explaining the operation of the variable subsampling circuit, Figures 10 and 11 are block diagrams of an example of the subsampling circuit and timing charts for explaining its operation, and Figures 12 and 13 are quantum A block diagram of an example of a quantization circuit and a route diagram for explaining its operation, and FIG. 14 is a route diagram used for explaining another example of quantization. Explanation of important symbols in the drawing ■ = Digital television signal input terminal, 2-niblock conversion circuit, 3: Dynamic range detection circuit,
4: Variable subsampling circuit, 6: Quantization circuit, 7
;Framing circuit. Agent: Tadashi Sugiura, Patent Attorney: Tadashi Sugiura, Book A, 71, 1, Figure 2, Town General Construction, 7° Linf, Figure 8, Figure 9, Figure 13A, Figure 13B, Figure 13C 13 Diagram 13F

Claims (1)

[Scope of Claims] Means for determining the dynamic range of each block consisting of areas belonging to the same field or a plurality of consecutive fields of a digital image signal; 1. A high-efficiency encoding device comprising: means for subsampling.