JP2518215B2 - High efficiency encoder - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a high-efficiency coding apparatus for compressing the number of bits per pixel of image data such as digital television signals.

[Outline of Invention]

According to the present invention, in a high-efficiency coding device applied when transmitting a digital video signal, a television screen is divided into a large number of two-dimensional blocks or three-dimensional blocks, and narrowed by the correlation of pixels in each block. The number of bits of pixel data in a block can be compressed by variable-length coding that adapts to the dynamic range, and the compressed code signal is coded by vector quantization for each number of bits of the code signal. The efficiency of conversion is extremely high.

[Conventional technology]

As a video signal coding method, some high-efficiency coding methods are known in which the average number of bits per pixel or the sampling frequency is reduced for the purpose of narrowing the transmission band.

As one of the quantization methods capable of high compression, a screen of one frame is divided into blocks of m pixels, an area in an m-dimensional vector space is divided into n, and n reference blocks are formed. For each block of actual data, the one with the minimum coding distortion is selected from the reference blocks, and the pattern number is transmitted as an index code.
On the receiving side, vector quantization is known in which a representative vector indicated by an index code is restored using a codebook.

Since vector quantization only needs to transmit an index code, a high compression rate can be obtained. However, in order to guarantee the faithfulness at the time of restoration, even if the patterns are similar, if the DC level and the gain are different, they are processed as different patterns, and therefore the number of reference blocks is, for example, (n =
2 ¹⁰ ), the coding efficiency is low, and
There is a problem that the circuit scale becomes extremely large.

In order to improve this point, a method of normalizing the pixel data by the average value of the pixel data of the block and the standard deviation of the amplitude distribution has been considered. However, if the pixel data is 8
Since it is a bit, even if the above-mentioned normalization is performed, the coding efficiency does not become sufficiently high.

[Problems to be solved by the invention]

The present invention is intended to increase the coding efficiency and reduce the circuit scale by combining the previously proposed variable-length coding method adapted to the dynamic range with the vector quantization method.

That is, the applicant of the present application obtains a dynamic range defined by a maximum value and a minimum value of a plurality of pixels included in a two-dimensional block as described in Japanese Patent Application No. 59-266407, and obtains the dynamic range. We have proposed a high-efficiency coding device that performs coding adapted to the range. Also, as described in Japanese Patent Application No. 60-232789, a high-efficiency coding apparatus that performs coding suitable for a dynamic range with respect to a three-dimensional block formed from pixels in an area included in each of a plurality of frames. Has been proposed. Further, as described in Japanese Patent Application No. 60-268817, there is a variable length coding method in which the number of bits changes according to a dynamic range in which the maximum distortion generated when performing quantization is constant. Proposed.

An object of the present invention is to apply the above-mentioned variable length coding method adapted to the dynamic range and perform the normalization and the pattern classification by the variable length coding adapted to the dynamic range before performing the vector quantization. The object of the present invention is to provide a high-efficiency coding device which can improve coding efficiency and has a small circuit scale.

[Means for solving problems]

According to the present invention, a maximum value MAX of a plurality of pixel data and a minimum value of a plurality of pixel data included in a two-dimensional block of a digital image signal or a block consisting of N areas belonging to each of N temporally consecutive frames. A dynamic range detection circuit that detects the dynamic range DR of each block from the maximum value MAX and the minimum value MIN, and the minimum value MIN is subtracted from the values of multiple pixel data, and the input data after removal of the minimum value is calculated. The subtraction circuit that forms the code signal is encoded with the number of quantization bits that is less than the original number of quantization bits of the input data after removal of the minimum value in the detected dynamic range DR and that corresponds to the dynamic range DR. A quantization circuit that generates a DT, a vector quantization circuit that vector-quantizes the code signal DT for each number of quantization bits of the code signal DT, and a dyna A high-efficiency code, comprising a mic range information, a framing circuit that transmits at least two additional codes of the maximum value MAX and the minimum value MIN, and a code signal obtained by vector quantization. It is an oxidizer.

[Action]

Since the television signal has a three-dimensional correlation in the horizontal direction, the vertical direction, and the time direction, the level change range of the pixel data included in the same block is small in the stationary part. Therefore, even if the dynamic range of the data PDI after removing the minimum level MIN shared by the pixel data in the block is quantized with a quantization bit number smaller than the original quantization bit number, quantization distortion hardly occurs. .

Further, removing the minimum value for each block means normalization for removing the difference in DC level between pixel data of blocks. Furthermore, the dynamic range of each block
Pattern classification based on the dynamic range DR is performed by variable length coding of the number of bits according to DR. The code signal obtained by the coding adapted to this dynamic range is vector-quantized. The code signal obtained by encoding adapted to the dynamic range has the bit number of one pixel compressed, and the difference in DC level is removed. Therefore, normalization processing must be performed during vector quantization. There is no need to perform it, and the coding efficiency can be made extremely high. However, since the patterns are classified, vector quantization corresponding to the number of bits of the code signal is performed very efficiently.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. This description will be given in the following order.

a. Configuration of transmitting side b. Configuration of receiving side c. Block and blocking circuit d. Dynamic range detection circuit e. Quantization circuit f. Modified example a. Configuration of transmitting side FIG. 1 shows the transmitting side of the present invention. The configuration of (recording side) is shown as a whole. For example, a digital video signal (digital luminance signal) in which one sample is quantized into 8 bits is input to an input terminal indicated by 1. This digital video signal is supplied to the blocking circuit 2.

The block circuit 2 converts the input digital video signal into a continuous signal for each two-dimensional block which is a unit of encoding. In this embodiment, one block has a size of (8 lines × 8 pixels = 64 pixels). The output signal of the blocking circuit 2 is supplied to the dynamic range detection circuit 3 and the subtraction circuit 4. The dynamic range detection circuit 3 determines the dynamic range DR and the minimum value for each block.
Detect MIN. Pixel data PD from blocking circuit 2
Is supplied to the subtraction circuit 4, and in the subtraction circuit 4, the minimum value
Pixel data PDI from which MIN has been removed is formed.

Further, the detected dynamic range DR is supplied to the bit number determination circuit 4 and the quantization circuit 5. The bit number determination circuit 4 determines the number of bits Nb adapted to the dynamic range DR of each block among (0 to 4 bits). As will be described later, the quantization circuit 5 adapts the dynamic range DR to quantize the pixel data PDI with the number of bits Nb. The fact that the number of bits Nb is 0 means that the levels of the pixels in the block are substantially equal, and only the minimum value MIN and the dynamic range DR need be transmitted.

The code signal DT generated from the quantizing circuit 6 is supplied to the vector quantizing circuits 7A, 7B, 7C and 7D. The vector quantization circuit 7A performs 1-bit vector quantization to generate a 1-bit index code. Vector quantization circuit 7B
Performs 2-bit vector quantization to generate a 2-bit index code. The vector quantization circuit 7C
3-bit vector quantization is performed to generate a 3-bit index code. The vector quantization circuit 7D performs 4-bit vector quantization to generate a 4-bit index code. Variable-length coding adapted to the dynamic range DR means that pattern classification is performed based on the dynamic range DR.

The index code obtained at the output of these vector quantization circuits 7A to 7D is supplied to the selection circuit 8. The selection circuit 8 selects the index code from the vector quantization circuit indicated by the bit number Nb from the bit number determination circuit 4.

In the vector quantization circuits 7A to 7D, between the code signal DT of (8 × 8 = 64 pixels, 1 pixel is 1 to 4 bits) from the quantization circuit 6 and, for example, (2 ¹⁰ = 1024) reference blocks. The pattern comparison is carried out at, and a 10-bit index code DV corresponding to the reference block with the smallest coding distortion is generated. As the pattern comparison, for example, a method can be used in which the distance between corresponding pixels between the input block and the reference block is obtained, and the reference block having the smallest distance is searched.

The dynamic range DR, the minimum value MIN, and the index code DV are supplied to the framing circuit 9. The framing circuit 9 converts the dynamic range DR, the minimum value MIN, and the index code DV into serial data, performs error correction coding processing on the index code DV and the above-mentioned additional code, and adds a synchronization signal. Transmission data is obtained at the output terminal 10 of the framing circuit 9, and this transmission data is sent to a transmission line such as a digital line.

As described above, the encoded code DT has a variable number of bits for each block, but the number of bits of pixel data of the block is uniquely determined from the dynamic range DR in the additional code. Therefore, there is an advantage that it is not necessary to insert a redundant code indicating a data delimiter in the transmission data, although the variable length code is adopted.

b. Configuration on the receiving side FIG. 2 shows the configuration on the receiving (or reproducing) side. The received data from the input terminal 11 is supplied to the frame decomposition circuit 12. Index code by frame disassembly circuit 12
The DV and the additional codes DR and MIN are separated and error correction processing is performed. The index code DV is supplied to the representative vector generation circuits 13A to 13D, and the block data (representative vector) corresponding to the index code DV is decoded by referring to the code block. This representative vector is supplied to the selection circuit 14. The selection circuit 14 is controlled by the number of bits Nb and selects a representative vector of the number of bits corresponding to the number of bits Nb. The output signal of the selection circuit 14 is supplied to the decoding circuit 15.

The decoding circuit 15 performs a process reverse to that of the quantization circuit 6 on the transmission side. That is, the data after the removal of the 8-bit minimum level is decoded into the representative level, this data and the 8-bit minimum value MIN are added by the addition circuit 16, and the original pixel data is decoded. The output data of the adder circuit 16 is supplied to the block decomposition circuit 17. The block decomposing circuit 17 is a circuit for converting the decoded data in the order of blocks into the same order as the scanning of the television signal, contrary to the blocking circuit 2 on the transmitting side. The decoded television signal is obtained at the output terminal 18 of the block decomposition circuit 17.

c. Block and Blocking Circuit A block, which is a unit of coding, will be described with reference to FIG. In this example, by dividing the screen of one field, a large number of two-dimensional blocks (8 lines × 8 pixels) shown in FIG. 3 are formed. In FIG. 3, a solid line indicates an odd field line, and a broken line indicates
The lines of even fields are shown. Unlike this example, N 2 frames belonging to each frame of N frames that are temporally consecutive are included.
The present invention can be applied to a three-dimensional block composed of a three-dimensional area.

The blocking circuit 2 will be described with reference to FIGS. 4, 5 and 6. For the sake of simplicity of explanation, it is assumed that the screen of one field has a configuration of (4 lines × 8 pixels) as shown in FIG. 5, and this screen is divided into two vertically and horizontally as shown by the broken line. Divided into 4 parts, (2 lines x 2
A case where eight blocks of (pixels) are formed will be described.

In FIG. 4, as shown in FIG. 6A, input data A consisting of 4 lines (Th _{0 to} Th ₃ ) is applied to the input terminal indicated by 21.
And a sampling clock B (FIG. 6B) synchronized with the input data A is supplied to the input terminal indicated by 22. The numbers (1 to 8) indicate the sample data of the line Th ₀ , the numbers (11 to 18) indicate the sample data of the line Th ₁ , and the numbers (21 to 28) indicate the sample data of the line Th ₂ . , And the numbers (31-38) are the line Th ₃
The sample data of each is shown. The input data A is supplied to the delay circuit 23 having a delay amount of Th and the delay circuit 24 having a delay amount of 2Ts (Ts: sampling period). Further, the sampling clock B is supplied to the 1/2 frequency dividing circuit 27.

The output signal C of the delay circuit 24 (FIG. 6C) is a switch circuit.
The delay circuit 23 is supplied to one of the input terminals of 25 and 26, respectively.
Output signal D (FIG. 6D) is supplied to the other input terminals of the switch circuits 25 and 26, respectively. The switch circuit 25 is 1 /
Controlled by the output signal E of the divide-by-2 circuit 27 (Fig. 6E), the switch circuit 26 outputs the pulse signal E as an inverter.
It is controlled by the pulse signal inverted by 28. The switch circuits 25 and 26 alternately select the input signal (C or D) every 2Ts. The output signal F from the switch circuit 25 is shown in FIG. 6F, and the output signal G from the switch circuit 26 is shown in FIG. 6G.

The output signal F of the switch circuit 25 is the first signal of the switch circuit 29.
Input terminal and a delay circuit 30 having a delay amount of 4 Ts. The output signal G of the switch circuit 26 is supplied to the delay circuit 31 having a delay amount of 2Ts. The output signal H of the delay circuit 30 (FIG. 6H) is supplied to the third input terminal of the switch circuit 29. The output signal I (FIG. 6I) of the delay circuit 31 is supplied to the second input terminal of the switch circuit 29 and the delay circuit 32 having a delay amount of 4Ts. The output signal J (FIG. 6J) of the delay circuit 32 is supplied to the fourth input terminal of the switch circuit 29.

The output signal of the 1/2 divider circuit 27 is supplied to the 1/2 divider circuit 33, and the output signal K (K in FIG. 6) is formed. The switch circuit 29 is controlled by the signal K, and the first and second switching is performed every 4Ts.
The second, third and fourth input terminals are sequentially selected. Therefore,
Signal L output from switch circuit 29 to output terminal 34
Is as shown in FIG. 6L. That is, the order of each field of data is the order of each block (for example, 1 → 2 → 11).
→ Converted to 12). Of course, the actual number of pixels in one field is much larger than the example shown in FIG. 5,
By the same scan conversion as described above, conversion is performed in the order of each block shown in FIG.

d. Dynamic Range Detection Circuit FIG. 7 shows an example of the configuration of the dynamic range detection circuit 3. As described above, the block circuit 2 sequentially supplies the input terminal indicated by 41 with image data of an area in which encoding is required for each block. The pixel data from the input terminal 41 is supplied to the selection circuit 42 and the selection circuit 43. One of the selection circuits 42 selects and outputs the one having a higher level between the pixel data of the input digital video signal and the output data of the latch 44. Other selection circuit 43
Is the pixel data of the input digital video signal and the latch 45
From the output data of, the one with the smaller level is selected and output.

The output data of the selection circuit 42 is supplied to the subtraction circuit 46 and is also captured by the latch 44. The output data of the selection circuit 43 is supplied to the subtraction circuit 46 and the latch 48, and is also captured by the latch 45. A latch pulse is supplied from the control unit 49 to the latches 44 and 45. Timing signals such as a sampling clock and a synchronizing signal which are synchronized with the input digital video signal are supplied from the terminal 50 to the controller 49. The control unit 49 supplies a latch pulse to the latches 44 and 45 and the latches 47 and 48 at a predetermined timing.

At the beginning of each block, the contents of latches 44 and 45 are initialized. All of the data of "0" is initialized to the latch 44, and all of the data of "1" is initialized to the latch 45. The maximum level is stored in the latch 44 among the pixel data of the same block that are sequentially supplied. In addition, the minimum level is stored in the latch 45 among the pixel data of the same block that is sequentially supplied.

When the detection of the maximum level and the minimum level is completed for one block, the maximum level of the block occurs at the output of the selection circuit 42. On the other hand, the minimum level of the block occurs at the output of the selection circuit 43. Latches 44 and 45 are reinitialized when the detection for one block is complete.

The output of the subtraction circuit 46 is the maximum level from the selection circuit 42.
The dynamic range DR of each block is obtained by subtracting MAX and the minimum level MIN from the selection circuit 43. These dynamic range DR and minimum level MIN are latched in the latches 47 and 48 by the latch pulse from the control block 49, respectively. The dynamic range DR of each block can be obtained at the output terminal 51 of the latch 47, and the output terminal 52 of the latch 48 can be obtained.
The minimum value MIN of each block is obtained.

e. Quantization circuit The quantization circuit 6 performs variable-length coding adapted to the dynamic range DR. FIG. 8 shows an example of the quantization circuit 6. In FIG. 8, the ROM indicated by 55 stores a data conversion table for converting the pixel data PDI (8 bits) after the minimum value removal into a compressed bit number. The number of bits Nb (generated in the number-of-bits determination circuit 4) from the input terminal 56 and the pixel data PDI from the input terminal 57 are supplied to the ROM 55 as address signals.

In the ROM 55, the data conversion table is selected according to the number of bits Nb, and the code signal DT is taken out at the output terminal 58.
The number of bits of the code signal DT changes in the range of 0 bit to 4 bits. Therefore, the number of effective bits in the code signal output from the ROM 55 changes. Valid bits are supplied to the vector quantization circuits 7A to 7D, respectively.

FIG. 9 is used to explain the variable bit number coding adapted to the dynamic range performed by the quantizing circuit 6. This encoding is a process of converting the pixel data PDI from which the minimum value has been removed into a representative level.
The allowable maximum value of the quantization distortion (referred to as maximum distortion) that occurs during this quantization does not exceed a predetermined value, for example 5.

FIG. 9A shows a case where the dynamic range DR (the difference between the maximum value MAX and the minimum value MIN) is 16. In the case of (DR = 16), the central level 8 is the representative level L10, and the maximum distortion E = 8. That is, when (0 ≦ DR ≦ 16),
The central level of the dynamic range is the representative level, and it is not necessary to transmit quantized data. Therefore, the required number of bits Nb is 0. On the receiving side,
From the minimum value MIN of the block and the dynamic range DR, decoding is performed with the representative level L0 as the restoration value.

FIG. 9B shows the case of (DR = 50), and the representative levels are determined to be (L0 = 8) (L1 = 25). Since there are two representative levels L0 and L1, (Nb = 1). (17 ≦ DR ≦ 5
In the case of 0), (Nb = 1).

FIG. 9C shows the case of (DR = 118), and the representative levels are determined to be (L0 = 8) (L1 = 25) (L2 = 42) (L3 = 59), respectively, and (E = 8) is there. Since there are four representative levels L0 to L3, (Nb = 2). In the case of (51 ≦ DR ≦ 118), (Nb = 2).

In the case of (119 ≦ DR ≦ 254), eight representative levels (L0
~ L7) is used. FIG. 9D shows the case of (DR = 254), and the representative level is (L0 = 8) (L1 = 25) (L2 = 42).
(L3 = 59} (L4 = 76) (L5 = 93) (L6 = 110) (L7 = 12
7). In order to distinguish the eight representative levels L0 to L7, (Nb = 3) is set.

In the case of (DR = 255), 16 representative levels (L0 to L1
5) is used. FIG. 9E shows the case of (DR = 261), and the representative level is (L8 = 144) (L9 = 161) (L10 = 178).
(L11 = 185) (L12 = 202) (L13 = 219) (L14 = 236)
(L15 = 253) (L0 to L7 are the same as the above values). In order to distinguish 16 representative levels (L0 to L15), (N
b = 4).

Even in the case of 8 bits, the actual value of the dynamic range DR is limited to about 200, so the maximum distortion in the case of 4 bits can be made smaller than 8, and as described above, the lossless code Maximum dynamic range without conversion
Considering that the rate of DR occurrence is small, it is possible to make modifications such as the number of bits being compressed or the maximum distortion being made smaller.

Since the television signals in one block show a three-dimensional correlation in the horizontal and vertical two-dimensional directions and in the time direction, in the steady part, the variation range of the level of pixel data included in the same block is small. Therefore, even if the dynamic range of the data DTI after removing the minimum level MIN shared by the pixel data in the block is quantized by the quantization bit number smaller than the original quantization bit number, the quantization distortion hardly occurs. . By reducing the number of quantization bits, the data transmission bandwidth can be made narrower than the original transmission bandwidth.

f. Modified Example In this one embodiment, as is apparent from FIG. 9, the median values L0, L1, L of each region formed by dividing the dynamic range.
2, L3 ... are used as the values when decrypting. This encoding method can reduce quantization distortion.

On the other hand, pixel data having the minimum level MIN and the maximum level MAX always exist in one block. Therefore, in order to increase the code signal with zero error,
As shown in Fig. 10, the dynamic range DR is (2 ^m -1)
(However, m is the number of quantization bits)
MIN may be the representative minimum level L0 and maximum level MAX may be the representative maximum level L3. The example in FIG. 10 shows a case where the number of quantization bits is 2 for simplicity.

In the above description, the index code DV, the dynamic range DR, and the minimum value MIN are transmitted. However, instead of the dynamic range DR as an additional code, the maximum value
MAX, quantization steps or maximum distortion may be transmitted.

Further, one block of data may be simultaneously taken out by a circuit combining a frame memory, a line delay circuit, and a sample delay circuit.

〔The invention's effect〕

According to the present invention, by vector quantization, the amount of data to be transmitted can be sufficiently reduced as compared with the original data, and the transmission band can be narrowed. In particular, according to the present invention, since the variable length coding adapted to the dynamic range is performed before the vector quantization, the normalization processing for removing the dynamic range and the pattern classification based on the dynamic range are performed. The coding efficiency of is extremely high, and the circuit scale can be reduced as compared with the conventional one. The encoding method adapted to the dynamic range has an advantage that the original pixel data can be almost completely restored from the received data in the stationary part where the change width of the luminance level is small, and there is almost no deterioration in image quality. It is suitable in combination with quantization.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram showing a configuration of a receiving side, and FIG. 3 is a schematic diagram used for explaining a block which is a unit of encoding processing. FIG. 5, FIG. 5 and FIG. 6 are schematic diagrams for explaining the blocking circuit, a block diagram of an example of the blocking circuit and a time chart for explaining the operation, and FIG. 7 is a dynamic range detecting circuit. Block diagram, FIG. 8 is a block diagram of an example of a quantization circuit, FIG. 9 is a schematic diagram for explaining variable length coding, and FIG. 10 is a schematic line for explaining another example of quantization. It is a figure. Description of main symbols in the drawings 1: Digital video signal input terminal, 2: Blocking circuit, 3: Dynamic range detection circuit, 4: Bit number determination circuit, 6: Quantization circuit, 7A, 7B, 7C, 7D: Vector quantization circuit,
8: selection circuit, 9: framing circuit.

Claims (1)

(57) [Claims] 1. A maximum value of a plurality of pixel data and a minimum value of the plurality of pixel data included in a two-dimensional block of a digital image signal or a block consisting of N areas belonging to each of N temporally continuous frames. While seeking the value,
Means for detecting the dynamic range of each block from the maximum value and the minimum value; means for subtracting the minimum value from the values of the plurality of pixel data to form input data after removal of the minimum value; Within the dynamic range, the input data after removal of the minimum value is coded with a smaller number of quantization bits than the original number of quantization bits, and the number of quantization bits according to the detected dynamic range, and the number of bits is for each block. Means for generating a code signal to be determined, means for vector quantizing the code signal for each quantization bit number of the code signal, dynamic range information, and at least two of the maximum value and the minimum value A high-efficiency coding device comprising an additional code and means for transmitting the code signal obtained by the vector quantization.