JP2547479B2 - Image coding control system - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image coding control system for highly efficiently coding an input image signal.

In order to reduce the bit rate of an image signal of a moving image or the like, a method of performing high efficiency coding by performing orthogonal transform coding for each processing block obtained by dividing one screen into a plurality of blocks is known. It is desired to reduce the circuit scale in such a high efficiency coding system.

BACKGROUND ART FIG. 1 is a block diagram of a main part of a conventional example. The image signal for a moving image or the like is applied to the orthogonal transform encoder 1. The orthogonal transform encoder 1 is a Fourier transform (Fourier Transform).
sform), Hadamard transform, Discrete Cosine transform (DCT), or the like, or can be combined with predictive coding such as interframe coding. . Recently, a structure based on the discrete cosine transform (DCT) has been put into practical use. Further, the size of the processing block for performing the orthogonal transform coding is, for example, about 8 to 16 pixels in the case of one-dimensional, and about 8 × 8 to 16 × 16 pixels in the case of two-dimensional.

The pixel signal is subjected to orthogonal transform coding for each processing block in the orthogonal transform encoder 1 and added to the variable length encoder 2 to be converted into a variable length code which assigns a short code to a signal having a high occurrence probability, and the buffer memory 3 The data width of the data is aligned and added to the buffer memory 3. This buffer memory 3
The data read from is transmitted to a transmission line or the like.

On the receiving side of the variable-length code signal, the variable-length decoder converts the variable-length code into a fixed-length code, and the orthogonal transform decoder reproduces the image signal by a process reverse to that of the orthogonal transform coding. In addition to that, the image will be displayed.

In the image coding system of the conventional example described above, for example, orthogonal transform coding is performed using n × m pixels (n and m are arbitrary integers) as a processing block, and all effective coefficients whose transform coefficients are not 0 are variable length. The encoder 2 converts the variable-length code output to a variable-length code. Therefore, the variable-length encoder 2 needs to have the ability to perform variable-length coding on a maximum of n × m signals and make the data width of the buffer memory 3 uniform. Become. Therefore, the circuit scale becomes large.

Further, the transformation coefficient on the high-frequency component side tends to be 0 due to the orthogonal transformation. Therefore, it is possible to reduce the circuit scale by processing only the transformation coefficient on the low-frequency component side. Since there is no possibility of this, the reproduced image quality may be greatly deteriorated.

DISCLOSURE OF THE INVENTION It is an object of the present invention to provide an image coding control system in which the above problems have been improved. More specifically, the object of the present invention is to perform high-efficiency coding without degrading coding characteristics. An object of the present invention is to provide an image coding control system capable of reducing the circuit scale.

The above-mentioned object is an orthogonal transform coding means for performing orthogonal transform coding for each block obtained by dividing one screen of an input image signal into a plurality of blocks, each block having transform coefficients for a plurality of pixels; Code control means for controlling the output of transform coefficients until the number of effective coefficients of the transform coefficients output from the orthogonal transform coding means reaches a predetermined number so that the number of variable-length codewords to be used becomes a predetermined number or less;
Variable length coding means for converting each conversion block output from the code control means into a variable length coding output; and a buffer for temporarily storing the variable length coding output for each block output from the variable length coding means This is accomplished with an image coding control system having memory means.

Further, the above-mentioned object is an analog / digital conversion means for converting an analog image signal into a digital image signal;
Dividing means for time-divisionally dividing the digital image signal into l (l is an arbitrary integer) input image signal, the frequency of each l input image signal is lower than the frequency of the digital image signal; l inputs L orthogonal transform coding means provided for each signal and performing orthogonal transform coding for each block obtained by dividing one screen of the corresponding input image signal into a plurality of screens;
Each of the blocks has a transform coefficient for a plurality of pixels; the corresponding orthogonal transform coding is provided for each of the l orthogonal transform coding means, and the variable length codeword obtained for each block is equal to or less than a predetermined number. L code control means for controlling to output the transform coefficients until the number of effective coefficients among the transform coefficients output from the means reaches a predetermined number; provided for each l code control means, and corresponding code control Coefficient processing means for generating, for each block, data defining the variable-length coded output from the transform coefficient output from the converter; the data generated by the l coefficient processing means is selected in time division to form a data string. Selecting means for outputting; converting means for generating the variable length coded output from each data in the data string; and a buffer for temporarily storing the variable length coded output for each block output from the converting means. Image coding control system having a far memory means.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a conventional image coding control system; FIG. 2 is a block diagram showing a basic configuration of an image coding control system of the present invention; and FIG. 3 is an image shown in FIG. FIG. 4 is a block diagram showing an embodiment of an encoding control system; FIG. 4 is a block diagram showing the configuration of the code controller shown in FIG. 3 when a two-dimensional variable length code is used; FIG. 5B is a diagram showing a conventional image coding process when a code is used; FIG. 5B is a diagram showing an image coding process according to the present invention when a two-dimensional variable length code is used; and FIG. 6 is a two-dimensional variable length code. FIG. 7 is a diagram showing the operation of the code controller shown in FIG. 4 in the case of using; FIG. 7 is a block diagram showing the configuration of the variable length encoder shown in FIG. 3 in the case of using a two-dimensional variable length code; 8 is a diagram showing the operation of the variable length encoder shown in FIG. 7; FIG. 9A is shown in FIG. FIG. 9B is a diagram showing the input / output relationship of the ROM; FIG. 9B is a diagram showing the input / output relationship of the encoding table shown in FIG. 7; FIG. 10 is a block diagram showing the rotator shown in FIG. 7; FIG. 12 is a diagram showing a configuration of the code controller shown in FIG. 3 when a length code is used; FIG. 12A is a diagram showing a conventional image coding process when a run length code is used; FIG. 12B is a run length code. FIG. 13 is a diagram showing an image encoding process according to the present invention in the case of using; FIG. 13 is a diagram showing the operation of the code controller shown in FIG. 11; FIG. 14 is a diagram showing the input / output relationship of the ROM shown in FIG. FIG. 15 is a diagram showing the configuration of the variable length encoder shown in FIG. 3 when a run length code is used; FIG. 16 is a diagram showing the input / output relation of the ROM shown in FIG. 15; FIG. 18 is a diagram showing the operation of the variable length encoder shown in FIG. 15; FIG. 18B is a diagram showing an input / output relationship regarding effective coefficients in the coding table shown in FIG. 15; FIG. 19A is a block diagram of a conventional image coding system having a parallel configuration; FIG. 20A is a block diagram of an image coding system having a parallel configuration according to a second embodiment of the present invention; FIG. 20A is a block diagram showing a transmission system having a conventional image coding control system having a parallel configuration shown in FIG. 18A; FIG. 20B is a block diagram showing a transmission system having an image coding control system having the parallel configuration of the second embodiment of the present invention shown in FIG. 18B; FIG. 21 is an image of the third embodiment of the present invention. FIG. 22A is a block diagram showing an encoding control system; FIG. 22A is a diagram showing problems that may occur in the first, second and third embodiments; FIG. 22B is a solution for the problems shown in FIG. 22A. And FIG. 23 shows a fourth embodiment of the present invention. Is a block diagram showing the configuration of an image encoding system.

BEST MODE FOR CARRYING OUT THE INVENTION The image coding control system of the present invention controls the number of variable-length codes obtained for each block so as to be a certain number or less, see FIG. And explain.

The image coding control system of the present invention is an orthogonal transform encoder.
10, variable length encoder 12, buffer memory 13 and code controller
Have 14. Orthogonal transform encoder 10 outputs 1 of the input image signal.
Orthogonal transform coding is performed for each processing block obtained by dividing the screen portion into a plurality of blocks. The code controller 14 controls the output of the orthogonal transform encoder 10 so that the number of variable-length code words obtained by the variable-length encoder 12 for each processing block is equal to or less than a predetermined number. The variable-length encoder 12 performs variable-length encoding on the output signal of the code controller 14 and aligns it with the data width of the buffer memory 13. The buffer memory 13 temporarily stores the variable-length coded output of the variable-length encoder 12. The orthogonal transform coded signal from the orthogonal transform encoder 10 is encoded using the image signal and the output of the code controller 14 and is given to the code controller 14.

Generally, there are a plurality of effective coefficients for each processing block by the orthogonal transform encoder 10. The code controller 14 controls the output of the orthogonal transform encoder 10, that is, the transform coefficient, so that the number of variable-length code words obtained by the variable-length encoder 12 for each processing block is equal to or less than a predetermined number. With this configuration, the variable-length encoder 12 has a circuit scale capable of processing a predetermined number or less of variable-length codewords, so that the size can be reduced as compared with the conventional example. Further, even if the low-frequency component side has a small number of effective coefficients and the high-frequency component side has a large number of effective coefficients due to the orthogonal transform coding, the high-frequency component side can be processed, and the deterioration of the reproduced image quality can be suppressed.

FIG. 3 is a block diagram showing a more detailed configuration of the image coding control system shown in FIG. The image coding control system shown is a discrete cosine transform block (DCT) 2
1, subtractor 22, quantizer 23, code controller 24, variable length encoder 2
5, it has a buffer memory 26, an inverse quantizer 27, an adder 28, a frame memory 29, and a quantization controller 30. In this embodiment, the orthogonal transform encoder 10 shown in FIG. 2 is replaced by a discrete cosine transform unit 21, a subtractor 22, a quantizer 23, an inverse quantizer 27, an adder 28, which performs interframe coding. The case where it is configured by the frame memory 29 and the like is shown.

The input image signal is subjected to a discrete cosine transform in each processing block in a discrete cosine transformer 21, and a difference from the transform coefficient of the previous frame is obtained in a subtractor 22 to obtain a quantizer 23.
, And the difference is quantized and applied to the sign controller 24. The code controller 24 controls the quantized output input from the quantizer 23 for each processing block so that the quantized output is equal to or less than a predetermined number of variable-length codewords obtained by the variable-length coder 25.
Here, the variable length codewords are roughly classified into two types: two-dimensional variable length codes and run length codes. The code controller 24 has a different configuration depending on which variable-length code word is used. The configuration of the code controller 24 will be described in detail later.

The variable-length coded output of the variable-length encoder 25 is temporarily stored in the buffer memory 26 and read by the configuration described later,
It is sent to the transmission line. The quantization controller 30 monitors the occupied amount of the buffer memory 26 and controls the quantization steps of the quantizer 23 and the inverse quantizer 27 so that overflow or underflow does not occur. The control information of the quantization step is transmitted to the receiving side together with the variable length coded output.

The difference between the transform coefficients inversely quantized by the inverse quantizer 27 is added to the contents of the previous frame (block) in the adder 28, added to the frame memory 29, and read when the next frame is processed. To be done.

FIG. 4 is a code controller using a two-dimensional variable length code.
It is a block diagram which shows the structure of 24 (1st Example). The code controller 24 includes a comparator 101, a counter 102, a comparator 103, and a delay device 10.
4 and selector 105. The comparator 101 includes a quantizer 23.
The quantized output (transformation coefficient) from (FIG. 3) is compared with 0, and when it is other than 0, a signal (pulse signal) instructing the count-up is output to the counter 102. While being instructed to count up, the counter 102 counts the pulse signal instructing to count up. The counter 102 is cleared by the block synchronization signal indicating the block break. That is,
The counter 102 counts the pulse signal instructing the count-up for each block. The comparator 103 outputs a select signal for the selector 105 to select 0 when the count value of the counter 102 exceeds a predetermined threshold value TH1. Delay device 10
Numeral 4 delays the quantized output in order to synchronize the generation of the select signal with the quantized output. Selector 105 and comparator 103
0 is selected while the select signal from (1) is given, and the quantized output (transformation coefficient) from the delay device 104 is selected otherwise.

FIG. 5A (a) shows 1 output from the discrete cosine transformer 11.
When each block (one screen of the input image signal is divided into a plurality) is composed of 8 × 8 pixels, the quantizer 23
Shows the quantized output of a block output by. By performing zigzag scanning on the 8 × 8 block in FIG. 5A (a) as indicated by the arrow, the combination of (zero run, effective coefficient) forming the two-dimensional variable-length code shown in FIG. 5A (b) is obtained. . That is, the effective coefficient of the DC component on the upper left is 5
Has zero run (number of consecutive zeros), so
It is represented by (0,5), and the effective coefficient 7 obtained by the next zigzag scan is 10 because the zero run is (10,7)
It is represented by. Similarly, (3,2), (0,5), (3,2)
2), (7,15), (10,7). The high frequency components after this are all "0", so they are not processed. The variable length code word shown in FIG. 5A (b) is obtained from these zero runs and effective coefficients (EOB is an end of block signal for indicating the end of the block, and the block synchronization signal is active). Output).

FIG. 5A is based on the conventional method. In the case of the example shown, seven variable length coded outputs are obtained. In such a case, if it is statistically obtained that the deterioration of the reproduced image quality is small even if 6 variable-length code words (in this case, 6 effective coefficients) including the DC component except EOB are used. , It is not necessary to convey all seven variable length codewords. The code controller 24 performs the following processing on the quantized output so that the number of variable-length code words obtained from one block is equal to or less than a predetermined number (a number that can statistically ensure that deterioration of reproduced image quality is small). To be

FIG. 5B (a) shows the operation of the code controller 24 when the number of variable-length codewords is limited to 6 or less. A zigzag scan is performed on the block in FIG.
Once obtained, the effective coefficient after that is replaced with 0,
Output Figure 5B (a). Zigzag scanning of FIG. 5B (a) yields FIG. 5B (b).

The operation of the code controller 24 shown in FIG. 4 will be described with reference to FIG. The quantized output shown in FIG. 6 (A) is input to the comparator 101. The first input data is the effective coefficient "5". In this case, the comparator 101 outputs one pulse signal instructing the count up. The counter 102 counts this, and as a result, the count value becomes 1 (before this)
The counter 102 is cleared by the EOB signal). The count value 1 is the threshold value TH1 (eg TH1 = 6) in the comparator 103.
Compared to. In this case, the count value is 1, so the comparator
103 does not output the select signal. This allows delay 1
Quantization output via 04 (effective coefficient 5) is the selector as it is
After passing through 105, it is given as a code control output to the variable length encoder 25 (FIG. 3) (FIG. 6 (B)).

Next, “0” is input to the comparator 101. In this case, comparator 1
01 does not generate a pulse signal. Therefore, the counter 102
The count value of 1 remains 1.

After that, after several “0” s are continuously input, the effective count 7 is given to the comparator 101. In this case, the counter 102
Counts up by 1 and the count value becomes 2. Thereafter, the counter 102 increments by 1 each time an effective coefficient is input. The comparator 103 selects the select signal when the count value exceeds the threshold value (TH1 = 6).
Output to. Upon receiving this select signal, the selector 105 selects and outputs "0". As a result, the selector 1 is selected until the counter 102 is cleared by the block synchronization signal (EOB signal).
05 selects and outputs "0" (Fig. 6 (B)).

FIG. 7 is a block diagram showing a configuration of the variable length encoder 25 shown in FIG. 3 when the two-dimensional variable length code is used.
The variable length encoder 25 includes a coefficient processor 111 and an encoding table 112.
And a rotator 113. The coefficient processor 111 has a ROM 114, a delay device 115, a counter 116, and a memory 117. The ROM 114 stores the memory 11 when the code control output from the code controller 24 is not 0.
Output the write instruction signal to instruct writing to 7. When the sign control output is 0, the ROM instructs the 114 counter 116 to count up by 1. The delay device 115 delays the write instruction signal output from the ROM 114 to synchronize the processing.

FIG. 9A is a diagram showing the operation of the ROM 114. A block sync signal and a code control output are input as an address of the ROM 114, and a write instruction signal and data to the counter 116 are output. Note that "*" is don't care (arbitrary). Also,
The write instruction signal is a low active signal.

Returning to FIG. 7, the memory 117 functions as a buffer, and when the write instruction signal is given (0 (low)), the block synchronization signal and the count value of the counter 116 (0.
Number) and the effective coefficient. The encoding table 112 inputs the block synchronization signal, the count value, and the effective coefficient from the memory 117, and outputs the code length and the code word.

FIG. 9B is a diagram showing an input / output relationship of the encoding table 112. When the block synchronization signal is 0 (low level), the last two bits "10" of the code word indicate the EOB signal (low level block synchronization signal).

Returning to FIG. 7, the rotator 113 refers to the code length from the encoding table 112 in order to align the code word output from the encoding table 112 with the data width of the buffer memory 26 (FIG. 3). To produce a variable length encoded output from.

FIG. 8 is a waveform diagram showing the operation of the variable length encoder 25 when the code control output of FIG. 6 (B) is input. The block sync signal shown in FIG. 8 (A) is 0 at the end of one block.
Become (EOB). At this time, the memory 117 is shown in FIG.
The data shown in is written. As mentioned above, * means do
Indicates n't care. First, the code control output “5” is ROM114
To enter. At this time, the block synchronization signal is 1.
Therefore, as can be seen from FIG. 9A, the low-active write instruction signal becomes "0", and "0" is output to the counter 116. Therefore, as shown in FIG.
A block synchronization signal “1”, a count value “0”, and an effective coefficient “5” are written in 7.

After that, 10 "0" s continue in the code control output. The counter 116 counts up in order from "0" next to the effective coefficient "5". During this period, the write instruction signal is inactive ("1"). When the effective coefficient “7” is input to ROM114,
A write instruction signal is given from the ROM 114. The count value “10” of the counter 116 at this time is written in the memory 117 together with the effective coefficient “7” and the block synchronization signal “1”. The write instruction signal is delayed by the delay unit 115 and given to the counter 116. As a result, the counter 116 is cleared.

Thereafter, similarly, the data shown in FIG. 8 (F) is written in the memory 117. The encoding table 112 refers to the table shown in FIG. 9B and outputs the code length and the code word to the rotator 113.

FIG. 10 is a block diagram showing the configuration of the rotator 113.
The rotator 113 has a shift circuit 121, an adder 122, and a delay device 123. The code length from the coding table 112 shown in FIG. 7 is input to the adder 122. The output of the adder 122 is the delay device 123.
Is delayed by a unit time and added to the code length input by the adder 122. The addition result is the buffer memory 26 (Fig. 3).
When the data width exceeds the predetermined data width of, the adder 122 carries a carry. This carry is given to the buffer memory 26 as a write control signal. The code word from the encoding table 112 is shifted by the shift circuit 121 based on the output signal of the delay device 123. The shifted codeword is output to the buffer memory 26 as a variable length coded output.

Next, the code controller 24 when the run length code is used
The configuration of the variable length encoder 25 (second embodiment) will be described. First, the configuration of the code controller 24 will be described.

FIG. 11 is a block diagram showing the configuration of the code controller 24 when the run length code is used. Code controller 24 is RO
It has an M131, a counter 132, a comparator 133, a delay device 134, a delay device 135 and a selector 136. The ROM 131 inputs the quantized output from the quantizer (FIG. 3) and the signal NZR indicating whether the quantized output one coefficient before is "0", and the quantized output is other than "0". Or at the beginning of zero run, a pulse signal instructing the count-up is output to the counter 132.

FIG. 14 is a diagram showing the input / output relationship of the ROM 131. ROM131
The signal NZR and the quantized output are given as the address of the, and data is output to the counter 132 and the delay device 134, respectively.

Returning to FIG. 11, the counter 132 counts up by +1 each time the count-up is instructed, and is cleared by the block synchronization signal. The comparator 133 compares the count value of the counter 132 with a predetermined designated value TH2, and outputs a select signal to the selector 136 when the count value exceeds the threshold TH2. The threshold value TH2 is selected so that the variable length codeword obtained by the variable length encoder 25 for each block is equal to or less than a predetermined number. The delay device 134 is provided to synchronize the processing. The delay device 134 is cleared by the block synchronization signal, and its output becomes 1 (indicating that the coefficient one coefficient before is other than "0"). The delay device 135 synchronizes the select signal with the quantized output. The selector 136 selects “0” when the select signal is output, and otherwise selects the quantized output from the delay device 135. The output of the selector 135 is given to the variable length encoder 25 as a code control output.

By zigzag scanning one block in FIG. 12A (a), the number of “0” consecutive with the effective coefficient in FIG. 12A (b) can be obtained. In FIG. 12A (b), 0 × 10 indicates that 10 “0” s continue. In the conventional method, all effective coefficients in one block and the number of "0" in each zero run are calculated,
A variable length codeword as shown is output. In contrast,
In this embodiment, the code controller 24 controls the quantized output so that the number of variable-length codewords is equal to or less than a predetermined number.

FIG. 12B (a) shows the processing when the variable length coded output is limited to 6 or less. In this case, TH2 = 6. When the total number of effective coefficients and zero runs reaches 6, the effective coefficients thereafter are replaced with 0. In the example of FIG. 12B, the effective coefficient "5" and later are truncated.

FIG. 13 is a diagram showing an operation of the code controller 24 shown in FIG. When the effective coefficient "5" is input to the ROM 131, the counter 13
Outputs a pulse signal that instructs 2 to count up.
Next, "0" is input to the ROM 131. Since this "0" is at the beginning of the zero run, the ROM 131 outputs a pulse signal to the counter 132. In this way, the counter 132 counts up by +1 each time the effective coefficient or "0" at the beginning of the zero run is input. When the count value of the counter 132 exceeds the threshold TH2, the comparator 133 outputs a select signal to the selector 136. When receiving this select signal, the selector 136 outputs "0" until the subsequent block synchronization signal is output.

FIG. 15 is a block diagram showing the configuration of the variable length encoder 25 when the run length code is used. Variable length encoder
25 has a coefficient processor 141, an encoding table 142 and a rotator 143. The coefficient processor 141 includes a delay device 141, a ROM 145, a counter 146,
It has a delay device 148, a selector 149, a memory 150 and a delay device 151.

ROM145 is block sync signal, code control output and delay device
Input the code control output of the previous coefficient output from 144,
It works as follows. Counter 1 when block sync signal is low (EOB signal) and sign control output is not "0"
Clear 46. When the output of the delay device 144 is other than "0", the output of the delay device 144 is "0", and the code control output is "0".
In other cases, and when the block synchronization signal is low, the memory 150 is instructed to write, and the select signal is output to the selector 149. FIG. 16 is a diagram showing the operation of the ROM 145.

The counter 146 counts up after the clear signal is applied until the next clear signal is applied. Delay device 14
The outputs of 4 and 148 are provided to selector 149, respectively. The count value of the counter 146 indicates the number of “0” in zero run.
In order to distinguish the value indicating the number of “0” s in this zero run from the significant figures, the delay device 148 is provided to the selector 149 together with “0”, and the output of the delay device 144 together with “1” is also to the selector 149. Given to. When there is no select signal (low “0”), the selector 149 selects the output (the number of zeros) of the delay device 148 together with “0”, and the select signal is output (high “1”).
At this time, the output (effective coefficient) of the delay device 144 is selected together with "1". The delay device 151 delays the block synchronization signal and the write instruction signal to synchronize the processing. The memory 150 functions as a buffer, and writes the block synchronization signal from the delay unit 151 and the output of the selector 149 in synchronization with the write instruction signal from the delay unit 151.

The coding table 142 has the coding tables shown in FIGS. 18A and 18B, respectively. Regarding the run length, FIG. 18A outputs the code length and the code word by using the block synchronization signal and the output of the selector 149 as an address. The output of the selector 149 in this case is the output of the delay 148 selected together with the data "0" for identification. In FIG. 18B, regarding the effective coefficient, the code length and the code word are output using the block synchronization signal and the output of the selector 149 as an address. In this case, selector 14
The output of 9 is the output of the delay 144 selected with the data "1" for identification. The rotator 143 is the rotator 11 described above.
It has the same configuration as in FIG. 3 (FIG. 10) and shifts the code length based on the code word to generate a variable length coded output, and also generates a write control signal from the code length.

FIG. 17 is a timing chart showing the operation of the variable length encoder 25 shown in FIG. FIGS. 17A and 17B show the block synchronization signal and the write instruction signal after being delayed by the delay device 151, respectively. At the time when the code control output “5” is input to the ROM 145, the last coefficient (* in the figure) of the previous one block is written in the memory 141 together with the identification data “1”. The code control output "5" is delayed by the delayer 144 for one processing time and is given to the selector 149 together with the identification data "1". At this time, "0" following the effective coefficient "5" is input to the ROM 145, and the count value of the counter 146 becomes "1". At this time point, the low-active write instruction signal is given from the delay unit 151 to the memory 150, so that the memory 150 writes the output of the selector 149. At this time, the select signal is high,
The code control output “5” from the delay unit 144 is written in the memory 150 together with the identification data “1”.

Hereinafter, "0" is continuously input to the ROM 145, and the counter 146 increments by 1 each time. After 10 consecutive "0" s, the code control output "7" is input to the ROM 145. At this time,
The write instruction signal from the delay device 151 is active (low)
become. The output of delay device 148 at this point is 10, and the select signal is low. Therefore, the delay unit 1 selected with the identification data “0” by the selector 149 is stored in the memory 150.
Output 48 “10” is written. This "10" is the number of consecutive "0" s between the effective coefficients "5" and "7". At the next timing, the write instruction signal is active and the select signal changes from low to high. Therefore, the selector 149
Selects the output of the delay unit 144, that is, the effective coefficient “7” together with the identification data 10 and writes it in the memory 150.

As described above, by providing the code controller 24, the variable length encoder 25 may have any configuration capable of generating a predetermined number of variable length codewords. This advantage of the present invention will be explained with reference to Figures 19A and 19B.

FIG. 19A is a block diagram showing a configuration of a conventional image encoder for transmitting image data of HDTV (High Definition Television). Now, consider the case where the analog video signal is digitized at 64 MHz. It is difficult in terms of processing speed to obtain a variable length coded output by directly encoding a 64 MHz digital signal. Therefore, in the configuration shown in the figure, after the analog video signal is converted into a 64 MHz digital signal by the A / D converter 42, it is separated into four 16 MHz digital signals by the demultiplexer for parallel processing. Therefore, the image coding control system (transmitter) has four source encoders 43.
a to 43d, a variable length encoder 44 having four systems and four buffer memories 45a to 45d. Each buffer memory
The output from 45 is converted into a transmission line speed by the transmission line interface 46. Each of the source encoders 43a to 43d corresponds to the orthogonal transform encoder 1 of FIG. The variable length encoder 44 includes four coefficient processors 47a to 47d and four encoding tables 48a to 48d.
And four rotators 49a-49d. As shown
In the conventional video encoding system, the source encoders 43a to 43a-4
The 3d and variable length encoder 44 must be configured to handle 16 MHz digital signals. Therefore, the scale of hardware increases.

On the other hand, according to the present invention, if the variable length code word 16 is controlled for the 8 × 8 block, it can be configured as shown in FIG. 19B. The image coding control system shown in FIG. 19B has four source encoders 50a to 50d, four code controllers 51a to 51d and a variable length encoder 52. Each source encoder 50a-5
0d corresponds to the orthogonal transform encoder 10 in FIG. 2, and is composed of the respective code controllers 51a to 51d, one selector 55, one encoding table 56, and one rotator 57. Note that the configuration of FIG. 19B needs to be able to process the variable-length codeword 16 for an 8 × 8 block, so the output is 4 MHz (= 16 MHz ÷ (64 /
16)) digital signal. The selector 55 sequentially selects the coefficient processors 54a to 54d and outputs the selected output to the encoding table 56. As a result, one encoding table 56,1
Only one rotator 57 and one buffer memory 53 are needed, and the hardware can be downsized.

Further, according to the present invention, since the processing speed becomes low, there is an advantage that a common circuit can be used on the transmitting side and the receiving side in a time division manner. This will be described with reference to FIGS. 20A and 20B.

FIG. 20A is a block diagram of a conventional transmission / reception system. The transmitting side is provided with four systems as shown in FIG. 19A, but for simplification, only one system is shown and each block is shown by reference numbers without suffixes a to d. The receiving side (decoding side) also has four systems, but only one system is shown.
The receiving side system has one transmission line interface 61, four buffer memories 62 (only one is shown), variable length encoder 6
It has three and four source decoders 64 (only one shown) and a D / A converter 65. The variable length encoder 63 has four rotators 66 (1
(Only one shown), 4 decryption cables 67 (only one shown)
And four coefficient processors 68 (only one shown).

FIG. 20B is a block diagram of a transmission / reception system according to the present invention. The components having four systems shown in FIG. 19B show only one system and are indicated by reference numerals without suffixes a to d. Further, the selector 55 of the variable length encoder 52 is omitted. Only one system is shown among the four system components on the receiving side (decoding side). The receiving side system has a transmission line interface 61, one buffer memory 71, a modulatable decoder 73, four source decoders 74 (only one is shown) and a D / A converter 65. The variable length encoder 73 has one decoding table 77.
And four coefficient processors 78 (only one is shown).

A variable length coding / decoding common block (hereinafter, simply referred to as a common block) 72 is provided commonly to the transmitter and the receiver. The common block 72 has a selector 75 and a rotator 76. The transmitter and the receiver use the common block 72 in a time division manner. The output of the encoding table 56 of the transmitter is given to the rotator 76 via the selector 75, and the output of the rotator 76 is the selector.
It is given to the buffer memory 53 of the transmitter via 75. The output of the buffer memory 71 of the receiver is given to the rotator 76 via the selector 75, and the output of the rotator 76 is given to the decoding table 77 via the selector 75. Thus, the rotator
Since 76 can be used in both transmitter and receiver,
The scale of the entire transmission / reception system can be reduced.

FIG. 21 is a block diagram of an image coding control system according to the third embodiment of the present invention. In Figure 21, the third
The same components as those in the figure are designated by the same reference numerals.
The configuration shown in FIG. 21 is obtained by adding a selector 80 to the configuration shown in FIG. The selector 80 is the comparator 103 (fourth comparator) of the code controller 24.
Frame memory according to the select signal
Either the output of 29 or “0” is output to the adder 28.
When the select signal is not output, the selector 80 selects the output of the frame memory 29. When the select signal is output, the selector 80 selects “0”.

FIG. 22A is a diagram showing the operation of the configuration shown in FIG. 3, and FIG. 22B is a diagram showing the operation of the configuration shown in FIG. The dot area of the X block shown in FIG. 22A (a) shows a range in which the conversion coefficient (effective coefficient and “0”) is not truncated. That is, all the transform coefficients of this X block pass through the code controller 24 (FIG. 3) as they are. In the subsequent X + 1 block, only the transform coefficients in the area A1 pass through the code controller 24, and the remaining transform coefficients are truncated. In the next X + 2 block, only the transform coefficient in the area A2 passes through the code controller 24 and the remaining coefficients are truncated.

The contents of the X block are output to the subtractor 22 via the frame memory 29 of FIG. 3, and the difference from the contents of the X + 1 block is calculated. Therefore, the transform coefficient of the X block appears in the area other than the area A1 of the X + 1 block. Similarly, X +
The 2-block area A2 is partially affected by the X-block conversion coefficient, and the X-block conversion coefficient also appears in areas other than the area A2. As a result, reproduced image quality may be deteriorated. That is, if the threshold value TH1 or TH2 of the code controller 24 is set to a small value, the high frequency component of the previous frame may remain in the subsequent frames.
The selector 80 shown in FIG. 21 is provided to solve this problem.

As shown in FIG. 22B (b), the area A of the X + 1 block
When 1 is processed, the select signal is given from the code controller 24 to the selector 80. As a result, the area of X + 1 block
In addition to A1, "0" is written instead of the transform coefficient of the X block. Similarly, "0" is written in the area A2 of the X + 2 block. As a result, the high frequency component of the preceding block does not remain in the succeeding block.

FIG. 23 is a block diagram of an image coding control system according to the fourth embodiment of the present invention. 23, the same components as those of FIG. 3 are designated by the same reference numerals. The embodiment of FIG. 23 has a configuration of predictive coding including orthogonal transformation, and the input image signal and the content of the corresponding previous frame are subtracted by the subtractor 22 to obtain the interframe difference. , The discrete cosine transformer 21 is subjected to orthogonal transform coding for each processing block, the quantizer 23 quantizes the transform coefficient and added to the code control block 24, and the variable length code not shown in the figure by the code controller 24. The number of signals for each processing block added to the rectifier is controlled to be a certain number or less.

Further, in this embodiment, in order to form a loop including orthogonal transformation, an inverse discrete cosine transformer 11A that adds the output signal of the inverse quantizer 27 is provided, and based on the orthogonal transform code by the discrete cosine transformer 21. It is configured such that it is returned and added to the adder 28.

The present invention is not limited to each of the above-mentioned embodiments, the orthogonal transform encoder 21 can be configured only by various orthogonal transform means such as Fourier transform and Hadamard transform, and It is also possible to adopt a configuration in combination with various predictive coding means such as inter-field coding. Further, the thresholds TH1 and TH2 described above can be selected according to the size of the processing block, the type of the orthogonal transformation means, and the like.

[Industrial applications]

INDUSTRIAL APPLICABILITY The present invention can be applied to the transmission of a large amount of image data such as HDTV and the transmission of image data such as video conference and video telephone.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A 63-246976 (JP, A) JP-A 63-132530 (JP, A) JP-A 1-14273 (JP, A)

Claims (27)

(57) [Claims] 1. An orthogonal transform coding means for performing orthogonal exchange coding for each block obtained by dividing one screen of an input image signal into a plurality of blocks, each block having transform coefficients for a plurality of pixels; Code control means for controlling the output of transform coefficients until the number of effective coefficients among the transform coefficients output from the orthogonal transform coding means reaches a predetermined number so that the obtained variable-length codeword becomes a predetermined number or less. A variable-length coding means for converting the transform coefficient output from the code control means into a variable-length coded output for each block; and a variable-length coded output for each block output from the variable-length coding means Image coding control system having buffer memory means for storing. 2. The image coding control system according to claim 1, wherein the predetermined number of the variable-length codewords is smaller than the number of transform coefficients regarding pixels included in each block. 3. The variable-length code word is a two-dimensional variable-length code; the code control means: counting means for counting the number of effective coefficients of the transform coefficients for each block; and counting by the counting means. Comparing means for comparing the number of effective coefficients with a predetermined threshold value; and a number of effective coefficients provided between the orthogonal transform encoding means and the variable length encoding means and less than the predetermined threshold value. , The transform coefficient from the orthogonal transform coding means is selected, and when the number of effective coefficients exceeds a predetermined threshold value, “0” is selected.
The image coding control system according to claim 1, further comprising a selection unit for selecting. 4. The image code control system according to claim 3, wherein the predetermined threshold value is equal to the predetermined number of the variable length coded words. 5. The variable-length coding means includes: counting means for counting, for each block, the number of consecutive "0" s of the transform coefficients output from the code control means; and the counting means. The image coding control system according to claim 3, further comprising: a conversion unit that generates the variable-length coded word from the number of "0" s and the effective coefficient output from the code control unit. 6. The conversion means: a memory means for recording a code word and its code length corresponding to a combination of the number of consecutive "0" s and the effective coefficient as an address; and an output from the memory means. The image coding control system according to claim 5, further comprising: rotator means for generating the variable length coded output from the coded code and the code length. 7. The variable-length codeword is a run-length code; the code control means: For each block, the total number of strings of "0" that is continuous with the number of effective coefficients of the transform coefficients. Counting means for counting the total number counted by the counting means; comparison means for comparing the total number counted by the counting means with a predetermined threshold value; and totalizing means provided between the orthogonal transform coding transform means and the variable length coding means. Selecting means for selecting the transform coefficient from the orthogonal transform coding converting means when the number is less than or equal to the predetermined threshold value, and selecting "0" when the total number exceeds the predetermined threshold value; The image coding control system according to claim 1, further comprising: 8. The image coding control system according to claim 7, wherein the predetermined threshold value is equal to the predetermined number of the variable length coded outputs. 9. The variable-length coding means includes: counting means for counting, for each block, the number of consecutive "0" s out of the transform coefficients output from the code control means; "0" counted by the counting means. Selecting means for selecting, for each pixel, one of the number of "and the effective coefficient output from the code control means; and the variable length code from the number of" 0 "or the effective coefficient selected for each pixel from the selecting means The image coding control system according to claim 7, further comprising: a conversion unit that generates a coded output. 10. The conversion means includes: a first table storing codewords corresponding to the number of “0” and code lengths thereof, and a second table storing codewords corresponding to the effective coefficient and code lengths thereof. 10. The image coding control system according to claim 9, further comprising: a memory unit having a table of 1 .; and a rotator unit for generating the variable length coded output from the code word and the code length output from the memory unit. 11. The transform coefficient is a residual signal of an input image signal between blocks of two consecutive frames; the image coding control system further quantizes the residual signal to correspond to the transform coefficient. 2. The image coding control system according to claim 1, further comprising a quantizing means for generating a quantized output for 12. The image coding control system further includes: an inverse quantizing means for inversely quantizing the transform coefficient from the code controlling means for each block to generate an inverse quantized output; Frame memory means for storing the dequantized output in the block of the frame immediately preceding the current block; an addition for adding the dequantized output in the current block and the dequantized output in the block of the previous frame Means for calculating the difference between the input image signal for the current block and the dequantized output for the block of the previous frame from the frame memory means, and subtracting means for outputting the residual signal. The image coding control system described. 13. The image coding control system further comprises a selection means for selecting the dequantized output from the frame memory means and “0” and outputting either one to the addition means. The image coding control system described. 14. The variable length code word is a two-dimensional variable length code; the code control means: counting means for counting the number of effective coefficients of the transform coefficients for each block; and counting by the counting means. Comparing means for comparing the number of effective coefficients with a predetermined threshold; and the orthogonal transform coding means and the transform coefficient from the orthogonal transform coding means when the number of effective coefficients is less than the predetermined threshold. And a selector for selecting "0" when the number of effective coefficients exceeds a predetermined threshold value; the selecting means has "0" when the selector selects "0".
13. The image coding control system according to claim 12, wherein when the selector selects the transform coefficient from the orthogonal transform coding means, the dequantized output from the frame memory means is selected. 15. The variable-length codeword is a run-length code; the code control means is: for each block, the total number of strings of "0" consecutive to the number of effective coefficients of the transform coefficients. Counting means for counting; a comparing means for comparing the combined number counted by the counting means with a predetermined threshold value; and a total number provided between the orthogonal transform coding transform means and the variable length coding means. Selecting means for selecting the dequantized output from the frame memory means when the number is less than or equal to the predetermined threshold value, and selecting "0" when the total number exceeds the predetermined threshold value; 13. The image encoding control system according to claim 12. 16. The image coding control system according to claim 1, wherein each block has n × n pixels (n is an arbitrary integer). 17. The image coding control system comprises: subtraction means for obtaining the residual signal by obtaining a difference between a current input image signal and an input image signal of a block of a frame immediately before, and the residual signal. Is given to the orthogonal transform coding means; Quantizing means for quantizing the orthogonal transform coded residual signal output from the orthogonal transform coding means to generate a quantized output corresponding to the transform coefficient. Dequantizing means for dequantizing the transform coefficient from the orthogonal transform coding means for each block to generate an inverse quantized output; inverse orthogonal transform coding means for inverse orthogonal transforming the dequantized output; Addition means for adding the inverse orthogonal transform coded output in the block and the inverse orthogonal transform coded output in the block of the preceding frame; frame memory means for storing the added output; The image coding control system according to claim 1, wherein a frame memory output output from the means is output to the subtraction means. 18. An analog-to-digital conversion means for converting an analog image signal into a digital image signal; a dividing means for dividing the digital image signal into l (l is an arbitrary integer) input image signal by time division The frequency of the l input image signals is lower than the frequency of the digital image signals; an orthogonal transform code is provided for each block provided for each l input signals and obtained by dividing one screen of the corresponding input image signal into a plurality of blocks. Orthogonal transform coding means for performing coding, each block having transform coefficients relating to a plurality of pixels; a predetermined number of variable-length codewords provided for each of the orthogonal transform coding means and obtained for each block. Control is performed so that the transform coefficients are output until the number of effective coefficients among the transform coefficients output from the corresponding orthogonal transform coding means reaches a predetermined number as follows. l code control means; a coefficient processing means which is provided for each of the l code control means, and which generates, for each block, data defining the variable-length coded output from the transform coefficients output from the corresponding code controller; Selecting means for time-divisionally selecting the data generated by the l coefficient processing means and outputting a data string; converting means for generating the variable length coded output from each data in the data string; and the converting Image coding control system having buffer memory means for temporarily accumulating variable length coded output for each block outputted from the means. 19. The image coding control system according to claim 18, wherein the data defining the variable-length coded output includes the number of “0” consecutive with the effective coefficient of the transform coefficients. 20. The variable-length code word is a two-dimensional variable-length code; the code control means: counting means for counting the number of effective coefficients of the transform coefficients for each block; and counting by the counting means. Comparing means for comparing the number of effective coefficients with a predetermined threshold value; and, when the number of effective coefficients is less than or equal to the predetermined threshold value, provided between the orthogonal coding varying means and the code control means. Selects the transform coefficient from the orthogonal coding transform means,
19. The image coding control system according to claim 18, further comprising selection means for selecting "0" when the number of effective coefficients exceeds a predetermined threshold value. 21. The variable-length coded output is a run-length code; the code control means: blocks the total number of strings of "0" that are consecutive with the number of effective coefficients of the transform coefficients. Counting means for counting each number; comparison means for comparing the total number counted by the counting means with a predetermined threshold value; and a total number provided between the orthogonal transform coding means and the code control means. When the predetermined threshold value or less, select the transform coefficient from the orthogonal coding transform coding means,
“0” when the total number exceeds the predetermined threshold
19. The image coding control system according to claim 18, further comprising: selecting means for selecting. 22. The image coding control system according to claim 20, wherein the predetermined threshold value is equal to the predetermined number of the variable length coded outputs. 23. The image coding control system according to claim 21, wherein the predetermined threshold value is equal to the predetermined number of the variable length coded outputs. 24. The converting means: a memory means for storing a code word and its code length corresponding to a combination of the number of consecutive “0” s and the effective coefficient as an address; and an output from the memory means. 19. The image coding control system according to claim 18, further comprising: rotator means for generating the variable length coded output from the coded code word and the code length. 25. A first table storing the code length corresponding to the number of “0” and the code length corresponding to the effective coefficient and storing the code length corresponding to the effective coefficient. 20. The image coding control system according to claim 19, further comprising: memory means having two tables; and rotator means for generating the variable length coded output from a codeword and a code length output from the memory means. 26. The image coding control system according to claim 24, wherein the rotator means is shared with a decoding side. 27. The image coding control system according to claim 24, wherein said rotator means is shared with a decoding side.