JPH0686255A - Picture encoder - Google Patents

Abstract

PURPOSE:To control data so that constant data generating amounts can be attained within a short unit period by quantizing the data by plural quantizers preliminarily decided by prediction, variable length-encoding the data, and then selecting and outputting the data according to the activity of each block. CONSTITUTION:Digital video data inputted from an input terminal 11 are divided into small blocks by a blocking circuit 1, and an orthogonal transformer 2 outputs transformation coefficients by a DCT to a non-zero coefficient counting circuit 3, a standard deviation calculating circuit 4, and a delay circuit 5. The circuit 3 counts and stores the number of coefficients being non-zero at the time of quantizing the data by preliminarily decoded plural quantization steps for each quantization step. The circuit 4 calculates standard deviation for each block. The outputs of the circuits 3 and 4 are inputted to a calculating circuit 6, the activity is calculated, inputted to a selecting circuit 7, and a quantizer 8 by which the target data generating amounts can be established is selected. The output of the transformer 2 is quantized through the delay circuit 5 by the quantizer 8, replaced with a variable length code by an encoder 9, transmitted through a buffer circuit 10, and outputted from a terminal 12 as a code to be transmitted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal coding apparatus which digitizes a video signal and records and transmits it at a constant transmission rate.

[0002]

2. Description of the Related Art FIG. 5 shows, for example, IEEE Transaction on Cons.
umer Electronics, Vol.34, No.3, Aug.1988, ■ An Exp
erimental Digital VCR with 40mm Drum, Single Actua
tor and DCT-Based Bit-Rate Reduction ■, SMCBorg
ers, et.al. is a block circuit diagram of the image signal encoding device, in which 31 and 32 are frame memories for temporarily storing an input video signal, and 33 is D for performing discrete cosine transform.
The CT device, 34 rearranges the output of the DCT device 33 in a predetermined order, and performs a block scanning / weighting process for multiplying a constant coefficient according to the position of the output of the DCT device 33 (waiting process). A processing block, 35 is an adaptive quantizer, 36 is a sorting circuit for changing the order of the coefficients according to the amplitude value of each quantized coefficient and obtaining an address indicating the order, 37 is a variable length output of the sorting circuit 36. A variable-length encoder that replaces the code, 38 is a buffer circuit that stores the variable-length code and outputs it at a constant rate, and 39 is a buffer control circuit that monitors the state of the buffer circuit 38 and determines quantization parameters and the like.

Next, the operation of FIG. 5 will be described. The input video signals (luminance signal Y and color signals U and V) are temporarily stored in the frame memories 31 and 32, and then, as a data block that does not overlap each other in units of 8 pixels in the vertical direction and 8 pixels in the horizontal direction, the frame memory 31, Read from 32. The DCT device 33 performs a two-dimensional discrete cosine transform on the data read from the frame memories 31 and 32 in the form of 8 × 8 blocks. The coefficient data obtained by the discrete cosine transform is rearranged in the order shown in FIG. 6 and weighted by the position in the block.

The output of the block scanning / weighting processing block 34 is quantized by an adaptive quantizer 35. The adaptive quantizer 35 includes a so-called threshold process in which all coefficient data below a certain value is zero data. The quantization step size and the threshold value used at the time of quantization are determined by using both the property of each block and the output of the buffer control circuit 39. For example, a block that includes abrupt level changes is considered to be visually less noticeable than a block that includes a high-definition signal with a small amplitude, so a block with abrupt level changes has a larger step size and threshold value. Quantize with.

The quantization step size and the threshold value are also controlled by a control signal supplied from the buffer control circuit 39 according to the state of the buffer circuit 38. That is, when the amount of data stored in the buffer circuit 38 increases, the quantization step size and the threshold value are increased, and conversely, when the amount of data is smaller than a predetermined value, the quantization step size and the threshold value are increased. To reduce. Under such control, the buffer circuit is prevented from overflowing. The output of the adaptive quantizer 35 is processed after rearranging the coefficients of the non-zero amplitude value in the order of amplitude so that the code amount generated in the sorting circuit 36 can be reduced.

The output of the sorting circuit 36 is converted by the variable length encoder 37 into a variable length code reflecting the statistical properties of the data, and written in the buffer circuit 38. The state of the buffer circuit 38 is constantly monitored by the buffer control circuit 39, and as described above, the quantization parameter is changed according to the filling degree of the buffer circuit 38. That is, when the filling degree of the buffer circuit 38 becomes high,
By setting both the quantization step size and the threshold value large, the amount of generated data is reduced, and conversely, when the filling degree of the buffer circuit 38 becomes low, both the quantization step size and the threshold value are reduced.

[0007]

As described above, in the video signal coding apparatus adopting so-called feedback control, in which the quantization parameter is changed according to the state of the buffer storing the variable length code, the amount of generated data is increased. It is difficult to set V to a constant value within a short time of less than a frame unit.
When it is required to efficiently suppress the amount of generated data to a fixed value or less in a frame unit such as TR or the like,
There was a problem that it was not always appropriate.

The present invention has been made in order to solve the above problems, and video signal encoding capable of controlling the data generation amount to a predetermined value even in a unit of a short period of one frame or less. The purpose is to provide a device.

[0009]

According to a first aspect of the present invention, there is provided a video signal encoding apparatus, which orthogonally transforms blocks obtained by dividing input video signals so that they do not overlap each other, and performs a plurality of predetermined quantization. Counts the number of coefficients that become non-zero for each block when quantized in steps, calculates the standard deviation of the data in each block, and calculates the linear sum of the number of non-zero coefficients in each block and the standard deviation. Then, the coded data amount is predicted based on the activity parameter, and the quantization step is selected according to the prediction result.

According to a second aspect of the present invention, there is provided a video signal encoding device, wherein a plurality of quantizers selected based on the activity calculated by the activity calculating means of the first aspect are provided, and each quantizer is provided. And a data selection means for selecting any of the data stored in a plurality of buffers for each block.

The video signal encoding apparatus according to the third aspect of the present invention, when configuring the data selecting means of the second aspect of the present invention, selects the data in the buffer having a smaller code amount in order from the block having a large activity. It is the one.

[0012]

According to the video signal encoding device of the present invention, the number of coefficients that become non-zero after quantization for each block, the activity parameter obtained as the sum of standard deviations, and the encoded data amount Shows a high correlation, so that a good encoded data amount prediction can be performed, an appropriate quantization step can be selected, and it is possible to control so that the generated data amount is constant within a short period. It will be possible.

Further, according to the second aspect of the present invention, since the outputs of different data amounts can be obtained for each of the plurality of quantizers, the data selecting means selects from the plurality of quantized data for each block. Then, the total code amount of a plurality of blocks can be brought closer to the target code amount.

Further, according to the invention of claim 3, when selecting a plurality of encoded data, the block to be selected is determined according to the activity of each block.
The property of the image of each block is taken into consideration, and the improvement of the reproduced image quality can be expected.

[0015]

EXAMPLES Example 1. Embodiment 1 of the present invention will be described below with reference to FIG.
Will be described. In FIG. 1, 1 is a blocking circuit, 2 is an orthogonal transformer, 3 is a non-zero coefficient counting circuit, 4 is a standard deviation calculation circuit, 5 is a delay circuit, 6 is an activity calculation circuit, 7 is a quantizer selection circuit, Reference numeral 8 is a quantizer, 9 is a variable length encoder, 10 is a buffer circuit, 11 is a video signal input terminal, and 12 is a code output terminal.

Next, the operation will be described. Video input terminal 1
The digital video input data input from 1 is divided into small blocks which do not overlap each other in the blocking circuit 1. The size of this small block is, for example, 8 pixels both in the vertical and horizontal directions. The block formed by the blocking circuit 1 is input to the orthogonal transformer 2. Orthogonal transformer 2
Then, orthogonal transform such as discrete cosine transform is performed for each block to obtain the transformed coefficient. Each transform coefficient output from the orthogonal transformer 2 is supplied to the non-zero coefficient counting circuit 3, the standard deviation calculating circuit 4, and the delay circuit 5.

In the non-zero coefficient counting circuit 3, the number of coefficients that become non-zero when quantized by a plurality of predetermined quantization steps is counted and stored for each quantization step. Further, the standard deviation calculation circuit 4 calculates the standard deviation of data for each block. The outputs of the non-zero coefficient counting circuit 3 and the standard deviation calculating circuit 4 are both given to the activity calculating circuit 6. In the activity calculation circuit 6, a predetermined constant is set to the count value N of the non-zero coefficient.
The sum of the value obtained by multiplying a and the standard deviation S by another predetermined constant b is calculated, and is defined as the activity act.
That is, the activity act is calculated by act = aN + bS. It has been confirmed by simulation that the activity calculated in this way has a high correlation with the amount of encoded data. Therefore, if you check the relationship between the activity value and the amount of generated data after encoding for each quantization step using multiple image data,
The amount of generated data can be predicted with high accuracy from the activity of each block of the input image. Therefore, the activity calculated by the activity calculating circuit 6 is given to the quantizer selecting circuit 7 and is used for selecting the quantizer that can achieve the target data generation amount.

Since the prediction of the generated data amount is performed for each block, the generated data amount can be controlled in a short unit of one frame or less, and can be set in a short unit of, for example, several blocks. is there. For example, when trying to make the encoded data amount constant in units of 100 blocks, the activity of each block is obtained for all 100 quantization blocks set in advance, and the data generation amount for each quantization step is calculated. From among the combinations of quantization steps that result in a predetermined data amount or less, the one that maximizes the data generation amount is selected.

The output of the orthogonal transformer 2 is supplied to the non-zero coefficient counting circuit 3 and the standard deviation calculating circuit 4 for predicting the generated data amount as described above, and is also input to the delay circuit 5. The delay circuit 5 compensates for the time delay until the quantization step is determined after predicting the generated data amount in the above process, and is input to the quantizer 8 for the time until the quantization step is determined. Delay the data. In the above example of performing control in 100 block units, at least 1
A delay of 00 blocks is required. The output of the delay circuit 5 is quantized by the quantizer 8 selected by the quantizer selection circuit 7, and then replaced by a variable-length code by the variable-length encoder 9. The output of the variable-length encoder 9 is temporarily stored in the buffer 10, then read at a constant rate, and output from the output terminal 12 as a code to be transmitted.

In the first embodiment described above, one input signal has been described. However, for example, when one video signal is composed of a luminance signal and two color signals,
The configuration of FIG. 1 may be applied to each signal, or the luminance signal and the chrominance signal may be multiplexed on the time axis and used as the input signal of the configuration of FIG.

When the above configuration is applied to, for example, a digital VTR, after data such as an error correction code is added to the data output from the video signal output terminal in FIG.
Magnetically recorded on tape. FIG. 2 shows a block circuit diagram of the entire signal processing of the digital VTR. In FIG. 2, 4
1 is an A / D converter for converting an input video signal (luminance signal Y and chrominance signals U, V) into a digital signal, 42 is a high efficiency coding encoder, 43 is an error correction encoder, 44 is a modulator, and 45 is a signal Is a magnetic recording / reproducing system for recording and reproducing data on a magnetic tape, 46 is a demodulator, 47 is a time axis correction device for removing time axis fluctuation components contained in the demodulated signal, 48 is an error correction decoder, and 49 is A high-efficiency coding decoder, 50 is a D / A converter for converting a digital signal into an analog reproduction signal.

The video signal coding apparatus according to the first embodiment shown in FIG. 1 corresponds to the high efficiency coding encoder 42 shown in FIG. The output of the high-efficiency encoding encoder 42 is, after the error correction code is added in the error correction encoder 43,
It is converted into a bit stream of the recording signal by the modulator 44,
Recorded on magnetic tape. In a digital VTR, a signal for one screen (one frame) is generally recorded on a plurality of tracks as shown in FIG. A given amount of data will be recorded on one track,
If the video signal coding apparatus of the first embodiment is used, control is performed so that the code amount is constant in units of one frame or less, and, for example, the area of the video recorded on one track is fixed.

In the digital VTR, a special reproduction mode such as speed search is introduced. For example, in the forward speed search (forward direction high speed reproduction), the locus of the head that scans the tape is different from that in the normal reproduction, and becomes the locus shown by the broken line in FIG. At this time, each time the head crosses a track, discrete data is read from each track. The read data is used as part of the reproduced video signal according to the correspondence with the position on the screen. The positional relationship between the read data and the screen is generally specified by the positional relationship between the head and the tape. According to the encoding device of the present invention, the signal recorded on each track and the position on the screen are compared. Since the correspondence becomes clear, it is possible to determine at which position on the screen the read signal is to be inserted. Furthermore, if the code amount is controlled in units of one track or less, the positional relationship between the read signal and the screen can be specified more clearly. As described above, in order to facilitate special reproduction, it is desired to keep the generated code amount constant at short time intervals.

Example 2. FIG. 4 is a block circuit diagram of a second embodiment of the present invention, in which the same reference numerals as those in FIG. 1 denote the same or corresponding portions, and 13 denotes a first quantizer, 1
4 is a second quantizer, 15 is a first variable length encoder, 16
Is a second variable length encoder, 17 is a first buffer circuit, 1
8 is the second buffer circuit, 19 is the first buffer circuit 1
7 and the second buffer circuit 18, a data selection circuit for selecting one of the outputs, 20 is the first and second buffer circuits 1
Monitor the amount of data for each block stored in 7, 18,
The block selection signal generation circuit generates a signal for selecting the output of the first buffer circuit 17 or the second buffer circuit 18 by the data selection circuit 19 for each block.
In FIG. 4, the first quantizer 13 and the second quantizer 1
4 and the first variable length coder 15, the second variable length coder 16, and the first buffer circuit 17 and the second buffer circuit 18 are equivalent devices.

Next, the operation of the second embodiment will be described. The input video signal is divided into blocks as in the first embodiment shown in FIG.
Orthogonal transformation is performed and the activity is calculated from the number of non-zero coefficients and standard deviation for each block. At this time, the quantizer selection circuit 7 determines the first quantization step which becomes the minimum value of the data exceeding the target data generation amount from the activity, and the first quantization step is performed so as to perform the quantization at the quantization step. While sending the signal to the quantizer 13,
The second quantizing step that has the maximum value of the data amount that is less than the target data generation amount is obtained, and a signal is sent to the second quantizer 14 so as to perform the quantization in the second quantizing step. Here, it is assumed that the same quantization step is used for a unit for performing data amount control, for example, 100 consecutive blocks in the above example.

The output of the first quantizer 13 is variable-length coded by the first variable-length encoder 15 and then stored in the first buffer circuit 17, and the output of the second quantizer 14 is After being quantized by the second variable length encoder 16, it is stored in the second buffer circuit 18. At this time, unless the prediction largely deviates, the data amount stored in the first buffer circuit 17 exceeds the target data amount, and the second buffer circuit 1
The amount of data stored in 8 should be below the target amount of data. Therefore, in the block selection signal generation circuit 20, the first buffer circuit 17 and the second buffer circuit 18
The amount of data stored in each block is monitored for each block, and the first buffer circuit 17 is provided for each block so that the amount of data is smaller than or equal to the target data amount in units of data control.
Alternatively, a control signal is sent to the data selection circuit 19 to select the data stored in the second buffer circuit 18.
At this time, various methods are conceivable as the selection method, but for example, the following method may be adopted.

First, the total amount of data stored in the first buffer circuit 17 is calculated. This amount of data should generally exceed the target amount of data. Therefore, in the data stored in the first buffer circuit 17, the blocks having the largest activity are sequentially replaced with the data stored in the second buffer circuit 18, and the total data amount becomes smaller than the target data amount. The combination of. The data selection circuit 19 selects the contents of the first buffer circuit 17 and the contents of the second buffer circuit 18 for each block according to this combination, and outputs the selected contents. In this way, since the output data string is formed by selecting the coded data, it is possible to perform control so as to reliably suppress the data to a fixed amount. In addition, since it is considered that deterioration of the screen is less noticeable for blocks with larger activity, it is considered desirable to reduce the amount of data sequentially from blocks with large activity as described above in terms of image quality.

[0028]

As described above, according to the present invention, the standard deviation of the transform coefficient after orthogonal transform for each block and the number of non-zero coefficients generated when quantized by a plurality of predetermined quantizers. Since it is configured to predict the data generation amount based on the activity obtained by linearly combining, and determine the quantization step size, it is possible to control the generated data amount to a constant amount even for a short period of one frame or less. I can.

Furthermore, after quantizing and variable-length coding by a plurality of quantizers determined by prediction, the data is selected and output according to the activity of each block. In addition to good control, the amount of generated data for each block can be assigned in consideration of reproduction image quality.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of an image coding apparatus according to a first embodiment of the present invention.

FIG. 2 is a block circuit diagram showing an example of the configuration of a digital VTR.

FIG. 3 is a diagram showing a track pattern on a tape of a digital VTR.

FIG. 4 is a block circuit diagram of an image coding apparatus according to a second embodiment of the present invention.

FIG. 5 is a block circuit diagram of a conventional image encoding device.

FIG. 6 is a diagram showing a scanning order when scanning data in one block.

[Explanation of symbols]

 1 Blocking circuit 2 Orthogonal transformer 3 Non-zero coefficient counting circuit 4 Standard deviation calculation circuit 6 Activity calculation circuit 7 Quantizer selection circuit 8 Quantizer 9 Variable length encoder 13 Quantizer 14 Quantizer 15 Variable length code 16 Variable-length encoder 19 Data selection circuit 20 Block selection signal generation circuit

Continuation of front page (51) Int.Cl. ⁵ Identification number Office reference number FI Technical indication H04N 7/137 Z

Claims (3)

[Claims] 1. An image coding apparatus which digitizes a video signal to divide one screen into a plurality of blocks which do not overlap each other, performs orthogonal transformation, and then performs coding,
Standard deviation calculating means for calculating the standard deviation of each block,
Non-zero coefficient counting means for counting non-zero coefficients generated in each block when quantized by a plurality of predetermined quantizers, standard deviation obtained by the standard deviation calculating means, and non-zero coefficient counting Activity calculating means for calculating, as an activity, a linear combination with the number of non-zero coefficients per block counted by the means, quantizer selecting means for selecting a quantizer according to the activity, and the quantizer selecting means. An image coding apparatus comprising: a plurality of quantizers selected by the variable quantizer and a variable length encoder that replaces the output of the selected quantizer with a variable length code. 2. The image coding apparatus according to claim 1, wherein a quantizer and a variable length coder for coding the output thereof and a plurality of buffers for storing the outputs of the variable length coder are respectively provided, Block selection signal generating means for deciding which of the plurality of buffers is selected for each block, and data for selecting and outputting the data of the plurality of buffers according to the output signal of the block selection signal generating means An image coding apparatus comprising: a selection unit. 3. The image coding apparatus according to claim 2, further comprising means for controlling the code amount to be equal to or less than a target value by sequentially selecting data in a buffer having a small code amount from a block having a large activity. A characteristic image encoding device.