JP2785209B2 - Data transmission equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to data for compressing a digital image signal by two-dimensional transform coding such as two-dimensional cosine transform (discrete cosine transform). The present invention relates to a transmission device, and more particularly to a data transmission device suitable for use in buffering for controlling a data amount of transmission data to a predetermined value or less.

[Summary of the Invention]

The present invention provides a method of compressing and encoding (n ² -1) AC component coefficient data among n ² coefficient data obtained by orthogonally transforming (n × n) pixels. In the transmission device, the coefficient data of (n ² −1) AC components is divided into low-order coefficient data and high-order coefficient data, and a first bit is assigned to each coefficient data of the low-order coefficient data. Allocates an integer multiple of the number of bits to convert to transmission data,
The higher-order coefficient data is assigned an integer multiple of the second bit number smaller than the first bit number and is converted into transmission data, so that the amount of generated information can be controlled. Further, the amount of transmission data can be efficiently compressed.

[Conventional technology]

In order to suppress the redundancy of an image signal, a transform coding method is known in which a screen is divided into blocks each having a predetermined number of pixels, and a linear transformation is performed for each block using a transformation axis that matches the characteristics of the original image signal. . Transform coding includes Hadamard transform,
Cosine transform and the like are known. A conventional cosine transform coding device has a configuration as shown in FIG. 13, for example.

In FIG. 13, a sampled discrete image signal f (j, k) is supplied to an input terminal indicated by 71.

This input signal is supplied to a cosine transform (DCT transform) circuit 72. In the cosine conversion circuit 72, two-dimensional cosine conversion is performed. In the two-dimensional cosine transform, the following signal processing is performed. However, one block of the original data is (n ×
n) two-dimensional data f (j, k) (j, k = 0,1, ..., n-1)
And

The coefficient value F (u, v) from the cosine transform circuit 72 is supplied to the block scanning circuit 73, and the coefficient data in the block is output by zigzag scanning from the DC component to the high frequency component. The coefficient data from the block scanning circuit 73 is supplied to the requantization circuit 74. In the requantization circuit 74, the coefficient data is quantized in a quantization step from the buffer control circuit 78. The output signal of the requantization circuit 74 is supplied to a sorting circuit 75. In the sorting circuit 75, after the coefficient data is sorted in the order of the absolute value of the amplitude,
Difference values for both amplitude and address are formed. The difference signal from the sorting circuit 75 is supplied to the variable length coding circuit 76. In the variable length coding circuit 76, the signal is converted into a code signal having a predetermined number of bits by run-length coding and Huffman coding.

The code signal from the variable length coding circuit 76 is supplied to the buffer memory 77. The buffer memory 77 is provided for converting the transmission rate of the code signal from the variable length coding circuit 76 into a rate that does not exceed the rate of the transmission path. The data rate on the input side of the buffer memory 77 is variable, but the data rate on the output side of the buffer memory 77 is substantially constant. Output data from the buffer memory 77 is taken out to a terminal 79. In the buffer memory 77, a change in the amount of transmission data is detected, and a detection signal is supplied to the buffer control circuit 78.

The buffer control circuit 78 controls the quantization step of the requantization circuit 74, and controls the coefficient data to be transmitted to have a predetermined data amount by thresholding in the variable length coding circuit 76. Thresholding is a process of subtracting a threshold from coefficient data whose absolute value is larger than the threshold. However, the DC component coefficient data F (0,0) is excluded from the thresholding target.

[Problems to be solved by the invention]

Feedback-type buffering as described above,
When the buffer memory 77 is about to overflow, the rate of input data to the buffer memory 77 is reduced, and conversely, when the buffer memory 77 is about to underflow, the rate of input data to the buffer memory 77 is increased. The quantization step and the threshold value are feedback-controlled by the buffer control circuit 78.
If the sensitivity to the feedback amount is increased too much for feedback control, oscillation will occur near the target value. Conversely, if the sensitivity is decreased too much, it will take time to converge. When it takes time to converge, it is necessary to increase the capacity of the buffer memory 77. As described above, the conventional buffering process has a problem that requires considerable know-how in practical use.

Further, the conventional feedback type buffering device has a drawback that a complicated circuit such as a sorting circuit 75 and a thresholding circuit is required.

Furthermore, in the conventional method, the amount of transmitted data can be suppressed below a predetermined value on average over a long period of time.
One field or one field of the television signal like R
There is a disadvantage that it is difficult to control data accurately on a frame basis.

Therefore, an object of the present invention is to provide a feed-forward type buffering without the need for complicated circuits such as a thresholding circuit and a sorting circuit.
An object of the present invention is to provide a data transmission device capable of setting a data rate to a constant rate in a unit of a field or one frame.

The applicant of the present application has proposed a data transmission device that encodes coefficient data previously obtained by transform coding with ADRC (code adapted to dynamic range DR) and suppresses the data amount of a coded output to a predetermined value or less. (See Japanese Patent Application No. 63-245227). This method can solve the problem of the conventional feedback-type buffering, and can increase the data compression rate. However, since it is necessary to combine an ADRC encoding device, there have been problems of a complicated circuit and an increase in data errors.

The present invention differs from the previously proposed method by controlling the data amount of the coefficient data itself obtained by transform coding.

Further, an object of the present invention is to separate the coefficient data of the AC component into low-order coefficient data and high-order coefficient data, and convert each coefficient data into transmission data based on a different encoding rule, thereby transmitting the transmission data. An object of the present invention is to provide a data transmission device capable of efficiently compressing data.

[Means for solving the problem]

The present invention provides a method of compressing and encoding (n ² -1) AC component coefficient data among n ² coefficient data obtained by orthogonally transforming (n × n) pixels. In the transmission device, the (n ² -1) AC component coefficient data is divided into low-order coefficient data and high-order coefficient data, and a first bit is assigned to each coefficient data of the low-order coefficient data. In addition to assigning an integer multiple of the number of bits to convert to transmission data, the higher order coefficient data is assigned an integer multiple of the second bit number smaller than the first bit number and transmitted. It is converted to data.

[Action]

For example, cosine transform is performed on an (8 × 8) L block, and coefficient data obtained by the cosine transform is (4 × 8).
4) Divided into four blocks. The original value of the coefficient data of the DC component is transmitted without being requantized. In the (4 × 4) block including the DC component coefficient data, the remaining 15 AC component coefficient data, that is, low-order coefficient data, are requantized and requantized. Data (including 0) is converted into transmission data. In this case, the transmission data corresponding to the low-order coefficient data is assigned a first bit number, for example, an integer multiple of 3 bits.

Three blocks that do not include a DC component are called M blocks. The M block is divided into (2 × 2) S blocks, and the S block is divided into sample units. The coefficient data of the AC component of the M block is higher-order coefficient data, and the higher-order coefficient data is requantized, and only non-zero significant data is transmitted. The transmission data corresponding to the higher-order coefficient data is assigned a number of bits that is an integral multiple of 2 bits. In this case, the presence or absence of significant coefficient data is indicated for the M block by the flag Fm for the M block. The flag Fs for the S block in the M blocks containing significant coefficient data
Indicates the presence or absence of significant coefficient data for the S block. Further, the presence or absence of significant coefficient data in the S block including the significant coefficient data is indicated by a flag Fp in sample units.

Therefore, the coefficient data of the AC component is efficiently converted into transmission data, the data amount can be finely controlled in units of M blocks, and buffering can be performed by feedforward control.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. This description is made in accordance with the following items.

a. Entire system of one embodiment b. Buffering process c. Modification a. Entire system of one embodiment In FIG. 1, a sampled discrete image signal is supplied to an input terminal indicated by 1 and input The digital image signal is supplied to the blocking circuit 2. In the blocking circuit 2, the digital image signal in the field is converted from the scanning order to the block order. FIG. 2 shows an example of an image block for DCT (hereinafter, referred to as an L block), which has 8 pixels in the horizontal direction and 8 lines in the vertical direction (8 × 8).
8) A two-dimensional block is formed. When the number of lines is 525 and the number of valid lines in one field is 240, and the number of valid samples in one line is 720, (720 × 240) ÷ (8 × 8) = 2700 L blocks are included in one field. include.

The output signal of this blocking circuit 2 is cosine transformed (DC
T conversion) circuit 3. In the cosine transform circuit 3, two-dimensional cosine transform is performed by a process similar to the conventional one. An (8 × 8) coefficient table corresponding to the size of the L block is obtained from the cosine transform circuit 3. In this coefficient table, the coefficient data of the DC component and the coefficient data of the AC component are data of a predetermined number of bits including a 1-bit sign (±).

The coefficient data from the cosine transform circuit 3 is supplied to the weighting circuit 4. The weighting circuit 4 multiplies the (8 × 8) coefficient table by a fixed weighting coefficient as shown in FIG. This weighting factor is set to 1 for the DC (direct current) component, and the higher the order, the higher the AC (alternating current) component,
The weighting coefficient is small. That is, a coefficient with a higher importance is multiplied by a larger weighting coefficient.

The coefficient data from the weighting circuit 4 is supplied to a buffer memory 5 composed of a one-field memory and an absolute value conversion circuit 6. The coefficient data converted to the absolute value by the absolute value conversion circuit 6 is supplied to the maximum value detection circuit 7, the maximum value detection circuit 8, and the frequency distribution memories 9 and 12, and the output signal of the maximum value detection circuit 7 is supplied to the frequency distribution memory 10 And the output signal of the maximum value detection circuit 8 is supplied to the frequency distribution memory 11. The maximum value detection circuit 7 detects the maximum value MAX1 of the absolute value of the AC coefficient for each sub-block (hereinafter, referred to as an M block) obtained by further dividing the DCT block. The other maximum value detection circuit 8
Is a sub-block obtained by further dividing the M block (hereinafter, S
The maximum value MAX2 of the absolute value of the AC coefficient is detected for each block.

As shown in FIG. 4A, the (8 × 8) L block is divided into four (4 × 4) blocks, and a block other than the block including the DC component coefficient data DC is an M block M1. , M2, and M3, and these M blocks are further divided into S blocks. The original value of the DC component coefficient data DC is transmitted, and the surrounding 15 AC coefficient data are converted into transmission data in units of 3 bits as described later. That is, the 15 low-order AC coefficient data and the high-order coefficient data included in the M block are coded according to different rules.

For the M block, a flag Fm as shown in FIG.
Is determined. One M block Mi (i shown in FIG. 4C
= 1, 2 or 3) is further divided into four (2 × 2) S blocks Si0, Si1, Si2, Si3 as shown in FIG. 4D.
A flag Fs as shown in FIG. 4E is determined for the S block. One S block Sij (ij
= 00 to 03, 10 to 13, 20 to 23 or 30 to 33) include four samples Pij0, Pij1, Pij2, and Pij3, as shown in FIG. 4G. For each sample, the flag Fp shown in FIG.
Is determined. One bit of each of the flags Fm, Fs, and Fp indicates the presence or absence of significant (non-zero) AC coefficient data. That is, a bit of “0” means that there is no significant data, and “1” indicates that there is significant data.

When dividing an L block into M blocks, or dividing an M block into an S block, as shown in FIG. 4, the division is not limited to the method of equally dividing the vertical and horizontal directions, but is performed in the zigzag scanning order. , A smaller block may be formed.

The frequency distribution memories 9, 10, 11 and 12 are provided for buffering processing to be described later. In the frequency distribution memory 9, the coefficient of the block AC including the DC component (lower order)
Is stored, and then this frequency distribution is 1
It is accumulated in the field period and converted into a cumulative frequency distribution table. The frequency distribution memory 10 stores the frequency distribution of the maximum value MAX1 in each M block of the AC coefficient converted into the absolute value,
Next, this frequency distribution is accumulated in one field period, and a cumulative frequency distribution table is formed. Further, the frequency distribution memory 11 stores the maximum value of the AC coefficient converted into the absolute value in the S block.
The frequency distribution of MAX2 is stored, and then this frequency distribution is accumulated in one field period to form a cumulative frequency distribution table.
Further, the frequency distribution memory 12 stores a frequency distribution of higher-order AC coefficients converted into absolute values, and then accumulates the values in one field period to form a cumulative frequency distribution table.

The buffer memory 5 has a memory capacity of one field, which is a unit period of the buffering process, and is supplied with a coefficient data weighting circuit 13 from the buffer memory 5.
The weighting circuit 13 is provided for buffering processing. The weighting circuit 13 multiplies the coefficient data by a controlled weighting coefficient so that the amount of transmission data per field (the number of transmission bits) does not exceed a predetermined target value. Can be The maximum value of the weighting coefficient is 1, for example, 1/2, 1/4, 1/6, 1/8, 1/1.
Weighting factors of 0, 1/12, 1/14, 1/16 are used. As the weighting factor becomes more popular, the amount of data to be transmitted decreases. This weighting factor is the reciprocal of the requantization step. The target of the buffering process is the data of the AC component, and the data of the DC component with high importance is transmitted as the original data.

The control signal generation circuit 14 forms an address for the frequency distribution memories 9, 10, 11 and 12, a mode control signal MD for designating a weighting coefficient for the weighting circuit 13, and the like. The coefficient data and the mode signal from the weighting circuit 13 are supplied to the formatting circuit 15, transmission data is generated from the output terminal 16 of the formatting circuit 15, and the transmission data is transmitted to the transmission path. An example of the transmission path is magnetic recording /
It is a process of reproduction. In the formatting circuit 15, processing such as addition of a synchronization pattern for transmission and error correction encoding is performed as necessary. The process of calculating the number of transmission bits can be performed within the data missing period (vertical blanking period) of the input data, and the data read from the buffer memory 5 in the next field period is determined in the previous field. Weighting processing is performed according to the set mode.

FIG. 5 shows a configuration of transmission data. The transmission data is
First, for example, a 10-bit DC component data CD is located,
Next, the coefficient data DATA1 of the low-order AC component is located, and then the flags Fm, Fs, and Fp are sequentially located, and the coefficient data DATA2 of the high-order AC component is located after these flags. ing. As described above, the flags Fm, Fs, and Fp indicate blocks containing significant data for each of the M block, the S block, and the samples in the S block.

For example, when significant data is included in M1 and M2 in the M block, the 3-bit flag Fm has a bit pattern of (110). Flags Fs relating to (4 × 2 = 8) S blocks S1j and S2j corresponding to the two M blocks M1 and M2 are transmitted. For example, in the S block, S1
When significant data is included in each of 0, S11, S20, and S23, the flag Fs has a bit pattern of (11001001). (4 × 4 = 16) samples P10k, P11k, P20 corresponding to four S blocks containing these significant data
The flag Fp regarding k and P23k is transmitted. Among these samples, for example, P101, P102, P103, P111, P112, P202, P230
Is significant data, the flag Fp is set to (0111011000
101000).

As described above, significant data among (63−15 = 48) AC coefficient data per L block is specified by the flags Fm, Fs, and Fp. These data values are DATA2 converted into transmission data, and are arranged in order after the flag. AC coefficient data obtained by cosine transform is
The data is converted into transmission data in the formatting circuit 15.

FIG. 6 shows a rule for converting low-order AC coefficient data into transmission data, and FIG. 7 shows a rule for converting high-order AC coefficient data into transmission data. As shown in FIG. 6, the low-order AC coefficient data is converted into transmission data having a length of an integral multiple of 3 bits. The bit pattern of the transmission data is the original bit (x0, x1,...) Having a sign bit S at the beginning.
., X8), a combination bit of “0” or “1” is inserted. "0" of the sign bit S means +, and "1" means-. The combination bit “1” means that 3 bits follow, and the combination bit “0” means a break of one sample. As for the low-order AC coefficient data, a sample having a value of 0 is also transmitted. Therefore, the reception data is delimited every three bits, and the delimitation of the sample can be detected from the last bit of the three bits, and the transmission data can be decoded into coefficient data on the reception side. In the transmission data shown in FIG. 6, four types of values can be represented by three bits. That is, (00: 0, 01: 1, 11: -1, 10: reserved word). This reserved word is used to represent the property of the next data.

The high-order AC coefficient data is converted into transmission data as shown in FIG. FIG. 7A shows the values and codes of AC coefficients in coefficient data obtained by DCT. ai represents the (i-1) th bit of the AC coefficient data. This coefficient data is converted into transmission data of the bit pattern shown in FIG. 7B. The bit pattern of the transmission data is such that a combined bit of “0” or “1” is inserted between the original bits having the sign bit S at the head. “1” of the combination bit
Is added before the last bit. Therefore, the end of the bit sequence is (1S) or (1a0), the break of the bit sequence can be detected, and the receiving side can decode the transmission data into coefficient data. Although not shown, (± 128 to ± 2
55) The above values are also converted into transmission data as in FIG.

As described above, the coding rule is changed between the low-order AC coefficient and the high-order AC coefficient for the following reason.

First, low-order AC coefficient data has a considerably larger value than low-order AC coefficient data, and hardly any zero-order AC coefficient data. Therefore, encoding that transmits only significant coefficient data is effective in terms of data compression for high-order data, but is not suitable for low-order data. Second, in the case of a large coefficient data value, 2
The number of bits of transmission data is smaller in the case of dividing in units of 3 bits than in the case of dividing in units of bits. Therefore, high-order coefficient data is converted into transmission data by an encoding method that is divided into three-bit units.

b. Buffering Process FIG. 8 shows a part related to the buffering process in one embodiment of the present invention in detail. From the absolute value conversion circuit 6
The AC coefficient is supplied to the multiplexer 21 and the multiplexer
21 output signals are supplied to the frequency distribution memory 9 as addresses. Further, the absolute value of the AC coefficient from the absolute value conversion circuit 6 is supplied to the maximum value detection circuit 7, and the maximum value detection circuit 7 detects the maximum value MAX1 for each M block. The maximum value MAX1 is supplied to the multiplexer 31, and the output signal of the multiplexer 31 is supplied to the frequency distribution memory 9 as an address. Further, the maximum value MAX2 of the AC coefficient for each S block detected by the maximum value detection circuit 8 is used as a multiplexer.
The output signal of the multiplexer 41 is supplied to the frequency distribution memory 11 as an address. Furthermore,
The absolute value of the AC coefficient is supplied to the multiplexer 51, and the output signal of the multiplexer 51 is supplied to the frequency distribution memory 12 as an address.

An M block counter indicated by 20 is provided.
Are supplied to the multiplexers 21, 31, 41 and 51 as upper addresses. The memory area of each of the memories 10, 11, and 12 is divided corresponding to the M blocks by the upper address. The memory 9 has M
The absolute value of low-order AC coefficient data of a block other than the block 4 (a block including coefficient data DC of a DC component) is stored. M block counter to distinguish this block
Twenty output signals are used.

The data read from the frequency distribution memory 9 is added to the adder circuit.
The signal is supplied to the adder 22, and is added to the output of the multiplexer 23 by the adder circuit 22. The multiplexer 23 is supplied with 0, +1 and the output signal of the register 24, and one of these input signals is selectively supplied to the adder circuit 22. The output signal of the adding circuit 22 is supplied to the register 24. The output signal of the register 24 is fed back to the multiplexer 23 and supplied to the multiplication circuit 25 as described above. This multiplication circuit
25 multiplies by three times, and the output signal of the multiplication circuit 25 is supplied to the addition circuit 26.

The data read from the frequency distribution memory 10 is used as an adder
The signal is supplied to the adder 32 and is added to the output of the multiplexer 33 by the adder circuit 32. The multiplexer 33 is supplied with 0, +1 and the output signal of the register 34, and one of these input signals is selectively supplied to the addition circuit 32. The output signal of the adding circuit 32 is supplied to the register 34. As described above, the output signal of the register 34 is fed back to the multiplexer 33 and supplied to the addition circuit 35.

In connection with the frequency distribution memory 11, similarly to the memory 10, an adder circuit 42, a multiplexer 43, and a register 44 are provided. The output signal of the register 44 is fed back to the multiplexer 43 and supplied to the addition circuit 35. The output signal of the addition circuit 35 is quadrupled by passing through the multiplication circuit 45, and the output signal of the multiplication circuit 45 is supplied to the addition circuit 46.

In association with the frequency distribution memory 12, similarly to the memories 10 and 11, an addition circuit 52, a multiplexer 53, a register 54, and a multiplication circuit (double circuit) 55 are provided. Multiplication circuit 45 and
55 can be constituted by a shift circuit.

As will be described later, the number of transmission bits Q related to the AC coefficient is obtained from the output of the addition circuit 26, and the number of transmission bits Q is supplied to the comparison circuit 56. The comparison circuit 56 is supplied with the target value P of the number of transmission bits from the terminal 57, and detects the magnitude relationship between the calculated number Q of transmission bits and the target value P. In the case of (P> Q), for example, a comparison output signal which becomes high level is generated.

The comparison output signal of the comparison circuit 56 is supplied to the mode generator 61 of the control signal generation circuit 14 which is surrounded by a broken line.
The mode generator 61 is, for example, a 4-bit mode control signal MD.
Occurs. This mode control signal MD is applied to the address generator 62.
And to the register 63. The mode signal generator 61
The mode number i is incremented from 0, and the comparison output signal for each mode number i is monitored. When the number of transmission bits Q and the target value P have a relationship of (P> Q), the mode number i is incremented. When the relationship of (P> Q) is not satisfied, the update of the mode number i is stopped.

The above-mentioned comparison output signal from the comparison circuit 56 is supplied to the register 63 as a clock, and when the relationship of (P> Q) is not satisfied, the mode control signal MD is taken into the register 63. Further, the address signal generated by the address generator 62 is supplied to the multiplexers 21, 31, 41 and 51, respectively.

The mode i controlled by the mode control signal MD is as follows, and the number of transmission bits increases in the order of the mode number i.

Mode 1: Transmit AC coefficient multiplied by 1/16.

Mode 2: Transmit AC coefficient multiplied by 1/14.

Mode 3: Transmit AC coefficient multiplied by 1/12.

Mode 4: Transmission is performed with the AC coefficient multiplied by 1/10.

Mode 5: AC coefficient is multiplied by 1/8 and transmitted.

Mode 6: The AC coefficient is multiplied by 1/6 and transmitted.

Mode 7: Transmit by multiplying the AC coefficient by 1/4.

Mode 8: Transmit by multiplying the AC coefficient by 1/2.

Mode 9: The AC coefficient is transmitted as it is.

The mode control signal MD from the register 63 is supplied to the weighting circuit 13 indicated by a broken line. The weighting circuit 13 is supplied with the mode control signal MD from the register 63 and the M block number generated by the counter 65 as an address, and reads out the ROM 64 for generating a weighting coefficient, the coefficient data from the buffer memory 5 and the ROM 64. And a multiplication circuit 66 for multiplying the weighting coefficient by the weighting coefficient. The output data of the multiplication circuit 66 is supplied to the formatting circuit 15 and is converted into transmission data together with the mode control signal MD.

In the weighting circuit 13, the reason why the M block number is supplied from the counter 65 is as follows.
This is because, instead of multiplying by a weighting coefficient such as 1/2, it is possible to more precisely multiply the weighting coefficient according to each block.

Hereinafter, a process for obtaining the number of transmission bits in the above-described embodiment will be described. The number of L blocks per field is represented by NB (for example, 2700 blocks / field).

First, the flags Fm and DC in the transmission data (see FIG. 5)
Must be transmitted in all blocks regardless of the image content. That is, (3 + 10) × NB = 13NB is a fixed data amount. Flags Fs and Fp and AC coefficient data DATA1
And the number of bits of DATA2 is variable, and it is necessary to know these bit numbers. The comparison circuit 56 compares the generated data amount Q with the target value P for a variable number of bits.

First, calculation of the amount of generated information for low-order AC coefficient data will be described. A frequency distribution of absolute values of all low-order AC coefficient data (15 × NB) in one field is created, and this frequency distribution is converted into a cumulative frequency distribution.

The frequency distribution memory 9 is cleared before writing.
The adder circuit 22 generates zero data at the time of the clear operation, and the sequentially changing address from the address generator 62 of the control signal generation circuit 14 is supplied to the memory 9 via the multiplexer 21 and zero data is stored in all addresses. Written.

After this clearing, the multiplexer 21 sets the absolute value conversion circuit 6
Absolute value of AC coefficient data from M and M block counter 20
And the multiplexer 23 selects the +1 input. The data of the address specified by the absolute value of the AC coefficient data and the output of the M block counter 20 is stored in the memory 9.
, And +1 is added by the adder circuit 22. The output data of the adding circuit 22 is written to the same address as the input data of the memory 9. After this process is performed for one field period, the frequency distribution memory 9 stores a frequency distribution table of the absolute values of the AC coefficient data around the DC component.

FIG. 9A is a frequency distribution raw graph in which the horizontal axis represents the absolute value n of the low-order AC coefficient and the vertical axis represents the frequency of occurrence. By accumulating the frequency distribution from the maximum value side, for example, from 511 to 0, the cumulative frequency distribution graph AC (n) shown in FIG. 9B is obtained.
Is obtained. In this embodiment, as shown in FIG.
9 types of requantization steps (1,2,4,6,8,10,12,14,16)
Is used, and each requantization step causes a lower order AC
The coefficient data is divided, and the value obtained by rounding the quotient to an integer is the value to be transmitted. In FIG. 10, n0, n1, n
2, n3, and n4 indicate values of points at which the number of bits of transmission data changes, corresponding to the requantization step. From the cumulative frequency distribution graph AC (n) and the values (n0, n1, n2, n3, n4), the amount of generated information can be calculated for low-order AC coefficient data. For example, when the requantization step is “1”, the amount of generated information can be obtained by the following equation.

(AC (0)-AC (2)) x 3 (AC (2)-AC (10)) x 6 + (AC (10)-AC (42)) x 9 + (AC (42)-AC (170) ) × 12 + (AC (170) × 15 = 3 × {AC (0) + AC (2) + AC (10) + AC (42) + AC (170)} In other words, low-order AC coefficient for each quantization step The amount of data generated information is Can be calculated. In order to obtain the value of AC (n) from the cumulative frequency distribution table, the address generator 62 sequentially generates addresses according to the mode number (requantization step).

Next, the calculation of the data amount of the flag Fs will be described.
The flag Fs must be sent when there is any AC coefficient having a non-zero value in 16 samples belonging to three M blocks. Therefore, it is sufficient to pay attention to the maximum value MAX1 of the AC coefficient of each M block. So 1
A frequency distribution of the maximum value MAX1 of the absolute value of the AC coefficient of each of the M blocks in the field is created, and this frequency distribution is converted into a cumulative frequency distribution.

The frequency distribution memory 10 is cleared before writing.
The adder circuit 32 generates zero data at the time of the clear operation, and the sequentially changing address from the address generator 62 of the controller signal generation circuit 14 is supplied to the memory 10 via the multiplexer 31, and the zero data is stored in all the addresses. Written.

After this clearing, the multiplexer 31 selects the maximum value MAX1 detected by the maximum value detection circuit 7 and the M block address, and the multiplexer 33 selects the +1 input. The data at the address specified by the maximum value MAX1 and the M block address is read from the memory 10 and
Is incremented by 1. The output data of the adder 32 is stored in the memory 10
Is written to the same address as the input data. This writing is performed once in 16 samples. After this processing is performed for one field period, the frequency distribution memory 10 stores M blocks M1, M2, and M3,
A frequency distribution table of the maximum value MAX1 of the absolute value of the AC coefficient is stored, respectively.

Also, like the frequency distribution memory 10, the frequency distribution memory 11
Is first cleared to zero, and then the memory 11 is incremented by 1 in the adder circuit 42 using the maximum value MAX2 of the absolute value of the AC coefficient detected for each S block and the M block address as addresses.
Is written to the same address, a frequency distribution table for one field period of the maximum value MAX2 of the absolute value of the AC coefficient is formed in the memory 11 for each M block. This writing is performed once in four samples.

Further, like the frequency distribution memories 10 and 11, the frequency distribution memory 12 is first cleared to zero, and then the addition circuit 52 is set using the absolute value of the AC coefficient and the M block address as addresses.
By writing the contents of the memory 12 incremented by 1 into the same address, a frequency distribution table of the absolute value of the AC coefficient in one field period is formed in the memory 12 for each M block.

After the distribution tables of the occurrence frequencies for one field are formed in the memories 10, 11 and 12, the cumulative frequency distribution tables are formed from these frequency distribution tables. In order to form the cumulative frequency distribution table, the multiplexers 31, 41 and 51 are switched to the state of selecting the output of the address generator 62 of the control signal generating circuit 14, and the multiplexers 33, 41
43 and 53 are switched to select the outputs of registers 34, 44 and 54, respectively. The address generator 62 has three M
In order to form the cumulative frequency distribution of each block, M blocks are distinguished by the upper bits, and values are distinguished by the lower bits.

The read output of the above address is added to the outputs of the registers 34, 44 and 54 by the adders 32, 42 and 52, respectively.
The registers 34, 44, and 54 are cleared to zero prior to the creation of the cumulative frequency distribution table. Therefore, the values accumulated from the maximum address are written in the memories 10, 11, and 12 for each M block.

FIG. 11A shows the maximum value of the absolute value of the AC coefficient for each M block.
6 is a frequency distribution graph with MAX1 as the horizontal axis and the frequency of occurrence as the vertical axis. By accumulating the frequency distribution from the side of the maximum value, for example, 511, toward 1, a cumulative frequency distribution graph S (n) shown in FIG. 11B is obtained. When the minimum value n0 to be transmitted is determined from the cumulative frequency distribution graph S (n), the number S (n0) of M blocks to be transmitted is known. Since a 4-bit flag Fs is transmitted per M block, the number of transmission bits of the flag Fs is S (n0) × 4 (bits) (2).

Next, the number of transmission bits of the flag Fp will be described. Similar to the bit number of the flag Fs, as shown in FIG. 11C, a frequency distribution graph having the maximum value MAX2 of the absolute value of the AC coefficient for each S block as the horizontal axis and the frequency of occurrence as the vertical axis is stored in the memory. Ten
Formed. By accumulating the frequency distribution from the side of the maximum value, for example, 511, to 0, a cumulative frequency distribution graph P (n) shown in FIG. 11D is obtained. When the minimum value n0 to be transmitted is determined from the cumulative frequency distribution graph P (n), the number P (n0) of S blocks to be transmitted is known. Since a 4-bit flag Fp is transmitted in one S block,
The number of transmission bits of the flag Fp is P (n0) × 4 (bits) (3).

Further, a frequency distribution table is formed in the memory 12 with all coefficient data (higher order coefficient data) of the M blocks as addresses. This frequency distribution table is converted into a cumulative frequency distribution table in the same manner as the flag. In the case of M block, low order AC
An encoding rule different from the coefficient data is applied. Therefore,
Even when the requantization step is set similarly to the low-order AC coefficient data, the value at the point where the expression bit length changes is different from that in FIG. FIG. 12 shows the changing points of the number of expression bits for higher-order AC coefficient data. From the cumulative frequency distribution table formed in the memory 12 and the value of the expression bit number change point, the amount of generated high-order AC coefficient data can be calculated in the same manner as the low-order AC coefficient data. For example, when the requantization step is “8”, the number of data samples and the number of transmission bits are as follows.

* Number of samples of 7-bit AC coefficient: AC (260) Number of transmission bits: 14AC (260) * Number of samples of 6-bit AC coefficient: AC (260)-AC (132) Number of transmission bits: 12 (AC (260) ) -AC (132)) * Number of samples of 5-bit AC coefficient: AC (132) -AC (68) Number of transmission bits: 10 (AC (132) -AC (68)) * Sample of 4-bit AC coefficient Number: AC (68) -AC (36) Number of transmission bits: 8 (AC (68) -AC (36)) * Number of samples of 3-bit AC coefficient: AC (36) -AC (20) Number of transmission bits: 6 (AC (36)-AC (20)) * Number of samples of 2-bit AC coefficient: AC (20)-AC (12) Number of transmission bits: 4 (AC (20)-AC (12)) * 1 bit Number of samples of AC coefficient of: AC (12) −AC (4) Number of transmission bits: 2 (AC (12) −AC (4)) Therefore, when the requantization step is “6”, transmission bits related to the AC coefficient The numbers are as follows:

2 (AC (12)-AC (4)) x 4 (AC (20)-AC (12)) x 6 + (AC (36)-AC (20)) + 8 (AC (68)-(AC (36 )) + 10 (AC (132) -AC (68)) + 12 (AC (260) -AC (132)) + 14AC (260) = 2 (AC (4) + AC (12) + AC (20) + AC (36) + AC (68) + AC (132) + AC (260)) (4) The number of transmission bits is (1), (2), (3) and (4)
This is the sum of the number of bits calculated by the equation, and the number of transmission bits changes according to the mode number (requantization step).

In FIG. 8, the amount of generated information represented by equation (1) is
It is obtained from the multiplication circuit 25. The sum of the amounts of generated information represented by the expressions (2) and (3) is obtained at the output of the multiplication circuit 45, and the amount of generated information represented by the expression (4) is obtained at the output of the multiplication circuit 55. Can be The output of the addition circuit 46 and the output of the multiplication circuit 25 are supplied to the addition circuit 26, from which the generated information amount Q relating to a variable data amount is obtained.

When (P> Q) is no longer satisfied by changing the mode number, the change of the mode number i is stopped. The mode number at this time is adopted. The mode control signal MD indicates the adopted mode number.

As described above, the mode in which the number of transmission bits is smaller than the target value is determined, and the weighting circuit 13 multiplies the AC coefficient delayed in the buffer memory 5 by the weighting coefficient corresponding to the mode.

c. Modifications In the above embodiment, the data in one field is (8 ×
8) and so on. However, data in one frame may be divided. Further, a block may be formed from two frames of image data in order to improve the compression ratio.

Further, the formatting circuit 15 may perform processing such as error correction coding and addition of a synchronization pattern. The number of transmission bits that increases in these processes is a fixed amount.

The present invention is applicable not only to two-dimensional blocks but also to transform coding applied to three-dimensional blocks.

The input image signal is not limited to a luminance signal of a television signal, but may be a component color video signal. The components may be processed simultaneously, or the components may be processed separately.

The transform code is not limited to the cosine transform, but may be an orthogonal transform or the like.

〔The invention's effect〕

According to the present invention, the amount of data that needs to be transmitted can be controlled to be smaller than the target value by the feedforward control. Therefore, unlike feedback control, problems such as oscillation do not occur. Further, the present invention can accurately control the data amount in units of one field or one frame, and is suitably applied to a digital VTR. Further, since the present invention does not require a complicated circuit such as a sorting circuit, there is an advantage that the circuit scale does not increase. Further, in the present invention, since the amount of generated information is obtained for each M block, the amount of generated information can be finely controlled with an independent threshold value for each M block.
In particular, since the coefficient data of the AC component is divided into low-order coefficient data and high-order coefficient data, and converted into transmission data according to an encoding rule suitable for each, the efficiency of coefficient data compression can be improved. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an entire system according to an embodiment of the present invention, FIG. 2 is a schematic diagram showing an example of a DCT transform block, FIG. 3 is a schematic diagram showing fixed weighting factors, FIG. FIG. 5 is a schematic diagram used for explaining an image area division and a flag, FIG. 5 is a schematic diagram showing a configuration of transmission data, FIG. 6 and FIG.
FIG. 8 is a schematic diagram used to explain the rules of code conversion into transmission data, FIG. 8 is a detailed block diagram of a part of one embodiment of the present invention, FIG. 9, FIG. FIG. 12 is a schematic diagram used for explaining a buffering process, and FIG. 13 is a block diagram used for explaining a conventional technique. Explanation of main symbols in the drawing 2: Blocking circuit, 3: Cosine conversion circuit, 5: Buffer memory, 7: Circuit for detecting maximum value MAX1 of AC coefficient data for each M block, 8: AC coefficient for each S block Circuit for detecting the maximum value MAX2 of data, 9, 10, 11, 12: frequency distribution memory, 13: weighting circuit, 14: control signal generation circuit, 15: formatting circuit, 16: output terminal.

Claims (1)

(57) [Claims] 1. An image obtained by orthogonally transforming (n × n) pixels
Among the n ² coefficient data in (n ² -1) pieces of the data transmission apparatus for transmitting compressed coded coefficient data of the AC component coefficient data of the (n ² -1) pieces of the AC components It is divided into low-order coefficient data and high-order coefficient data, and each coefficient data of the low-order coefficient data is assigned an integer multiple of the first bit number and converted into transmission data.
A data transmission device wherein the higher-order coefficient data is converted to the transmission data by assigning an integer multiple of the second bit number smaller than the first bit number to the transmission data. .