JPS62123834A - Coding transmission system - Google Patents

Abstract

PURPOSE:To eliminate the effect of uncovered background and to attain high compression by using a background memory. CONSTITUTION:The output of a blocking circuit 2 is inputted to a standstill discrimination circuit 3 and whether or not picture elements belonging to a different frame are coincident is checked. Further, an encoder block 7 checks the dynamic range, the adapted quantization is supplied and the result is compared with a picture element data in the background memory 4 by a comparator 6 and whether or not they are coincident in the unit of blocks and picture elements is checked. When the decision circuit 3 detects that the coincidence between different frames and the data is not coincident with a data SB of the background memory 4, an AND gate 12 supplies a revision code SR to write an input picture element in the background memory 4. A framing circuit 9 sends the revision code SR, a background code SB, a quantized width DELTA, a representative minimum level L0, and a coding code DT. The reception side restores the original picture from the codes.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an encoding transmission method for compressing the number of bits per pixel of an image signal such as a digital television signal and transmitting the compressed bit number.

[Summary of the invention]

This invention provides a background memory for storing background information on each of the transmitting side and the receiving side in a coding transmission system commonly used for band-compressing and transmitting image signals such as digital television signals. By looking at the motion state between consecutive frames of a predetermined period and holding fixed background information in these background memories, it is possible to form transmission data with a reduced number of bits compared to the number of bits of the original data. In addition, by encoding only necessary frames, redundancy in the temporal direction can be removed and a significant compression rate can be achieved.
This solves the problem of missing information (anchor hard background noise).

[Conventional technology]

As methods for encoding television signals, several methods are known in which the average number of bits per pixel or the sampling frequency is reduced in order to narrow the transmission band.

As an encoding method that lowers the sampling frequency, subsampling is used to thin out the image data to 172 pixels, and indicate the subsampling point and the position of the subsampling point used during interpolation (i.e., either above, below or to the left or right of the interpolation point). A method has been proposed that transmits a flag (indicating whether to use data at sub-sampling points).

One of the encoding methods that reduces the average number of bits per pixel is D PCM (differenti
alPCM) is known. DPCM focuses on the fact that the pixels of a television signal have a high correlation and the difference between adjacent pixels is small, and this difference signal is quantized and transmitted.

Another encoding method that reduces the average number of bits per pixel is to subdivide one field screen into small blocks and calculate the deviation of the pixel at the representative point and the level distribution of data within the block for each block. There is something to transmit.

[Problem that the invention seeks to solve]

The encoding method that attempts to reduce the sampling frequency using subsampling has a sampling frequency of 172
Therefore, there was a risk that aliasing distortion would occur.

DPCM has a problem in that coding errors propagate to subsequent coding.

The method of encoding in units of blocks has the disadvantage that block distortion occurs at the boundaries between blocks.

SUMMARY OF THE INVENTION An object of the present invention is to provide an encoding transmission method that does not have the problems of the above-mentioned conventional techniques, such as generation of aliasing distortion, propagation of errors, and generation of block distortion.

The applicant of this application has determined a dynamic range defined by the maximum and minimum values of a plurality of pixels included in a two-dimensional block, as described in Japanese Patent Application No. 59-266407, and kE is a coding transmission method that performs adaptive coding. This invention is
This invention relates to the improvement of a coding transmission method using two-dimensional blocks, and provides a coding transmission method that determines the dynamic range of a three-dimensional block and codes a digital television signal while adapting to this dynamic range. The purpose is to

Further, another object of the present invention is to obtain patent application No. 58-237.
By introducing a background memory as described in the specification of No. 371, storing background information in this background memory, and compressing and encoding only frames (or fields) that are different from the background information, a significant compression rate is achieved. An object of the present invention is to provide a coding transmission method that can reduce the influence of uncovered background noise.

[Means for solving problems]

The present invention includes an encoding circuit 7 that blocks an input image signal at a predetermined period spanning a plurality of fields and compresses and encodes the data for each block; It has a determination circuit 3.6.12 that determines whether or not there is a change in data, and a background memory 4 that stores data of background image information, and an encoding circuit 7 based on the output of the determination circuits 3 and 6.12. In addition, it controls whether or not the contents of the background memory 4 are updated by the signal obtained by decoding the encoded output, and the encoded output of the encoding circuit 7 and the determination circuit 3, 6.12
The receiving side has a memory 24 corresponding to the background memory 4 of the transmitting side, and the transmitted data frames the background memory 4 of the transmitting side.
This encoding transmission method is characterized in that the memory 24 is updated in synchronization with the image data and the image is restored.

[Operation] Image signals such as television signals have three-dimensional correlation in the horizontal direction, vertical direction, and time direction, so in the stationary part, the correlation between pixel data included in the same three-dimensional block is is strong. Therefore, it is easy to compress and encode data in units of blocks.

For example, the minimum level M shared by pixel data within a block
Even if the Guinami clean range of the data DTI after r N is removed is quantized using a smaller number of quantization bits than the original number of quantization bits, almost no quantization distortion occurs. By reducing the number of quantization bits, the data transmission bandwidth can be made narrower than the original one.

In addition, if multiple fields (or frames) in a block are the same image, the encoding code of only one image is transmitted, and the discrimination code indicating that the images of other frames are still parts is transmitted. Transmitted instead of encoded code. In this case, when the fixed background is the same as the fixed background stored in the background memory, there is no need to encode and transmit a single image, and a high compression rate can be achieved. Moreover, the background information stored in the background memory can solve the problem of uncovered hack ground noise, where the background information of the previous position disappears after the moving object moves.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. This description is given in the following order.

a, Configuration of the transmitting side, Configuration of the receiving side C, Block and blocking circuit d, Encoder block e, II child circuit, Modification a, Configuration of the transmitting side. This shows the configuration as a whole. For example, an NTSC digital television signal in which one sample is quantized to 8 pins is input to an input terminal indicated by 1. This digital television signal is supplied to the blocking circuit 2.

The blocking circuit 2 converts the input digital television signal into a continuous signal for each block, which is a unit of encoding. The output signal of the blocking circuit 2 is supplied to the static determination circuit 3. The stillness determination circuit 3 checks whether corresponding pixels in the two-dimensional area included in each of the four frames in the three-dimensional block match each other, and assigns a one-bit determination code SS indicating a match or mismatch to each pixel. This is a circuit that occurs every time. The stillness determination circuit 3 detects the absolute value of the difference between pixels at corresponding positions in two two-dimensional regions belonging to different frames, and determines that the two pixels are the same when the absolute value of this difference is sufficiently small. be judged.

Reference numeral 4 indicates a background memory consisting of a frame memory, into which output data of the update control circuit 5 is written. The background data read from the background memory 4 is supplied to the comparison circuit 6.

The comparator circuit 6 is supplied with the human-powered television signal from the blocking circuit 2 .

The comparison circuit 6 generates a background code SB for each block and one background code SP for each pixel. The background code SB for each block indicates whether each of the two-dimensional areas included in each of the four frames in the three-dimensional block matches the background/information at the corresponding position stored in the background memory 4. This is a bit signal. The pixel-based background code SP is a 1-bit signal indicating whether input pixel data and corresponding pixel data in the background memory 4 match. The background code SP becomes high level when there is a match.

The comparison circuit 6 compares four 2's of each frame of the same block.
The absolute value of the difference between the pixel data included in the dimensional area and the pixel data in the background memory 4 at the position corresponding to the two-dimensional area is detected, and when the absolute value of this difference is sufficiently small, it is determined that they match.

The output data of the blocking circuit 2 is sent to the encoder block 7.
supplied to The encoder block 7 performs encoding adapted to the dynamic range of each block. That is, the encoder block 7 calculates the maximum level MAX, the minimum level Mlli, and the dynamic range DR of each of the professional and the professional signals. This dynamite clean range DR
By dividing the quantization width by the number of steps corresponding to the number of quantization bits, the quantization width Δ of 4 bits is determined, and the quantization width Δ of 8 bits is determined.
A representative minimum level LO of bits is detected. Quantization width Δ
The pixel data DT■ after the minimum level removal is quantized. It is determined in which region of the divided regions the pixel data DTI after the minimum level removal is included, and a 4-bit encoded code DT that specifies the region is formed by quantization.

The output of the encoder block 7 is supplied to a framing circuit 9 via a gate circuit 8. Further, the output of the encoder block 7 is supplied to the decoder block 11. The decoder block 11 performs decoding processing that is the reverse of the processing performed by the encoder block 7, and generates decoded image data as its output. This image data is supplied to the update control circuit 5.

The determination code F S S from the stillness determination circuit 3 and the background code SP for each pixel from the comparison circuit 6 are supplied to the AND gate 12 . An update code SR is generated at the output of this AND gate 12. When this update code SR is at a high level, the corresponding data in the background memory 4 is updated. In other words, when the four corresponding pixels belonging to each of the four frames in the block match, and the corresponding input pixel does not match the corresponding data in the background memory 4, the update code S
R is set to high level, and this input pixel is written into the background memory 4.

The update code SR is transmitted to the framing circuit 9 and the update control circuit 5.
supplied to The background code SB for each block from the comparison circuit 6 is supplied to the gate circuit 8 and the framing circuit 9. In this example, update code SR1 background code S
B, @ child width Δ, representative minimum level LO1 encoding code D
I am trying to transmit T. These data are supplied to the framing circuit 9 and converted into transmission data.

As for the format of the transmission data, each data part consisting of update code SR1, background code SB, representative minimum level LO, quantization width Δ, and encoding code DT is encoded with an independent error correction code, and each error correction is performed. It is possible to use one that adds code parity for transmission. In addition, update code 1"S R1 background code SB other than encoded code DT,
The quantization width Δ and the representative minimum level LO may each be encoded with independent error correction codes. Furthermore, a common error correction code is applied to both the update code SR2, the background code SB, the quantization width Δ, and the representative minimum level LO,
You may add that parity.

Transmission data is taken out to an output terminal 10 of the framing circuit 9. Although not shown, the transmission data from the framing circuit 9 is transmitted as serial data (or recorded on a recording medium).

The background code SB for each block determines the input data block and the corresponding professional code stored in the background memory 4.
When it is determined that the blocks are the same, the gate circuit 8 prohibits transmission of that one block. Only the outputs of the encoder block 7 of blocks that are not identical to the image stored in the background memory 4 are supplied via the gate circuit 8 to the framing circuit 9 and transmitted.

The update control circuit 5 includes a subtraction circuit that subtracts the read data of the background memory 4 from the decoded data from the decoder block 11 for each corresponding pixel, and a multiplication circuit that multiplies the output of this subtraction circuit by a predetermined weighting coefficient for each pixel. , an addition circuit that adds the output of this multiplication circuit and the read data of the background memory 4, and a weighting coefficient generation circuit that generates a predetermined weighting coefficient.

Assuming that the output data from the update control circuit 5 is Yk, the output data of the background memory 4 of the previous frame is Yk-1, the corresponding pixel data in the image data from the decoder block 11 is Xk, and the weighting coefficient is Wk. , output data Yk is generated from the update control circuit 5 according to the following equation.

Yk = Yk - 10Wk (Xk - Yk - 1) = W
k Xk + (1-Wk) When the Yk-1 update code SR is low level and no update is performed
Writing to the background memory 4 is prohibited or (Wk=
O) and the same data as before is written.

When the update code SR is at a high level, data Yk processed according to the above calculation is written into the background memory 4. In this case, a memory is provided in which a weighting coefficient is stored for each pixel, and the weighting coefficient is read out when updating. In other words, at the first update, for example, (wk = 1/8) is set, and thereafter, the weighting coefficient is sequentially doubled, and (1/4.1/
2.1).

By changing the weighting coefficients in this manner, when the background changes, the response time can be shortened and the effect of colored noise can be avoided.

b. Receiving side configuration FIG. 2 shows the configuration of the receiving (or reproducing) side.

The received data from the input terminal 21 is sent to the frame decomposition circuit 2.
2. The frame decomposition circuit 22 separates the encoded code DT, additional codes Δ, LO, background code SB, and update code SR, and performs error correction processing. These 4-bit encoded code DT and additional code are supplied to a decoder block 23.

The decoder block 23 performs processing opposite to that of the encoding block 7 on the transmitting side. That is, the data DTT after removing the 8-bit minimum level is formed, and this data DTT
and the 8-bit representative minimum level LO are added, and the original pixel data PDI is decoded. The output data PDI of the decoder block 23 is transmitted to the update control circuit 25 and the selector 26.
supplied to

The update control circuit 25 is supplied with the read output from the background memory 24 . Update code SR from frame decomposition circuit 22 controls updating of background memory 24 .

When the update code SR is at a high level, the contents of the background memory 24 are replaced by the restored data from the decoder block 23.

Read output of background memory 24 and decoder block 23
The selector 26 selects one of the restored data. The background code SH for each block allows the background memory 24
Regarding the same block, the output of the background memory 24 is selected instead of the restored data. The output of this selector 26 is supplied to a block decomposition circuit 27.

The block decomposition circuit 27 is a circuit for converting decoded data in the order of blocks into the same order as the scanning of the television signal, contrary to the blocking circuit 2 on the transmitting side. The original television signal is decoded and output to the output terminal 28 of the block decomposition circuit 27.

b. Description of Blocks Blocks, which are units of encoding, will be described with reference to FIG. In FIG. 3, B is a two-dimensional area bl belonging to each of the four frames.

b2. b3. This shows an l block consisting of b4, where solid lines indicate odd field lines and broken lines indicate even field lines. The 8 pixels included in each of the 8 lines of each frame form the areas bl, b2°, b3 . b4 is configured. Therefore, one block is composed of (8x8x4=256) pixels.

The smaller the number of quantization bits of the encoded code DT, the better, in order to suppress redundancy. However, in order to avoid increasing quantization distortion, the number of quantization bits must not be reduced too much. When the number of quantization bits is 8 bits, there are 256 possible levels of the television signal (0 to 255).

However, in a stationary area excluding unsteady areas such as the contour of an object, 1
The level distribution of the pixels of the block is concentrated in a narrow level range. In the case of television signals, each pixel within one three-dimensional block has a correlation, so
In the steady portion, the dynamic range DR is not very large, and a maximum value of 128 is sufficient. Therefore, even if the number of bits of the encoded code is 4 bits as in this embodiment, it is possible to prevent quantization distortion from increasing.

That is, the dynamic range DR is 128 in the worst case.
becomes. Even in this case, when the number of quantization nodes is 4 bits, the division level unit is 8, and the quantization distortion is 4 bits.
becomes. This degree of quantization distortion cannot be visually discerned. On the other hand, in the unsteady part, the variation width becomes large, but in the present invention, the dynamic range DR is adaptively determined, so that a drop in response does not occur in the transient part.

FIG. 4 shows an example of the configuration of the blocking circuit 2 described above. Frame memories 15, 16, and 17 are connected in cascade to the input terminal 1. The pixel data of the current frame F4 and the previous three frames F3 . F2.
Pixel data of Fl is supplied to the scan conversion circuit 1. At the output terminal 19 of the scan conversion circuit 18, corresponding two-dimensional areas b1. b2. b3. Each pixel data of b4 is obtained sequentially. That is, as shown in FIG.
Four consecutive frames Fl, F2 . Corresponding areas bl, b2 . b3° and b4 are output in the order indicated by the numbers. Within each area, data is output in accordance with the scanning order.

d, encoder block FIG. 6 shows an example of the configuration of the encoder block 7. As shown in FIG.

The blocking circuit 2 sequentially supplies the image data of the area that needs to be encoded for each block to the input terminal 31, as described above.

The pixel data from this input terminal 31 is sent to a delay circuit 32,
The signal is supplied to the selection circuit 33 and the selection circuit 34. One selection circuit 33 selects and outputs the one with a higher level between the pixel data of the input digital television signal and the output data of the latch 35. The other selection circuit 34 selects the pixel data of the input digital television signal.
Between the output data of the notch 36, the one with the smaller level is selected and output.

The output data of the selection circuit 33 is supplied to the subtraction circuit 37 and is also taken into the latch 35. The output data of the selection circuit 34 is supplied to the subtraction circuit 37 and the latch 39, and is also taken into the latch 36. Latches 35 and 36
A latch pulse is supplied from the control section 40.

The control unit 40 is supplied with a sampling clock from a terminal 41 that is synchronized with the input digital television signal. A synchronization signal synchronized with the input digital television signal is supplied to the control section 40 from an input terminal 42. The control unit 40 supplies latch pulses to the launch 35° 36 and latches 38 and 39 at predetermined timing.

At the beginning of each block, the contents of latches 35 and 36 are initialized. The latch 35 is initialized with data of all degrees 0, and the launch 36 is initialized with data of all degrees l. Among the pixel data of the same block that is sequentially supplied, the maximum level is The pixel data is stored in the latch 35. Also, among the pixel data of the same block that is sequentially supplied, the minimum level is stored in the latch 36.

When the detection of the maximum level and minimum level is completed for one block, the maximum level of the block appears at the output of the selection circuit 33. On the other hand, the minimum level of the block is generated at the output of the selection circuit 34.

(2) When the detection for the block is completed, the latches 35 and 36 are initialized again.

The dynamic range DR of each block is obtained from the output of the subtraction circuit 37 by subtracting the maximum level MAX from the selection circuit 33 and the minimum level MTN from the selection circuit 34. These dynamic range DR and minimum level M T N are latched by latches 38 and 39, respectively, by a latch pulse from control section 40.

Dynamic range DR stored in lunch 38 is RO
Supplied to M43. The ROM 43 generates a quantization width Δ by dividing the dynamic range DR according to the number of bits of the encoded code. In other words, this ROM
43 is supplied with an 8-bit address, and 1/16 (
In the case of 4-bit quantization), the quantization width Δ (4 bits) of the rounded result is
It is read from 3. This quantization width Δ is taken out to the output terminal 47 and is also supplied to the quantization circuit 50.

The minimum level MIN stored in the latch 39 is
6 and is also supplied to one input terminal of the subtraction circuit 51. The input digital television signal PD via the delay circuit 32 is supplied to the other input terminal of the subtraction circuit 51.

Therefore, the data DTT after minimum level removal is obtained as the output of the subtraction circuit 51, and this data DTT is sent to the quantization circuit 51.
supplied to The quantization circuit 50 has a configuration to be described later, and a 4-bit encoded code DT is taken out at its output terminal 48.

The other input terminal of the adder circuit 46 is supplied with the data of A to the quantization width via the A multiplier circuit 45 . The representative minimum level LO generated at the output of the adder circuit 46 is taken out to an output terminal 49.

e. Quantization circuit FIG. 7 shows the configuration of an example of the above-mentioned ROM 43 and quantization circuit 50. However, to simplify the explanation, the number of quantization bits is set to 2 bits instead of 4, and the dynamic range is divided into 4.

In FIG. 7, 51 indicates an input terminal to which the dynamic range DR is supplied, and 52 indicates an input terminal to which the data DTT after minimum level removal is supplied. The dynamic range DR is set to 1/4 level by the ROM 43, and the quantization width Δ is read from the ROM 43.

The output of this ROM 43 is supplied to multipliers 54 and 55. The output tripled by the multiplier 54 is supplied to one input terminal of the level comparator 56. The output doubled by the multiplier 55 is supplied to one input terminal of the level comparator 57. The output of the ROM 43 is supplied to one input terminal of the level comparator 58. These level comparators 5
The data DTI after minimum level removal is supplied to the other input terminal of each of the input terminals 6, 57, and 58.

The respective outputs of level comparators 56, 57, and 58 are CI, C
2 and C3, these outputs C1, C2, and C3 change as follows depending on the level of data DTI.

(li (3/4) D CI when R≦DTI≦DR
="l', C2="1", C3="l't2'
l When (2/4)DRSDTI<(3/4)DRC
1 = 'O', C2 = "1', C3 = "1''(3>
(1/'4)DR5DTI<(2/4)C when DR
1='O', C2='0'', C3='l.

f4) OSDT I < (1/4) CI at DR
='O', C2="0°, C3="0" The outputs CI, C2, and C3 of the level comparators 56, 57, and 58 described above are supplied to the priority encoder 59. The priority encoder 59 causes the output terminal 48 to The priority encoder 59 generates the encoded code (11) in the case (1) above, and generates the encoded code (10) in the case (2) above. Generate an encoded code, and in the case of (3) above, (01)
In the case of (4) above, (0
0) is generated.

Pixel data PD including the minimum level MIN within one block
As shown in FIG. 8, belongs to the dynamic range DR from the minimum level MIN to the maximum level MAX. The ROM 43 outputs a quantization width Δ obtained by equally dividing this dynamic range DR into four. Comparators 56, 57, and 58 determine which of the divided level ranges the data DT2 after the minimum level has been removed belongs to, and is converted into a 2-bit encoded code DT corresponding to the level range. Further, the representative minimum level LO is calculated by adding 2Δ to the minimum level M E N. These quantization widths Δ1 representative minimum level O1 encoding code DT
is transmitted.

In this embodiment, as is clear from FIG. 8, the dynamic range is equally divided by the quantization width Δ, and the median values of each region are LO, LL, L2, . L3 is used as a value during decoding. This encoding method can reduce quantization distortion.

On the other hand, the minimum level M T N and the maximum level M A
Pixel data having each level of X always exists within one block. Therefore, in order to create a large number of encoded codes with an error of O, the dynamic range DR is divided into (2'''-1) (where m is the number of quantization bits) as shown in FIG. The minimum level MIN may be set as the representative minimum level LO, and the maximum level MAX may be set as the representative maximum level L3.

When performing the quantization shown in FIG. 9, the minimum level M T
N is output as is as the representative minimum level LO, and RO
It is assumed that M43 performs division by (1/15).

In addition to the configuration shown in FIG. 7, the quantization circuit 50 uses a digital divider, supplies the quantization width Δ to the digital divider as a denominator input, and calculates the data DT after minimum level removal.
A configuration may also be adopted in which T is supplied to the divider as a numerator input. This divider generates a 2-bit output corresponding to a value obtained by truncating fractions below the decimal point as an encoded code.

f. Modification In the above explanation, three items are transmitted: the encoded code DT, the quantization width Δ, and the representative minimum level LO.

However, the dynamic range DR may be transmitted instead of the quantization width Δ as an additional code, or one of the quantization width Δ or the dynamic range DR and the representative maximum level may be transmitted.

In addition, one block of data is processed by a circuit that combines a frame memory, a line delay circuit, and a sample delay circuit.
They may be taken out at the same time.

Furthermore, the number of bits in the background code SB for each block may be increased to indicate information on the mutual relationship between regions of each frame, in addition to the coincidence and mismatch with the information stored in the background memory. good.

That is, four areas bl, b2. b3. When b4 match each other but differ from the information stored in the background memory, only one encoded output is transmitted within the same area, such as transmitting only the encoded output of − areas. If the data is transmitted, further compression becomes possible.

〔Effect of the invention〕

According to this invention, the amount of data to be transmitted can be sufficiently reduced compared to the original data, and the transmission band can be narrowed. Further, the present invention has the advantage that in a stationary portion where the variation range of pixel data is small, the original pixel data can be almost completely restored from the received data, and there is almost no deterioration in image quality. Furthermore, according to the present invention, since the dynamic range is determined for each block, the response is good at transient parts such as edges where the range of change is large.

Further, according to the present invention, by providing a background memory, redundancy in the time direction can be removed without deteriorating image quality, so that high compression is possible. However, since background information is stored in the background memory, it is not affected by the uncovered background.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the transmitting side according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the receiving side, and FIG. 3 is a route diagram used to explain blocks that are units of encoding processing. 4 and 5 are an example of the configuration of a blocking circuit and a route diagram for explaining it, FIG. 6 is a block diagram of an example of an encoder block, FIG. 7 is a block diagram of an example of a quantization circuit, and FIG. 8 and 9 are route maps γ for explaining one example of quantization and another example. Explanation of main symbols in the drawings 1: Digital television signal input terminal, 2-blocking circuit, 3: Stillness determination circuit, 4: Background memory, 5:
Update control circuit, 7: encoder block, 8: gate circuit, 11 decoder block. Agent Patent Attorney Tadashi Sugiura Tomo

Claims (1)

[Claims] An encoding circuit that blocks an input image signal at a predetermined period spanning a plurality of fields and compresses and encodes the data for each block; It has a determination circuit that determines whether there is a change in data at a corresponding image position, and a background memory that stores data of background image information, and controls the encoding circuit based on the output of the determination circuit, and also controls the encoding circuit according to the output of the determination circuit. It controls whether or not the contents of the background memory are updated with a signal obtained by decoding the encoded output, and the encoded output of the encoder circuit and the output of the determination circuit are framed and transmitted, and the receiving side An encoded transmission system comprising a memory corresponding to the background memory on the transmitting side, and updating the transmitted data in synchronization with the background memory on the transmitting side to restore an image.