JPS6359187A - Highly efficient encoder - Google Patents

Abstract

PURPOSE:To prevent the generation of distortion in a block due to impulsive noise, a ringing or the like by correcting a maximum value and a minimum value respectively by the average value of picture data included respectively in a maximum level range and a minimum level range in a block and reassigning by the corrected dynamic range. CONSTITUTION:Since a television signal has a three dimensional correlation relating to a horizontal direction, vertical direction and a time direction, in a stationary part, the width in the change of the level of picture element data included in the same block is small. Accordingly, even when data from which the minimum level commonly used in the picture element data in the block is quantized by the number of quantized bits smaller than the number of original bits, the distortion in the quantization is hardly produced. The average value of the picture element data in the maximum level range and the minimum level range of the level ranges divided into the number corresponding to the number of quantized bits is detected and this average value is newly defined to be the maximum value and the minimum value to perform an encoding, thereby, the distortion in the block can be prevented according to the ringing, the improve noise or the like.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-efficiency encoding device that compresses the number of bits per pixel of image data such as a digital television signal.

[Summary of the invention]

In this invention, in a high-efficiency encoding device applied when transmitting a digital video signal, a television screen is divided into a large number of two-dimensional blocks or three-dimensional blocks, and the pixels in each block are narrowed due to the correlation of pixels within each block. The number of bits of pixel data in a block can be compressed by encoding that adapts to the dynamic range, and the maximum and minimum values of image data that are included in the maximum and minimum level ranges in the block, respectively, can be compressed. Since the signal is corrected by the average value and reallocated using the corrected dynamic range, block distortion due to impulsive noise, ringing, etc. is prevented from occurring.

[Conventional technology]

As video signal encoding methods, several high-efficiency encoding methods are known in which (1) the average number of bits per pixel or sampling frequency is reduced in order to narrow the transmission band.

The applicant of this application has determined a dynamic range defined by the maximum and minimum values of a plurality of pixels included in a two-dimensional block, as described in Japanese Patent Application No. 59-266407, and A high-efficiency encoding device that performs adaptive encoding is proposed. Furthermore, as described in Japanese Patent Application No. 60-232789, a high-efficiency encoding device performs encoding adapted to a dynamic range with respect to a three-dimensional block formed from pixels in areas included in each of a plurality of frames. is proposed. Furthermore, as described in Japanese Patent Application No. 60-268817, there is a variable length encoding method in which the number of bits changes depending on the dynamic range so that the maximum distortion caused when quantization is constant. Proposed.

FIG. 11 is used to explain the previously proposed encoding method adapted to the dynamic range. Dynamic range DR (difference between maximum value MAX and minimum value MIN)
is calculated for each two-dimensional block consisting of (8 lines x 8 pixels = 64 pixels), for example. Also, the lowest level (minimum value) within the block is removed from the input pixel data.

The pixel data after this minimum value has been removed is converted to a representative level. This quantization divides the detected dynamic range DR into four level ranges corresponding to a number of bits smaller than the original quantization bit number, for example, two bits, and detects the level range to which each pixel data in the block belongs. , is a process of generating a code signal indicating this level range.

In Figure 11, the dynamic range DR of the block is 4.
It is divided into level ranges AO to A3. Pixel data included in the minimum level range is encoded as (00), pixel data included in the level range At is encoded as (01), and pixel data included in the level range A2 is encoded as (1).
pixel data included in the maximum level range is encoded as (11). Therefore, the 8 bits of each pixel are compressed into 2 bits and transmitted.

On the receiving side, the received code signal is at the representative level/L/L.
Restored to O~L3. This representative level LOL3 is the center level of each of the level ranges AO to A3.

[Problem that the invention seeks to solve]

The above-mentioned encoding method adapted to the dynamic range has a problem in that block distortion occurs due to ringing and impulsive noise. FIG. 12 is a diagram for explaining the occurrence of block distortion. In FIG. 12, for ease of explanation, changes in data for a one-dimensional block, that is, a block formed by a predetermined number of samples in the horizontal direction, are represented as analog waveforms, and the restored values on the receiving side are shown as broken lines. It is shown.

As shown in Fig. 12, the image output of the video camera includes:
Small level ringing often occurs near edges where the level changes are steep. In the block that includes this ringing, the peak value of the ringing is the maximum value MAXI.
, and is encoded in accordance with the dynamic range DPI determined by the minimum value MINI. In the next block, since the ringing has converged, the maximum value MAX2 decreases, and encoding is performed in accordance with the dynamic range DR2 determined by the minimum value M I N 'l and the maximum value MAX2. Therefore, a difference in brightness level occurs between these two blocks, causing block distortion. Block distortion similarly occurs in the case of impulsive noise.

Although the difference in luminance level of the block distortion described above is small, it has a certain area, so there is a visually noticeable problem.

An object of the present invention is to provide a highly efficient encoding device in which block distortion is prevented from occurring in dynamic range-adapted encoding.

[Means for solving problems]

In this invention, the maximum value MAX of a plurality of pixel data and the minimum value of a plurality of pixel data included in a two-dimensional block of a digital image signal or a block consisting of N regions belonging to each of N temporally consecutive frames. A dynamic range detection circuit that calculates the MIN and detects the dynamic range DR for each block from the maximum value MAX and the minimum value MIN; Maximum level range A3 and minimum level range AO when divided into ranges
a circuit for extracting the input image data included in each of the input image data included in the maximum level range A3;
a circuit for forming a second average value MrN' of the input image data included in the average value MAX' and the minimum level range AO; a subtraction circuit that forms input data after value removal; a first average value MAX' and a second average value MIN';
a circuit that calculates a modified dynamic range DR'; and a quantization circuit that encodes the input data after the minimum value is removed in accordance with the modified dynamic range DR', which is smaller than the original quantization bit number. , a framing circuit for transmitting the modified dynamic range information and associated information and code signals.

[Effect]

Since the television signal has three-dimensional correlation in the horizontal direction, vertical direction, and time direction, the range of change in the level of pixel data included in the same block is small in the stationary portion. Therefore, even if data after removing the minimum level shared by pixel data in a block is quantized with a smaller number of quantization bits than the original number of quantization bits, almost no quantization distortion occurs.

In addition, the average value of pixel data included in the maximum level range and minimum level range among the level ranges divided into numbers corresponding to the number of quantization bits is detected, and this average value is used as the new maximum and minimum level range. By encoding as a value, block distortion due to ringing, impulse noise, etc. can be prevented.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. This description is given in the following order.

a. Configuration of the transmitting side; Configuration of the receiving side C; Block and blocking circuit d; Dynamic range detection circuit e; quantization circuit f; Modification a; Configuration of the transmitting side FIG. This shows the overall configuration of the (recording side). For example, a digital video signal in which l samples are quantized to 8 bits is input to the input terminal indicated by
A digital luminance signal) is input. This digital video signal is supplied to the blocking circuit 2.

The blocking circuit 2 converts the input digital video signal into continuous signals for each two-dimensional block, which is a unit of encoding. In this embodiment, the l block has a size of (8 lines x 8 pixels - 64 pixels). The output signal of the blocking circuit 2 is supplied to a dynamic range detection circuit 3 and a delay circuit 4. The dynamic range detection circuit 3 detects a minimum value M I N and a maximum value M for each block.
Detect AX and dynamic range DR. Pixel data from the delay circuit 4 is supplied to a comparison circuit 5 and a comparison circuit 6.

The dynamic range DR from the dynamic range detection circuit 3 is supplied to a shift circuit 7 , the maximum value M A X is supplied to a subtraction circuit 8 , and the minimum value MIN is supplied to an addition circuit 9 . The shift circuit 7 is used to perform division of A when the number of quantization bits is 2 bits.
One level range value of the level range divided from is obtained. The output signal of this shift circuit 7 is supplied to a subtraction circuit 8 and an addition circuit 9. Therefore, from the subtraction circuit 8,
The lower threshold of the maximum level range is obtained, and the adder circuit 9 obtains the upper threshold of the minimum level range. The output signal of these subtraction circuit 8 and the output signal of addition circuit 9 are supplied to comparison circuits 5 and 6, respectively.

The output signal of the comparator circuit 5 is supplied to an AND gate 10,
The output signal of comparison circuit 6 is supplied to AND gate ll. Input data from the delay circuit 4 is supplied to AND gates 10 and 11. The output signal of the comparison circuit 5 becomes high level when the input data is larger than the threshold value, and therefore, the pixel data of the input data included in the maximum level range is extracted at the output terminal of the AND gate 10.

The output signal of the comparator circuit 6 becomes high level when the input data is smaller than the threshold value, and therefore, the AND gate II
Pixel data of input data included in the minimum level range is extracted to the output terminal of .

The output signal of the AND gate 10 is supplied to the average value forming circuit 12, and the output signal of the AND gate 11 is supplied to the average value forming circuit 13. These average value forming circuits 12 and 1
3 calculates the average value for each block, and terminal 14
, a reset signal for each block is supplied to average value forming circuits 12 and 13 . From the average value forming circuit 12,
Average value MAX' of pixel data belonging to the maximum level range
is obtained, and the average value forming circuit 13 obtains the average value M I N ' of the pixel data belonging to the minimum level range. The average value MIN'' is subtracted from the average value MAX' by the circuit 15.
The dynamic range DR is subtracted from the subtraction circuit 15.
' is obtained.

Further, the average value MIN' is supplied to the subtraction circuit 16, and the average value MIN' is subtracted from the input data via the delay circuit 17 in the subtraction circuit 16, and the data P after the minimum value is removed is
A DI is formed. This data PDI and the modified dynamic range DR' are supplied to the quantization circuit 7.

The quantization circuit 18 quantizes the pixel data PDI in accordance with the dynamic range DR' and generates a code signal DT.

Corrected dynamic range DR', average value MIN'
and code signal DT are supplied to the framing circuit 19. As shown in FIG. 2, the framing circuit 19 forms serial data consisting of a dynamic range DR', an average value M I N ', and one block of data. The data of l block has the number of bits (2 bits x 64). This serial data is encoded with an error correction code and a synchronization signal is added to form transmission data. This transmission data is taken out to the output terminal 20.

b. Receiving side configuration FIG. 3 shows the configuration on the receiving (or reproducing) side.

The received data from the input terminal 35 is sent to the frame decomposition circuit 3.
6. The frame decomposition circuit 36 separates the code signal DT and additional codes DR' and MIN', and also performs error correction processing.

The code signal DT is supplied to the decoding circuit 37, and the dynamic range DR' is supplied to the decoding circuit 37. Further, the average value MIN' is supplied to the adder circuit 38. The output signal of the decoding circuit 37 is supplied to the addition circuit 38, and the output signal of the addition circuit 38 is supplied to the block decomposition circuit 39. The decoding circuit 37 performs processing opposite to that of the quantization circuit 18 on the transmitting side. That is, the 2-bit code signal is decoded to a representative level, and this data and the 8-bit average value M
IN is added by the adder circuit 38, and the original pixel data is decoded.

The output signal of the adder circuit 38 is supplied to a block decomposition circuit 39. The block decomposition circuit 39 is a circuit for converting the decoded data in the order of blocks into the same order as the scanning of the television signal, contrary to the blocking circuit 2 on the transmitting side. A decoded video signal is obtained at the output terminal 40 of the block decomposition circuit 39.

C. Blocks and Blocking Circuits Blocks, which are units of encoding, will be explained with reference to FIG. In this example, by dividing the screen of the l field, as shown in Fig. 4 (8 lines x 8 pixels)
A large number of two-dimensional blocks are formed. In Figure 3,
Solid lines indicate lines for odd fields, and dashed lines indicate lines for even fields. Unlike this example, the present invention can also be applied to a three-dimensional block composed of N two-dimensional regions belonging to each of N temporally consecutive frames.

The blocking circuit 2 will be explained with reference to FIGS. 5, 6, and 7. For the sake of simplicity, it is assumed that the L field screen has a configuration of (4 lines x 8 pixels) as shown in Figure 6, and this screen is divided into two vertically and horizontally as shown by the broken line. A case will be explained in which 8 blocks (2 lines x 2 pixels) are formed.

In FIG. 5, input data A consisting of four lines (The to Thj) as shown in FIG. 7A is supplied to an input terminal indicated by 21, and input data A is supplied to an input terminal indicated by 22.
A sampling clock B (FIG. 7B) synchronized with is supplied. Numbers (1 to 8) indicate sample data of line T he, numbers (11 to 18) indicate sample data of line Th, and numbers (21 to 8) indicate sample data of line Th, respectively.
28) indicates sample data of line Th, and numbers (31 to 38) indicate sample data of line Th, respectively. Delay circuit 23 whose input data A has a delay amount of Th
and is supplied to the delay circuit 24 with a delay amount of 27 seconds (Ts: sampling period). Also, sampling clock B
is supplied to the A frequency dividing circuit 27.

The output signal C (FIG. 7C) of the delay circuit 24 is supplied to one input terminal of the switch circuits 25 and 26, respectively, and the output signal D (FIG. 7D) of the delay circuit 23 is supplied to the other input terminal of the switch circuits 25 and 26. are supplied to the input terminals of the respective input terminals. The switch circuit 25 is controlled by the output signal E (Fig. 7E) of the frequency dividing circuit 27, and the switch circuit 26 is controlled by the pulse signal E.
is controlled by the pulse signal inverted by the inverter 28.The switch circuits 25 and 26
The input signal (C or D) is selected alternately every time. The output signal F from the switch circuit 25 is shown in FIG. 7F, and the output signal G from the switch circuit 26 is shown in FIG. 7G.

The output signal F of the switch circuit 25 is connected to the first input terminal of the switch circuit 29 and the delay circuit 30 has a delay amount of 4Ts.
supplied to The output signal G of the switch circuit 26 is 2Ts
The signal is supplied to the delay circuit 31 having a delay amount of . The output signal H of the delay circuit 30 (H in FIG. 7) is supplied to the third input terminal of the switch circuit 29. Output signal of delay circuit 31■
(FIG. 7 1) is supplied to the second input terminal of the switch circuit 29 and the delay circuit 32 having a delay amount of 47 seconds.

The output signal J (FIG. 7J) of the delay circuit 32 is supplied to the fourth input terminal of the switch circuit 29.

The output signal of the frequency divider 27 is supplied to the frequency divider 33, and an output signal K (K in FIG. 7) is formed. The switch circuit 29 is controlled by this signal K, and the first . Second. The third and fourth input terminals are sequentially selected.

Therefore, the signal taken out from the switch circuit 29 to the output terminal 34 is as shown in the sixth diagram. That is, the order of each field of data is converted to the order of each block (for example, 1-2-11-12). Of course, the actual number of pixels in the l field is much larger than in the example shown in FIG. 6, but it is converted into the block-by-block order shown in FIG. 4 by scan conversion similar to that described above.

d. Dynamic range detection circuit FIG. 8 shows the configuration of an example of the dynamic range detection circuit 3. As described above, the image data of the area that needs to be encoded is sequentially supplied to the input terminal 41 from the blocking circuit 2 for every l block. Pixel data from this input terminal 41 is supplied to a selection circuit 42 and a selection circuit 43. The - selection circuit 42 selects and outputs the one with a higher level between the pixel data of the input digital video signal and the output data of the latch 44. The other selection circuit 43 selects and outputs the one with a smaller level between the pixel data of the input digital video signal and the output data of the latch 45.

The output data of the selection circuit 42 is supplied to the subtraction circuit 46 and is also taken into the latch 44 . The output data of the selection circuit 43 is supplied to the subtraction circuit 46 and the latch 48, and is also taken into the latch 45. Latches 44 and 4
5, a launch pulse is supplied from the control section 49. The control unit 49 is supplied from a terminal 50 with timing signals such as a sampling clock and a synchronization signal that are synchronized with the input digital video signal. The control unit 49 has a latch 44°4.
5. Supply latch pulses at predetermined timings to 47, 48, and 53.

At the beginning of each block, the contents of latches 44 and 45 are initialized. All on latch 44.

Data of 0 is initialized, and the latch 45 contains all l.
The data of ゛ is initialized. Among the sequentially supplied pixel data of the same block, the maximum level is stored in the latch 44. Furthermore, among the pixel data of the same block that is sequentially supplied, the minimum level is stored in the latch 45.

When the maximum level and minimum level detection is completed for one block, the maximum level of the block appears at the output of the selection circuit 42. The output signal of this selection circuit 42 is supplied to a latch 53, and an output terminal 5 derived from the latch 53
4, the maximum level MAX is taken out. On the other hand, the output of the selection circuit 43 produces the minimum level of the block. When the detection for l block is completed, latches 44 and 4
5 is reinitialized.

The dynamic range DR of each block is obtained from the output of the subtraction circuit 46 by subtracting the maximum level MAX from the selection circuit 42 and the minimum level MIN from the selection circuit 43. These dynamic range DR and minimum level MIN are controlled by the latch pulse from the control block 49.
latches 47 and 48, respectively. The dynamic range DR of each block is obtained at the output terminal 51 of the latch 47, and the minimum value MIN of each block is obtained at the output terminal 52 of the latch 48.

e. Quantization circuit The quantization circuit 18 performs fixed length encoding adapted to the dynamic range DR. FIG. 9 shows an example of the quantization circuit 18. In FIG. 9, the ROM indicated by 55 stores a data conversion table for converting the pixel data PD1 (8 bits) after minimum value removal into a compressed number of bits.

The dynamic range DR from the input terminal 56 and the pixel data PDI from the input terminal 57 are supplied to the ROM 55 as address signals.

In the ROM 55, a data conversion table is selected by the dynamic range DR, and a code signal D is output to the output terminal 58.
T is taken out.

Television signals within one block are horizontal.

Since there is a two-dimensional correlation in the vertical direction and a three-dimensional correlation in the time direction, the range of change in the level of pixel data included in the same block is small in the stationary portion. Therefore, the minimum level MI shared by pixel data within a block
Even if the dynamic range of the data DTI after N is removed is quantized using a smaller number of quantization bits than the original number of quantization bits, almost no quantization distortion occurs. By reducing the number of quantization bits, the data transmission bandwidth can be made narrower than the original one.

f. Modification In the above explanation, the code signal DT, dynamic range DR', and average (IMIN') are transmitted. However,
Instead of the dynamic range DR'', the average value MAX' or the quantization step may be transmitted as an additional code.

In addition, the average value information of the data included in the maximum level range or the data included in the minimum level range is the intermediate value when the most numerous level in a block or the pixel data in a block are arranged in descending order. You may also use

The present invention can be applied not only to coding adapted to a fixed-length dynamic range but also to coding adapted to a variable-length dynamic range. In the variable length method, the number of quantization bits (the number of divisions of the level range) changes depending on the dynamic range DR', so the configuration that determines the thresholds for the maximum and minimum level ranges is fixed length. It is more complicated than that. That is, it is necessary to find the number of quantization bits from the detected dynamic range DR, and to find the number of divisions from this number of quantization bits. Using this division number, a threshold value is determined in the same manner as in one embodiment of the present invention.

Furthermore, one block of data is processed by a circuit that combines a frame memory, a line delay circuit, and a sample delay circuit.
They may be taken out at the same time.

〔Effect of the invention〕

According to the present invention, it is possible to prevent block distortion from occurring in blocks containing ringing, impulsive noise, and the like. As shown in Fig. 12, even in blocks that include ringing (represented as one-dimensional blocks for simplicity), the maximum value MAX 1 is not the peak of ringing, but the pixels included in the maximum level range. The average value MAX' (indicated by a dashed line) of the data is replaced, and the minimum value MINI is similarly replaced by MIN'' (indicated by a dashed dotted line). Since reallocation is performed within the range DR', the restoration level becomes almost the same as the restoration level of adjacent blocks, and block distortion is prevented from occurring.

That is, the original dynamic range DR shown in FIG. 11 is modified according to the present invention to become a dynamic range DR'' as shown in FIG. 10, and this dynamic range DR' is divided into four level ranges AU' to A3'. In this case, the minimum level L as the restoration level on the receiving side
Q is made to match the average value MIN', and the maximum level L3 is made to be equal to the average value MAX''.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a route map showing the data structure, Fig. 3 is a block diagram showing the structure of the receiving side, and Fig. 4 is a unit of encoding processing. A route map used to explain a certain block, FIG. 5, FIG. 6, and FIG. 7 are respectively a route map for explaining a blocking circuit, a block diagram of an example of a blocking circuit, and a time chart for explaining the operation. Figure 8 is a block diagram of a dynamic range detection circuit, Figure 9 is a block diagram of an example of a quantization circuit, and Figure 10 is a block diagram of an example of a quantization circuit.
11 is a route diagram used to explain the present invention, FIG. 11 is a route diagram used to explain fixed length encoding adapted to dynamic range DR, and FIG. 12 is a waveform diagram used to explain the occurrence of block distortion. Explanation of main symbols in the drawings 1: Digital video signal input terminal, 2-blocking circuit, 3: Dynamic range detection circuit, 5.6: Comparison circuit, 7: Shift circuit, 12: Framing circuit, 18:
Quantization circuit. Agent Patent Attorney Tadashi Sugiura Figure 8: Amount of money and bribes Figure 9: Figure 11 Figure 10: I-O, Seller of amount Figure 12

Claims (1)

[Scope of Claims] The maximum value of a plurality of pixel data included in a two-dimensional block of a digital image signal or a block consisting of N regions belonging to each of N temporally consecutive frames and the maximum value of the plurality of pixel data. Means for determining the minimum value and detecting the dynamic range for each block from the maximum value and the minimum value, and dividing the dynamic range into a plurality of level ranges corresponding to a number of bits smaller than the original number of quantization bits. means for extracting input image data included in a maximum level range and a minimum level range, respectively; and a first input image data included in the maximum level range.
and means for forming a second average value of the input image data included in the average value of and the minimum level range, and subtracting the second average value from the value of the plurality of pixel data, means for forming input data; means for calculating a corrected dynamic range from the first average value and the second average value; , and means for encoding according to the modified dynamic range; and means for transmitting information related to the modified dynamic range and the code signal.