JP2832971B2 - Image data quantization circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quantization circuit for image data applied to compression-encode image data.

[Conventional technology]

Each pixel (sample) of digitized image data
Various encoding schemes have been proposed for reducing the number of bits of an image signal using correlation of image signals. The present applicant filed Japanese Patent Application Laid-Open
As described in Japanese Patent No. 144989, a high-efficiency coding apparatus that obtains a dynamic range that is a difference between a maximum value and a minimum value of a plurality of pixels included in a two-dimensional block, and performs encoding adapted to the dynamic range. Has been proposed.
Also, as described in Japanese Patent Application Laid-Open No. 62-92620, a high-efficiency coding apparatus that performs coding suitable for a dynamic range with respect to a three-dimensional block formed from pixels in a plurality of regions belonging to a plurality of frames. Has been proposed. Further, as described in Japanese Patent Application Laid-Open No. 62-128621, a variable length encoding method in which the number of bits changes according to a dynamic range so that the maximum distortion generated when quantization is performed is constant. Proposed.

Encoding adapted to these dynamic ranges (hereinafter abbreviated as ADRC) is based on the fact that, in a small area (block) obtained by dividing one screen, a bit per pixel is utilized by utilizing the fact that an image has a strong correlation. This is a highly efficient coding method that reduces the number. That is, the difference between the minimum value or the maximum value in the block and the level of each pixel is smaller than the original level, and this difference is quantized with a smaller number of bits (eg, 4 bits) than the original number of bits (eg, 8 bits). It is possible to do.

The present invention can be applied to the quantization of the level normalized by the maximum value or the minimum value in the above-mentioned ADRC or to the compression of the n-bit code obtained by the ADRC to m bits (n> m). . However, the present invention is not limited to ADRC, and can be applied to a quantization circuit that compresses an n-bit digital image signal into m bits.

As an example, in ADRC that performs 2-bit quantization, the dynamic range DR of a block, which is the difference between the maximum value MAX and the minimum value MIN, is equally divided into four level ranges, and the minimum value
The value of the pixel after MIN has been removed is represented by a 2-bit quantization code corresponding to the level range. On the decoding side, one of the central decoding representative levels I0 to I3 of each level range is decoded from the dynamic range DR and the quantization code,
The pixel data in the block is restored by adding the minimum value MIN to the decoded value.

FIG. 4 shows an example of quantization in ADRC. FIG. 4 shows an example of a one-dimensional ADRC in which one block is composed of six pixels that are continuous in the horizontal direction, and data indicated by white dots is a true value such as 4 bits or 8 bits of the pixels in the block. And has a horizontal change as indicated by the solid line 101.
In the case of encoding by the above-described 2-bit ADRC, a restoration level indicated by x is obtained on the decoding side, and a change in a signal indicated by a broken line 102 occurs in the restored image.

FIG. 5 shows another example of quantization in ADRC. Fifth
The figure shows a temporal change of a pixel at a position spatially corresponding to each of six consecutive frames in the time direction. For simplicity, it is assumed that each block including these six pixels has the same maximum value MAX and minimum value MIN. Data indicated by white dots is the true value of the pixel, and has a change in the time direction indicated by a solid line 103. In the case of encoding with the above 2-bit ADRC,
On the decoding side, a restoration level indicated by x is obtained, and a signal change indicated by a broken line 104 occurs in the restored image.

[Problems to be solved by the invention]

In conventional quantization, the original pixel level is replaced with the closest decoded representative level in order to reduce the quantization error and improve the S / N. However, even if quantitatively good, visually noticeable degradation may occur in the restored image. In the example shown in FIG. 4, the original gentle horizontal change 101 becomes a drastic change 102 after restoration, and visually noticeable noise (deterioration) occurs in the restored image. This noise is a kind of noise that is generated by reducing the snow noise generated in the television image received at the time of the weak electric field. Is sensitive to the differential characteristics of

As in the case of the spatial change, in the example shown in FIG.
04, and the same noise as described above occurs in the restored image.

As can be seen from FIG. 4 and FIG.
The data of two samples which are spatially adjacent to each other or spatially correspond to the original digital data and are temporally connected are different,
This is because one and the other are quantized into different 2-bit codes. That is, noise occurs when the data of the two samples is included above and below the boundary between two adjacent level regions.

Therefore, an object of the present invention is to provide an image data quantization circuit that can preserve the spatial change of the original image signal and visually improve the quality of the restored image even if a quantitative error increases. Is to provide.

Another object of the present invention is to quantize image data in which output data having a level corresponding to original data is obtained by performing quantization in consideration of visual characteristics only when there is a possibility that noise may occur. It is to provide a circuit.

[Means for solving the problem]

According to the present invention, in an image data quantization circuit for compressing digital data quantized by n bits into data of m bits (n> m), a code of upper m bits of the digital data of n bits is spatially adjacent. Different between two sample data or spatially corresponding two sample data that are temporally continuous, and one and the other of the two sample data take levels above and below the m-bit code change point, respectively. And a median filter to which a plurality of n-bit data or m-bit data including two-sample data is supplied and which selects intermediate data in the supplied data. When the state is detected by, the median buffer is used instead of the n-bit data or the m-bit data of one of the two sample data. By selecting the output data of the filter, the quantization circuit of the image data, characterized in that to obtain the data of m bits.

[Action]

The 4-bit quantized code DT in which ADRC encoding has occurred is compressed by a 2-bit code signal. Quantization code
The switch circuit 14 selects the DT and the output signal of the median filter to which the quantization code is supplied. Switch circuit
14 is controlled by the output signal of the detection circuit 18. Detection circuit 18
Are spatially adjacent two sample data or spatially corresponding two temporally continuous two sample data different from each other.
It is detected that each bit is included in a different level region in the case of bit quantization. At the time of this detection, the output signal of the median filter 17 is selectively output.

Since the median filter 17 changes a sudden level change into a gentle level change, it is possible to prevent visual deterioration of the image quality of the restored image. In addition, when there is no possibility that visually noticeable noise is generated in the restored image, quantitative quantization is performed, so that output data that is faithful in level to the original data can be obtained.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In FIG. 1, a digital video signal in which one pixel (one sample) is quantized to 8 bits is supplied to an input terminal indicated by 1, for example. The blocking circuit 2 converts the data order of the input digital video signal from the scanning order to the block order. For example, a screen of one frame is subdivided to form a block of (4 × 4 = 16 pixels).

The output signal of the blocking circuit 2 is supplied to the maximum value and minimum value detection circuit 3, and the maximum value, MAX, and minimum value MIN of the pixels included in each block are detected, respectively. The maximum value MAX and the minimum value MIN are supplied to the subtraction circuit 6, and a dynamic range DR, which is a difference between the maximum value MAX and the minimum value MIN, is calculated. The dynamic range DR and the minimum value MIN are taken out to output terminals 10 and 11 via delay circuits 8 and 9, respectively. Output terminals 10, 11, 21
Although not shown, a framing circuit is connected, and in the framing circuit, a dynamic range DR, a minimum value MIN, and a code signal compressed to 2 bits described later are converted into a signal form of a frame structure, and if necessary, Error correction coding is performed. Transmission data is obtained from the framing circuit.

The output signal of the blocking circuit 2 is supplied to the subtraction circuit 5 via the delay circuit 4. The delay circuit 4 delays the output signal of the blocking circuit 2 for a time required to detect the maximum value MAX and the minimum value MIN. The subtraction circuit 5 has a minimum value MI
N is supplied, and data after the minimum value is removed from the subtraction circuit 5 is obtained. The data normalized by the minimum value removal processing is supplied to the quantization circuit 7. The dynamic range DR is supplied to the quantization circuit 7 and the quantization circuit 7 outputs, for example, 4
The bit quantization code DT is extracted.

In the quantization circuit 7, the dynamic range DR is set to (2 ⁴ = 1
6) The value of the output data of the subtraction circuit 5 is divided by the quantization step which is the equally divided value, and the obtained quotient is truncated to form an integer (quantized code DT).
The quantization circuit 7 can be realized by a ROM or a division circuit.

The 4-bit data DT from the quantization circuit 7 is supplied to the sample delay circuit 12 and the median filter 17. The output signal of the sample delay circuit 12 is supplied to the sample delay circuit 13. The output signal of the sample delay circuit 12 is a switch circuit
It is supplied to one input terminal 15 of 14. Sample delay circuit
The output signals of 12 and 13 are supplied to a median filter 17 and a coincidence detection circuit 18. The median filter 17 is supplied with data of three consecutive samples in the horizontal direction, and the median filter 17 selectively outputs a sample having an intermediate level among the data of the three samples. The output signal of the median filter 17 is supplied to the other input terminal 16 of the switch circuit 14.

The output signal of the switch circuit 14 is the upper 2 bits selection circuit 20
, And a 2-bit code signal is extracted from an output terminal 21. In this embodiment, the original 8-bit image data is compressed to 4-bit data by ADRC, and further compressed to 2-bit data.

The switch circuit 14 is controlled by an output signal of the coincidence detection circuit 18. The coincidence detection circuit 18 determines that the coincidence becomes “1” (high level) when two consecutive sample data in the horizontal direction are different and these sample data take a level near the change point of the 2-bit code. Generate a signal. Other than the above, a signal which becomes “0” (low level) is generated. The output signal of the coincidence detection circuit 18 is generated for each sample data. When the coincidence signal ("1") is generated, the input terminal 16 of the switch circuit 14 is selected, and the output signal of the median filter 17 is output. The match signal is “0”,
That is, the input terminal 15 of the switch circuit 14 is selected by the mismatch signal, and the quantization code DT is output.

Two horizontally continuous sample data from the sample delay circuits 12 and 13 are supplied to the coincidence detection circuit 18.
The match detection circuit 18 is supplied with reference data from the ROM 19.

As shown in FIG. 2, a 4-bit quantization code DT (1111) corresponding to the maximum value MAX is formed by ADRC from a 4-bit quantization code DT (0000) corresponding to the minimum value MIN of the block. Upper 2 bits (MSB) of this 4-bit code
And the second MSB) are selected by the 2-bit selection circuit 12. Therefore, two-bit code signals (00) (01) (10) (11) are formed. In FIG. 2, the 4-bit code marked with * has values above and below the change point of the 2-bit code. If the code of two samples that are continuous in the horizontal direction is one of the upper and lower codes above and below the change point, as described at the beginning, deterioration occurs in which a gradual level change becomes a sharp change. Therefore, in this case, the output code of the median filter 17 is selected.

The ROM 19 generates 8-bit reference data consisting of codes marked with * above and below the change point. The reference data is as follows.

(00110100) (01000011) (01111000) (10000111) (10111100) (11001011) In the coincidence detection circuit 18, the two sample data (8 bits) from the sample delay circuits 12 and 13 and the above-mentioned six reference data are obtained. Be compared. This comparison can be done at once in parallel, or serially in time division.

FIG. 2B shows a quantization code DT (x
0, x1, x2, x3, x4,...). Among these quantization codes, x2 is (1100) and other x0, x1, x3,
x4 has a level of (1011). At the timing when the sample data x2 is generated at the output of the quantization circuit 7, the sample data x1 is generated at the output of the sample delay circuit 12, and the sample data x0 is generated at the output of the sample delay circuit 13. Therefore, the quantization code DT of three samples (x0, x1, x2) is supplied to the median filter 17, and the sample data of x0 and x1 are supplied to the coincidence detection circuit 18. Sample data x0
And x1 have the same level, so that the match detection circuit 18
Generates a mismatch signal (“0”) from the switch circuit.
At 14 the output signal of the sample delay circuit 12 (sample data x
1) is selected.

Next, at the timing when the sample data x3 occurs at the output of the quantization circuit 7, (x1, x
The quantization code DT of three samples (2, x3) is supplied, and the match detection circuit 18 is supplied with sample data of x1 and x2. Sample data x1 and x2 have different levels,
Since a different code signal is obtained when converted into a 2-bit code, the match detection circuit 18 outputs a match signal (“1”).
Is generated, and the output signal of the median filter 17 (a code having the same level as the sample data x1 and x2) is selected by the switch circuit 14.

Further, the quantization code DT of three samples (x2, x3, x4) is supplied to the median filter 17, and at the next timing, the output signal of the median filter 17 is selected by the switch circuit 14 in the same manner as described above. . By the above operation,
The 4-bit code signal obtained from the switch circuit 14 is
The level of sample data x2 is reduced from (1100) to (1011).
x0 to x4 are all (10).

FIG. 2C shows another example of the quantization code DT. In FIG. 2C, among six sample data consecutive in the horizontal direction, x0, x1, x4, and x5 have a level of (0011), and the other x2
And x3 have a level of (0100). Quantization circuit 7
The switch circuit 14 selects the sample data x1 at the timing when the sample data x2 is generated in the output of. At the timing when the next sample data x3 occurs at the output of the quantization circuit 7, the switch circuit 14 selects the output of the median filter 17. However, the median filter 17 has (x1,
Since x2 and x3) are supplied, the output of the median filter 17 is the same (0100) code as x2 and x3.

Further, at the timing when the next sample data x4 is generated at the output of the quantization circuit 7, since the sample data x2 and x3 have the same level, the switch circuit 14 sets the sample data x3.
Select At the next timing, the sample data
Since x3 and x4 are supplied to the match detection circuit 18, the switch circuit 14 selects the output of the median filter 17. However, the median filter 17 has sample data (x3,
x4, x5) is supplied, so that the output of the median filter 17 is a code of (0011) which is at the same level as x4 and x5.

Accordingly, in the example shown in FIG. 2C, the output code of the switch circuit 14 does not change from the original code signal, and the output 2-bit code signal has a steep level change, and no improvement can be expected. . In order to perform effective processing even in the case of data having the level relationship shown in FIG. 2C, a so-called 5-tap median filter to which five consecutive sample data are supplied may be used. Sample data having a unique level corresponding to the number of taps of the median filter can be processed.

FIG. 3 shows another embodiment of the present invention. The 4-bit quantization code DT formed by the ADRC is supplied to the upper 2-bit selection circuit 20 and the sample delay circuit 12B. An output signal of the upper two-bit selection circuit 20, a signal obtained by delaying the output signal by the sample delay circuit 12A, and the sample delay circuit 1
The signal delayed by 2A and 13A and the median filter 17
Supplied to The output signal of the median filter 17 and the output signal of the sample delay circuit 12A are selected by the switch circuit 14, and taken out to the output terminal 21.

The switch circuit 14 is controlled by an output signal of the coincidence detection circuit 18. The match detection circuit 18 is supplied with output signals of the sample delay circuits 12B and 13B.

The other embodiment shown in FIG. 3 is similar to the above-described embodiment except that a 4-bit code signal is converted into a 2-bit code signal before being supplied to the switch circuit 14 and the median filter 17. This is the same as one embodiment.

Unlike the above-described embodiment, three temporally continuous sample data, for example, three sample data having a time difference for each frame may be supplied to the median filter at spatially corresponding positions.

Also, the present invention provides a variable-length ADRC and three-dimensional block.
The present invention can be applied to a quantization circuit for other high efficiency codes such as ADRC.

〔The invention's effect〕

According to the present invention, it is possible to prevent visually conspicuous deterioration in which a gentle change of the original image data is transformed into a drastic change after decoding. Further, in the present invention, the processing by the median filter is performed only when there is a risk that the above-described degradation occurs, and in other cases, the processing is not performed through the median filter. It can be performed.

[Brief description of the drawings]

FIG. 1 is an overall block diagram of one embodiment of the present invention, and FIG.
FIG. 3 is a schematic diagram used for explaining a process of compressing a 4-bit code into 2 bits, FIG. 3 is a block diagram of another embodiment of the present invention, and FIGS. 4 and 5 are diagrams for explaining conventional quantization. FIG. Explanation of main reference numerals in the drawing 1: input terminal of digital video signal, 7: quantization circuit of ADRC, 14: switch circuit, 17: median filter, 18: coincidence detection circuit. 20: circuit for selecting upper 2 bits, 21: output terminal.

Claims (1)

(57) [Claims] An image data quantization circuit for compressing digital data quantized by n bits into data of m bits (n> m), wherein a code of upper m bits of the digital data of n bits is spatially Are different between two sample data adjacent to or spatially corresponding to each other and temporally continuous, and one and the other of these two sample data set the level above and below the change point of the m-bit code. A detection circuit that detects a state to be taken, and a median filter that is supplied with a plurality of n-bit data or m-bit data including the two-sample data and selects intermediate data in the supplied data. When the detection circuit detects the state,
M-bit data is obtained by selecting output data of the median filter in place of one of n-bit data or m-bit data of sample data, thereby obtaining m-bit data. .