JP2827319B2 - High efficiency coding apparatus and method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-efficiency encoding apparatus and method for compressing the number of bits per pixel of image data such as digital television signals.

[Conventional technology]

As a video signal encoding method, there are known several high-efficiency encoding methods for reducing the average number of bits per pixel or the sampling frequency for the purpose of narrowing the transmission band.

The present applicant obtains a dynamic range defined by the maximum value and the minimum value of a plurality of pixels included in a two-dimensional block as described in JP-A-61-144989, and adapts to this dynamic range. Has proposed a high-efficiency coding apparatus that performs the above coding. Also, JP-A-62-92
As described in Japanese Unexamined Patent Publication No. 620, a high-efficiency encoding apparatus has been proposed which performs encoding suitable for a dynamic range with respect to a three-dimensional block formed from pixels in an area included in each of a plurality of frames. Further, JP-A-62-2286
As described in Japanese Patent Publication No. 21, a variable-length encoding method has been proposed in which the number of bits is converted according to a dynamic range in which the maximum distortion generated when performing quantization is constant.

FIG. 6 is used to explain the previously proposed coding method (referred to as ADRC) adapted to the dynamic range. Dynamic range DR (maximum value MAX and minimum value M
IN difference) is calculated for each two-dimensional block composed of (8 lines × 8 pixels = 64 pixels), for example. Further, the minimum level (minimum value) in the block is removed from the input pixel data. The pixel data after the removal of the minimum value is converted to a representative level. This quantization divides the detected dynamic range DR into four level ranges A0 to A3 corresponding to a bit number smaller than the original quantization bit number, for example, 2 bits, and a level range to which each pixel data in the block belongs. Is detected, and a code signal indicating this level range is generated.

In FIG. 6, the dynamic range DR of the block is divided into four level ranges A0 to A3. Pixel data included in the minimum level range A0 is encoded as (00), pixel data included in the level range A1 is encoded as (01),
Pixel data included in the level range A2 is encoded as (10), and pixel data included in the maximum level range A3 is encoded as (11).
Is encoded. Therefore, the 8-bit data of each pixel is compressed to 2 bits and transmitted.

On the reception side, the received code signal is
Restored to L3. This representative level L0 to L3 is the level range
It is the middle level of each of A0 to A3.

The encoding method adapted to the above dynamic range is as follows.
There is a problem that block distortion occurs due to ringing and impulse noise. FIG. 7 is a diagram for explaining the occurrence of block distortion. In FIG. 7, for the sake of simplicity, a change in data for a one-dimensional block, that is, a block formed by a predetermined number of samples in the horizontal direction, is represented as an analog waveform, and the restored value on the receiving side is indicated by a broken line. It is shown.

In the imaging output of the video camera, as shown in FIG.
A small level of ringing often occurs near an edge where the level change is steep. In the block including the ringing, the peak value of the ringing is detected as the maximum value MAX1, and the coding is performed in accordance with the dynamic range DR1 determined by the minimum value MIN1. In the next block, the maximum value is MAX2 because the ringing has converged.
(MAX1> MAX2), and if the minimum value MIN2 of the next block is, for example, MIN1 = MIN2, the dynamic range DR2 = M
Encoding is performed according to AX2-MIN2 (<DR1). Therefore,
A difference in luminance level occurs between these two blocks, and block distortion occurs. In the case of impulsive noise, block distortion occurs for the same reason. Although the difference between the luminance levels of the block distortion described above is small, it has a certain area, and thus has a problem that it is visually noticeable.

In order to solve the above-mentioned problem of occurrence of block distortion due to ringing and impulsive noise, the present applicant has
As described in the specification of Japanese Patent Application No. 61-202118, there has been proposed a method of performing preprocessing on input data converted into a block structure. That is, the dynamic range is set to ADRC
The maximum level range when equally divided by the number of quantization bits (6th
Average value MA of input data values included in A3) in the figure
X 'and the average value MIN' of the input data included in the minimum level range (A0 in FIG. 6) are detected, and as shown in FIG. Are set to the restoration levels L3 and L0, respectively. Sixth
As shown in the figure, the quantization in which the representative levels L0 to L3 do not include the maximum value MAX and the minimum value MIN and are set to the median of each level range is referred to as non-edge matching, as shown in FIG. , The mean values MAX ′ and MIN ′ are called edge matching.

ADRC, which is preprocessed by the non-edge matching described above and quantized by the edge matching, in FIG. 7, even in a block including ringing, the maximum value is changed to the average value MAX ′ instead of the ringing peak. Similarly, the minimum value is changed to MIN '. Since the edge matching is quantized within the modified dynamic range DR 'determined by MAX' and MIN ', the difference between the restoration level and the restoration level of the adjacent block is reduced, and the occurrence of block distortion is prevented. .

ADRC coding adapted to the above dynamic range
Since the amount of data to be transmitted can be greatly reduced, it is suitable for application to a digital VTR. In particular, the variable length ADRC can increase the compression ratio. However, variable length ADRC is
Since the amount of transmission data varies depending on the content of the image, a digital VT that records a predetermined amount of data as one track
When a fixed-rate transmission line such as R is used, a buffering process is required.

As a buffering method of the variable length ADRC, the present applicant forms a cumulative dynamic range frequency distribution as described in Japanese Patent Application No. 61-257586,
A threshold value for determining the number of allocated bits prepared in advance is applied to this frequency distribution, and the amount of data generated during a predetermined period, for example, one frame period, is determined so that the generated data amount does not exceed the target value. Proposes what to control.

[Problems to be solved by the invention]

As described above, when preprocessing is performed by non-edge matching quantization and then variable-length ADRC is applied to ADRC that performs quantization by edge matching, the number of allocated bits based on the original dynamic range DR However, since a new dynamic range DR 'is transmitted to the receiving side, a problem arises due to the mismatch between the two.

That is, in order to control the amount of generated information, a frequency distribution table for a predetermined period, for example, one frame period of the dynamic range DR is formed, and this frequency distribution table is converted into a cumulative frequency distribution table. , T2, T3, T4 (T1 <T2 <
A threshold of T3 <T4) applies. In the case of (DR <T1), the allocated bit number n is set to 0 (that is, no quantization code is transmitted), and in the case of (T1 ≦ DR <T2), (n =
1), (n = 2) if (T2 ≦ DR <T3), (n = 3) if (T3 ≦ DR <T4),
(If T4 ≦ DRF, (n = 4).

As described above, (MAX'-MIN '= DR'), and quantization is performed based on the modified dynamic range DR ', and the dynamic range DR' is transmitted. For the dynamic range of a block, (T2 ≦ DR <T3)
If the relationship of (T2 ≦ DT ′ <T3) holds, (n = 2) on the encoder side, and (n = 2) on the decoder side.
2) and no problem occurs. However, since (DR> DR ′), when (T1 ≦ DR ′ <T2), the decoder incorrectly determines (n = 1) on the decoder side, causing a problem that a correct decoding operation is not performed.

Therefore, an object of the present invention is to provide a high dynamic range that is used for quantization and that is to be matched with the dynamic range used for buffering processing, thereby preventing the occurrence of mismatch between the encoder side and the decoder side. An object of the present invention is to provide an efficiency coding apparatus and method.

Another object of the present invention is to provide a high-efficiency coding that can effectively prevent ringing and block distortion due to impulse noise by matching the number of bits of non-edge matching quantization with the number of bits of edge matching quantization. It is to provide an apparatus and a method.

[Means for solving the problem]

The present invention relates to a maximum value MAX and a minimum value MIN of a plurality of pixel data contained in a two-dimensional block of a digital image signal or a block composed of N regions belonging to each of N frames continuous in time, and a difference between the maximum value MAX and the minimum value MIN. And a maximum value / minimum value detection circuit (3) for obtaining the dynamic range DR of each block, and the dynamic range information DR is ^expressed as 2 ¹ , 2 ² ,.
A circuit (9A-9D) for equally dividing by the number of (natural numbers of 2) and generating the divided values Δ4 to Δ1, and averaging the values of the input image data included in the level range of the divided values from the maximum value MAX and the minimum value MIN Then, a circuit (5A-5D, 6A-6D, 10A-10D) that obtains n new maximum values and minimum values and obtains n new dynamic ranges DR4 to DR1 from the new maximum values and minimum values. , 11A-11D, 12A-1
2D, 13A to 13D, 15A to 15D), a circuit (23A to 23D) for creating a frequency distribution table for each of the n new dynamic ranges DR4 to DR1 for a predetermined period, and n from the n frequency distribution tables A circuit (24, 25) that calculates the amount of generated information based on the pieces of threshold information T1 to T4 and sets the n pieces of threshold information T1 to T4 so that the amount of generated information falls within a predetermined data amount. , 26, 27) and n new dynamic ranges for each block and DR4
~ DR1 and the threshold information T1 ~ T4 set, the number of bits allocated to each block is obtained, and edge matching according to one new dynamic range corresponding to the number of allocated bits out of n new dynamic ranges A circuit that performs quantization on each pixel data of a block (18A-18B,
19, 21). Further, the present invention is a high-efficiency encoding method for encoding a digital image signal as described above.

[Action]

Since the television signal has a three-dimensional correlation in the horizontal direction, the vertical direction, and the time direction, in the stationary part, the variation width of the level of the pixel data included in the same block is small. Therefore, even if the data after removing the minimum level shared by the pixel data in the block is quantized with a smaller number of quantization bits than the original number of quantization bits,
Almost no quantization distortion occurs.

Further, an average value of pixel data included in a maximum level range defined by a maximum level MAX and a predetermined level lower than MAX and a minimum level defined by a minimum level MIN and a minimum level defined by a predetermined level higher than MIN is detected. . In this case, depending on the number of allocated bits n (4, 3, 2, 1), the quantization step width Δ4 to
Δ1 is obtained, and the average values MAX4 to MAX1 and MIN4 to MIN1 of the input pixel data existing in the maximum level range and the minimum level range defined by each quantization step width are detected. By performing quantization of edge matching using these average values as new maximum and minimum values, block distortion due to ringing, impulse noise, or the like is prevented.

The calculation of the amount of generated information and the setting of the thresholds T1 to T4 for reducing the amount of generated information to a predetermined amount or less are performed based on the dynamic ranges DR4 to DR1 used for the edge matching process. Mismatch between the decoder and the decoder side is prevented. In addition, since a new dynamic range is obtained from pixel data existing in a level range having a width corresponding to the number of allocated bits, even when the original dynamic range DR is small, block distortion can be effectively prevented.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings. This description is made in the following order.

a. Configuration on the transmission side b. Configuration on the reception side c. Modifications a. Configuration on the transmission side FIGS. 1A and 1B show the overall configuration of the transmission side (recording side) of the present invention. is there. Although FIG. 1A and FIG. 1B are connected to each other, they are drawn as separate figures because of the drawing area.

In FIG. 1A, a digital video signal (digital luminance signal) in which one sample is quantized to 8 bits, for example, is input to an input terminal indicated by 1. This digital video signal is supplied to the blocking circuit 2.

The blocking circuit 2 converts the input digital video signal into a continuous signal for each two-dimensional block which is a unit of encoding. In this embodiment, one block has a size of (8 lines × 8 pixels = 64 pixels) as shown in FIG. An output signal of the blocking circuit 2 is supplied to a maximum value / minimum value detection circuit 3 and a delay circuit 4. Maximum value,
The minimum value detection circuit 3 has a minimum value MIN and a maximum value M for each block.
Detect AX. The delay circuit 4 delays the input data by the time required for detecting the maximum value and the minimum value. Pixel data from the delay circuit 4 is supplied to the comparison circuits 5A, 5B, 5C, 5D and the comparison circuits 6A, 6B, 6C, 6D.

The maximum value MAX from the maximum value / minimum value detection circuit 3 is supplied to the subtraction circuits 7A, 7B, 7C and 7D, and the minimum value MIN is added to the addition circuit 8
A, 8B, 8C, 8D. These subtraction circuits 7A, 7
B, 7C, 7D and the adder circuits 8A, 8B, 8C, 8D have the non-edge matching quantum with the respective bit numbers of 4 bits, 3 bits, 2 bits, and 1 bit from the bit shift circuits 9A, 9B, 9C, 9D. Value of one quantization step (Δ4 =
1 / 16DR, Δ3 = 1 / 8DR, Δ2 = 1 / 4DR, Δ1 = 1 / 2DR) are supplied, respectively. The bit shift circuits 9A, 9B, 9C, 9D
In order to perform this division, the dynamic range DR is shifted by 4 bits, 3 bits, 2 bits, and 1 bit, respectively. From the subtraction circuits 7A, 7B, 7C, and 7D, (MAX
−Δ4, MAX−Δ3, MAX−Δ2, MAX−Δ1) are obtained, and the (MI) is obtained from the adders 8A, 8B, 8C, 8D.
N + Δ4, MIN + Δ3, MIN + Δ2, MIN + Δ1) are obtained respectively. The threshold value from these subtraction circuits 7A, 7B, 7C, 7D and the addition circuits 8A, 8B, 8C, 8D is
A, 5B, 5C, 5D and 6A, 6B, 6C, 6D, respectively.

The output signals of the comparison circuits 5A, 5B, 5C, 5D are AND gates 10A,
10B, 10C, and 10D, respectively, and the comparison circuits 6A, 6B, 6C, and 6
The output signal of D is supplied to AND gates 11A, 11B, 11C, and 11D, respectively. AND gates 10A, 10B, 10C, 10D and 11A, 11B, 1
Input data from the delay circuit 4 is supplied to 1C and 11D. The output signals of the comparison circuits 5A, 5B, 5C and 5D become high level when the input data is larger than the threshold value, and therefore,
The output terminals of the AND gates 10A, 10B, 10C, and 10D have (MAX to
MAX-Δ4) (MAX to MAX-Δ3) (MAX to MAX-Δ2) (M
Pixel data of input data included in the maximum level range of AX to MAX-Δ1) is respectively extracted. Comparison circuits 6A, 6B, 6
The output signals of C and 6D become high when the input data is smaller than the threshold value, and therefore, the AND gates 11A, 11B, 1
The output terminals of 1C and 11D are (MIN to MIN + Δ4) (MIN to MI
Pixel data of input data included in the minimum level range of (N + Δ3) (MIN to MIN + Δ2) (MIN to MIN + Δ1) is respectively extracted.

The output signals of the AND gates 10A, 10B, 10C, and 10D are supplied to the averaging circuits 12A, 12B, 12C, and 12C, and the AND gates 11A and 11C are provided.
The output signals of B, 11C and 11D are averaged by circuits 13A, 13B, 13C and 13
Supplied to D. These averaging circuits 12A, 12B, 12C, 12
C and 13A, 13B, 13C, and 13D calculate an average value for each block, and a reset signal of a block cycle is supplied from a terminal 14 to the averaging circuits 12A, 12B, 12C, 12C and 13A, 13B, 13C, and 1C.
Supplied in 3D. From the averaging circuit 12A, (MAX to MA
An average value MAX4 of pixel data belonging to the maximum level range of (X−Δ4) is obtained, and (M) is obtained from the averaging circuits 12B, 12C, and 12D.
AX to MAX-Δ3) (MAX to MAX-Δ2) (MAX to MAX-Δ
Average value MAX of pixel data belonging to the maximum level range of 1)
3, MAX2, MAX1 can be obtained respectively. Averaging circuits 13A, 13B, 1
From 3C and 13D, (MIN to MIN + Δ4) (MIN to MIN + Δ
3) Average values MIN4, MIN3, MIN2, of pixel data belonging to the minimum level range of (MIN to MIN + Δ2) (MIN to MIN + Δ1)
MIN1 can be obtained respectively. The corresponding average values are subtracted by the subtraction circuit 15.
A, 15B, 15C, 15D subtraction, subtraction circuit 15A, 15B, 15
The dynamic ranges DR4, DR3, DR2, and DR1 are obtained from C and 15D, respectively.

FIG. 3 is a diagram for explaining formation of the dynamic ranges DR4, DR3, DR2, and DR1. Bit shift circuit 9A
Is the original dynamic range DR as shown in FIG. 3A.
Is divided into 16 equal parts to form a quantization step width Δ4. The maximum level range (MAX-Δ4) and the minimum level range (MIN + Δ
4) the average value of the pixel data present in each of them is the maximum value MAX4
And MIN4. As shown in FIG. 3B, the bit shift circuit 9B forms a quantization step width Δ3 obtained by dividing the original dynamic range DR into eight equal parts, and (MAX−Δ3) and (MIN +
The average value of the pixel data existing in each of Δ3) is the maximum value MA
X3 and MIN3. Using the quantization step width Δ2 formed by the bit shift circuit 9C, the maximum values MAX2 and MIN2 are formed as shown in FIG. 3C. Further, using the quantization step width Δ1 formed by the bit shift circuit 9D, the maximum values MAX1 and MIN1 are formed as shown in FIG.

Further, as shown in FIG. 1B, the average values MIN4, MIN3, MI
N2 and MIN1 are supplied to subtraction circuits 16A, 16B, 16C and 16D, and average values MIN4 and MIN are obtained from the input data PD passed through the delay circuit 17.
3, MIN2 and MIN1 are respectively subtracted in the subtraction circuits 16A to 16D to form data after the minimum value is removed. This data and the modified dynamic range DR4 to DR1 are
18A, 18B, 18C and 18D, respectively. In this embodiment, a variable length ADRC in which the number of bits n allocated to quantization is 0 bit (a code signal is not transmitted), 1 bit, 2 bits, 3 bits, or 4 bits,
Edge matching quantization is performed. Quantization circuit 18A, 1
8B, 18C, and 18D are configured by, for example, a ROM. The output signals of these quantization circuits 18A, 18B, 18C and 18D are
Supplied to 19.

The code signal selected by the selector 19 is transmitted as an encoded output DT. Further, a selector 20 to which the dynamic ranges DR4 to DR1 and the minimum values MIN4 to MIN1 are supplied is provided. The selectors 19 and 20 are controlled by the bit number code Bn read from the ROM 21.

The allocated bit number n indicated by the bit number code Bn is
The bit number code Bn is determined for each block by the ROM 21, and is supplied to the quantization circuits 18A, 18B, 18C, and 18D. The variable-length ADRC performs efficient coding by reducing the number of allocated bits n in a block having a small dynamic range and increasing the number of allocated bits n in a block having a large dynamic range. That is, the number of bits n
Assuming that the threshold for determining is T1 to T4 (T1 <T2 <T3 <T4), a block of (DR1 <T1) does not transmit a code signal, and only information of a dynamic range DR1 is transmitted. The block of (T1 ≦ DR2 <T2) is (n = 1), the block of (T2 ≦ DR3 <T3) is (n = 2), and the block of (T3 ≦ DR4 <T4) is n = 3), and the block of (DR ≧ T4) is (n = 4).

The ROM 21 is supplied with respective comparison output signals of the comparison circuits 22A, 22B, 22C, and 22D as addresses. Comparison circuit 22A
Compares the dynamic range DR4 with the threshold T4, the comparison circuit 22B compares the dynamic range DR3 with the threshold T3, and the comparison circuit 22C compares the dynamic range DR2 with the threshold T4.
The comparison circuit 22D compares T2 with the dynamic range DR1 and the threshold T1. These comparison circuits (DRn
> Tn) (n = 0, 1, 2, 3 or 4), an output signal of "1" (high level) is generated.

Assuming that the comparison output signals of the comparison circuits 22A, 22B, 22C, and 22D are a, b, c, and d, the ROM 21 generates a 3-bit output signal Bn according to the following table.

When (Bn = 4), the selector 19 selects the output signal of the quantization circuit 18A, and the selector 20 selects DR4 and MIN4. When (Bn = 3), the selector 19 sets the quantization circuit 18B
And the selector 20 selects DR3 and MIN3. When (Bn = 2), the selector 19 sets the quantization circuit 18
The output signal of C is selected, and the selector 20 selects DR2 and MIN2. When (Bn = 1), the selector 19 sets the quantization circuit 18
The output signal of D is selected, and the selector 20 selects DR2 and MIN2. When (Bn = 0), the selector 19 does not output a code signal, and the selector 20 selectively outputs DR1 and MIN1.

A code signal DT selected by the selector 19, a dynamic range DRn selected by the selector 20, a parameter code Pi indicating a set of an average value MINn and a threshold are supplied to a framing circuit (not shown). In the framing circuit, an error correction code is encoded as necessary, and a synchronization signal is added. The output terminals of the framing circuit
The transmission data converted to serial data is extracted.

The variable-length ADRC can control the amount of generated information (so-called buffering) by changing the threshold values T1 to T4. Therefore, the variable length ADRC is useful for a transmission line that requires the amount of generated information per field or frame to be a predetermined value, for example, a digital VTR.

In this embodiment, in order to calculate the amount of generated information, as shown in FIG. 1A, frequency distribution table creation circuits 23A, 23B, 23
C and 23D are provided. The frequency distribution table creation circuit 23A is supplied with the dynamic range DR4 from the subtraction circuit 15A. The frequency distribution table creation circuits 23B, 23C, and 23D have a subtraction circuit 1
Dynamic ranges DR3, DR2, and DR1 are supplied from 5B, 15C, and 15D, respectively. The frequency distribution table creation circuit 23A is shown in FIG.
As shown in (2), a table corresponding to the frequency distribution graph with the dynamic range DR4 as the horizontal axis and the frequency as the vertical axis is created in the memory. The frequency distribution table creation circuits 23B, 23C, and 23D respectively create tables corresponding to the frequency distribution graphs shown in FIGS. 4B, 4C, and 4D in the memory. The frequency distribution is created every predetermined period such as one frame period and two frame periods. After the tables are created, thresholds T4, T3, T2, and T1 are supplied from the threshold table 24 to the frequency distribution table creating circuits 23A, 23B, 23C, and 23D, respectively.

In the threshold table 24, a set of thresholds (T1, T2, T
3, T4) are prepared in plurals, for example, 32 sets, and these sets of thresholds are used as parameter codes Pi (i = 0, 1, 2,..., 3).
1). The amount of generated information is set to decrease monotonically as the number i of the parameter code Pi increases. However, as the amount of generated information decreases, the image quality of the restored image deteriorates.

When the threshold value T1 is given to the frequency distribution table creating circuit 23A, the threshold value T4 indicated by a hatched area in FIG.
The number of blocks having a larger dynamic range DR4 is tabulated, and the tabulated value S4 is used as a frequency distribution table creation circuit 23A.
Output from This total value S4 is the total number of blocks to which 4 bits are allocated. Further, when the threshold value T3 is given to the frequency distribution table creation circuit 23B, as shown in FIG. 4B, the number of blocks having a dynamic range DR3 larger than T3 is totaled, and a total value S3 is generated. From the frequency distribution table creating circuits 23C and 23D, as shown in FIGS. 4C and 4D, total values S2 and S1 of blocks having dynamic ranges larger than the thresholds T2 and T1, respectively, are generated. In FIG. 4B, FIG. 4C, and FIG. 4D, the reason why the plurality of regions are distinguished by different oblique lines or dots is to indicate the regions divided by other thresholds.

The total value S4 is the total number of blocks having an allocated bit number of 4 bits, the total value S3 is the total number of blocks having an allocated bit number of 3 bits or more, and the total value S2 is the total number of blocks having an allocated bit number of 2 bits or more. The total value S1 is the total number of blocks and the total number of blocks is 1 or more. Therefore, a value obtained by multiplying the sum of these total values (S4 + S3 + S2 + S1) obtained by the addition circuit 26 by the number of pixels in one block (64 in this embodiment) is the total number of bits in the predetermined period. However, since the number of pixels is constant, the multiplication process of 64 is omitted in this embodiment.

The output signal of the addition circuit 26 is supplied to the comparison circuit 27,
Compared to the target value from 28. When the amount of generated information is equal to or smaller than the target value, it is determined that the amount of transmission data for a predetermined period does not exceed the capacity of the transmission path. The output signal of the comparison circuit 27 is supplied to the read control circuit 25. The read control circuit 25 controls reading of the threshold values T4 to T1 from the threshold table 24. Threshold T4
T1 are stored in the threshold table 24, for example, in 32 types. The set of thresholds is selectively read from the threshold table 24 according to the parameter code Pi.

In this case, reading is performed in order from the set of thresholds that increase the amount of generated information. It is determined that the set of thresholds when the amount of information generated from the adding circuit 26 becomes equal to or less than the target value is optimal. This set of threshold values is used by the comparison circuits 22A-2
2D (FIG. 1B). Further, a parameter code Pi indicating a set of threshold values is supplied to a framing circuit (not shown) and transmitted to a receiving side.

In FIG. 4, when calculating the aggregate values S4 to S1 of the number of blocks equal to or greater than the threshold value T4 to T1, the frequency distribution table is set to a cumulative type so that the aggregate value can be generated immediately when the threshold value is changed. Conversion is preferred. Taking the frequency distribution table of FIG. 4A as an example, by sequentially accumulating the frequencies from the maximum value of the dynamic range DR4 toward the minimum value,
The cumulative frequency distribution table shown in FIG. 4E is obtained. In this cumulative frequency distribution table, the cumulative frequency at the time when the threshold value T4 is given is nothing but the total value S4. Other aggregated values S3, S
2. Similarly, S1 can also be easily obtained from the cumulative frequency distribution table.

b. Configuration on the receiving side FIG. 5 shows the configuration on the receiving (or reproducing) side. The data received from the input terminal 31 is supplied to the frame decomposition circuit 32. The frame decomposition circuit 32 separates the code signal DT from the additional codes DRn, MINn, and Pi, and performs an error correction process.

The code signal DT is supplied to the decoding circuit 33, and the parameter code Pi and the dynamic range DRn are supplied to the decoding circuit 33. Further, the average value MINn is supplied to the adding circuit 34. The output signal of the decoding circuit 33 is supplied to the addition circuit 34, and the output signal of the addition circuit 34 is supplied to the block decomposition circuit 35. The decoding circuit 33 includes quantization circuits 18A and 18 on the transmission side.
The processing that is the reverse of the processing of B, 18C, and 18D is performed. That is, the code signal DT is decoded to the representative level, this data and the 8-bit average value MINn are added by the adder circuit 34, and the original pixel data is decoded. The decoding circuit 33 performs decoding using threshold values T4 to T1 indicated by the parameter code Pi.

The output signal of the addition circuit 34 is supplied to the block decomposition circuit 35. The block decomposition circuit 35 is a circuit for converting the restored data in the order of blocks into the same order as the scanning of the television signal, contrary to the blocking circuit 2 on the transmission side.
A decoded video signal is obtained at the output terminal 36 of the block decomposition circuit 35.

c. Modified example In the above description, the code signal DT and the dynamic range
DRn and the average value MINn are transmitted. However, instead of the dynamic range DRn as an additional code, the average value MAXn
Alternatively, the quantization step width may be transmitted.

〔The invention's effect〕

According to the present invention, it is possible to prevent occurrence of block distortion in a block including ringing, impulsive noise, and the like. According to the present invention, efficient encoding can be performed by the variable-length ADRC, and the dynamic range used for control of the amount of generated information and quantization is the same. Cause no problem.
When obtaining a new dynamic range DRn, the maximum levels MAXn and MINn are the average values of the pixel data existing in the maximum level range and the minimum level range according to the number of bits. Therefore, it is possible to effectively prevent the occurrence of block distortion as compared with another method in which the maximum level range and the minimum level range are fixed values irrespective of the number of allocated bits.

[Brief description of the drawings]

1A and 1B are block diagrams of an embodiment of the present invention, FIG. 2 is a schematic diagram of an example of a block, and FIG. 3 is a schematic diagram used to explain formation of a new dynamic range. , FIG. 4 is a schematic diagram used to explain a frequency distribution table for buffering, FIG. 5 is a block diagram showing an example of a configuration on the receiving side, and FIGS. 6, 7, and 8 are quantization diagrams. FIG. 4 is a schematic diagram used for describing an operation and occurrence of block distortion. Explanation of main symbols in the drawings 1: input terminal, 3: maximum value, minimum value detection circuit, 7A to 7D: subtraction circuit, 8A to 8D: addition circuit, 9A to 9D: bit shift circuit, 12A to 12D, 13A to 13D: averaging circuit, 18A to 18D: quantization circuit, 23A to 23D: frequency distribution table creation circuit, 24: threshold value table, 27: comparison circuit.

Claims (2)

(57) [Claims] A maximum value and a minimum value of a plurality of pixel data included in a two-dimensional block of a digital image signal or a block composed of N regions belonging to each of N frames that are temporally continuous, and a difference between these values. Means for determining a dynamic range of each block; means for equally ^{dividing the} dynamic range into a number of 2 ¹ , 2 ² ,... 2 ⁿ (n ≧ 2 natural numbers); By averaging the values of the input image data included in the level range of the division value from the maximum value and the minimum value, n new maximum values and minimum values are obtained, and n is calculated from the new maximum value and the minimum value. Means for obtaining a number of new dynamic ranges, means for creating a frequency distribution table for each of the n new dynamic ranges for a predetermined period, and n threshold information from the n frequency distribution tables On the basis of Means for calculating the amount of raw information and setting the n pieces of threshold information so that the amount of generated information falls within a predetermined amount of data; The number of bits allocated to each block is obtained from the threshold information obtained, and the edge matching quantization corresponding to the one new dynamic range corresponding to the number of allocated bits among the n new dynamic ranges is performed on the block. Means for applying to each pixel data. 2. The maximum value and the minimum value of a plurality of pixel data included in a two-dimensional block of a digital image signal or a block composed of N regions belonging to each of N frames that are temporally continuous, and their difference. Obtaining a dynamic range of each block; dividing the dynamic range into 2 ¹ , 2 ² ,... 2 ⁿ (n ≧ 2 natural numbers) equally; and generating a divided value; By averaging the values of the input image data included in the level range of the division value from the maximum value and the minimum value, n new maximum values and minimum values are obtained, and n is calculated from the new maximum value and the minimum value. Obtaining a new dynamic range; creating a frequency distribution table for each of the n new dynamic ranges for a predetermined period; and n thresholds from the n frequency distribution tables. Calculating the amount of generated information based on the information and setting the n pieces of threshold information so that the amount of generated information falls within a predetermined data amount; and the n new dynamic ranges of each block. And the number of bits allocated to each block from the set threshold information. The edge matching quantum corresponding to one of the new dynamic ranges corresponding to the number of allocated bits among the n new dynamic ranges. Applying the encoding to each pixel data of the block.