JP2595625B2 - Digital video signal receiving device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal receiving apparatus which has been compressed and transmitted at a low transmission rate.

[Summary of the Invention] The present invention does not transmit m-bit data for all pixels, but for higher-order n bits (m
> N), by decoding the pixel data transmitted with a large number of bits by referring to the pixel data transmitted with a small number of bits around the pixel data, This is to enable good decoding of a video signal.

[Conventional technology]

As one of the data compression methods for digital video signals, a technique called subsampling in space is known.

For example, as shown in FIG. 9, a method of transmitting only every other pixel data indicated by a mark in the horizontal and vertical directions and thinning out pixel data indicated by a mark is often used. In this way, when one pixel is represented by 8 bits, it is equivalent to transmitting all pixels with one bit by 4 bits, and transmission data can be compressed to 1/2.

In this case, at the time of transmission, the pixel data at the position of the thinned-out X mark becomes the grid pattern of 5 pixels at the position of the transmitted ○ mark. The reproduction is performed by interpolation using the pixel data and the pixel data indicated by the upper and lower circles.

[Problems to be solved by the invention]

However, in the case of in-space subsampling described above,
When the pixel data at the position of the cross is correlated with the pixel data at the top, bottom, left, and right, the pixel data at the position of the cross obtained by interpolation is good, but when there is no correlation, Becomes unreproducible. That is, for example, when the video signal suddenly changes in level as shown by the solid line in FIG. 10A, and when there is no correlation between the pixel data at the position of the cross and the pixel data at the position of the circle, Since there is no information on the pixel data at the position, the pixel data obtained by interpolation has the level indicated by the square in FIG. 10B, and cannot be reproduced. This means that, for example, an image of a line segment consisting only of pixel data at the position of the mark x as shown by the solid line a in FIG. 9 cannot be reproduced.

This is because the pixel data at the position of the mark x was thinned out by spatial compression called subsampling in space, and information in the level direction of the pixel data at the position of the mark x disappeared, and the balance in the level direction was lost. Due to that.

Therefore, the inventor of the present application has conceived of a novel transmission device that can improve this point and perform well-balanced compression.

FIG. 11 shows an embodiment of the new transmission device, and FIG.
The figure is a timing chart for the explanation.

In FIG. 11, the video signal through the input terminal (1) is
The signal is supplied to the A / D converter (2), is sampled by the clock CLK ₁ (FIG. 12A) through the terminal (3), and the sampled value is 5-bit digital data (pixel data) in this example. . The 5-bit pixel data DA from the A / D converter (2) is supplied to one input terminal of the selection circuit (4) as it is and supplied to the upper 3-bit selection circuit (5). Only the upper three bits of the data DA are obtained, and the three bits of data are supplied to the other input terminal of the selection circuit (4). The selection circuit (4) is supplied with the selection signal SEL from the selection signal forming circuit (5). The selection circuit (4) outputs pixel data of 5 bits and data of 3 bits. It is obtained in such a way that both the horizontal and vertical directions are alternated and it is transmitted via the output terminal (11).

FIG. 13 is an explanatory diagram of this output pixel data. A circle indicates 5-bit pixel data, and a triangle indicates 3-bit pixel data. Pixels have the same number of bits.

In this example, the selection signal forming circuit (5) includes flip-flops (6) and (7) and an exclusive OR circuit (8). Then, the flip-flop (6) is triggered by the clock CLK ₁ through the terminal (3), and the flip-flop (6) is synchronized with the horizontal synchronizing signal of the video signal through the terminal (9) (FIG. 12B). (6) is reset, and the clock CLK ₁
, And a signal PT (FIG. 12C) that is reset at the beginning of the horizontal section is obtained.
This signal PT is supplied to an exclusive OR circuit (8).

The signal SH triggers the flip-flop (7), and the signal FL of the field period through the terminal (10) resets the flip-flop (7), thereby inverting the state every horizontal section. LA (No.
12) is obtained, and this signal LA is supplied to an exclusive OR circuit (8). Therefore, the exclusive OR circuit (8) outputs the signal PT every horizontal section.
A signal in which the signal having the same phase and the signal PT being inverted alternately appear, that is, the selection signal SEL (FIG. 12E).
Is obtained.

For example, when the selection signal SEL is “1”, 5-bit pixel data is obtained from the selection circuit (4).
If bit pixel data is obtained, as described above, the output terminal (11) has 5-bit pixel data and 3-bit pixel data arranged on the screen in a 5-mesh grid as shown in FIG. Is obtained.

FIG. 14 is a block diagram of an example of the transmission data receiving apparatus. A 3-bit or 5-bit data is converted through an input terminal (12) into a conversion circuit (13) composed of, for example, a shift register (5 bits) and its peripheral circuits. Supplied to

On the other hand, the clock CLK ₂ on the receiving side of the pixel period is connected to the terminal (14).
Is supplied to the conversion control signal forming circuit (16) via the terminal (15), and a signal ID indicating the head position of the horizontal section and the head position of the field is supplied to the conversion control signal forming circuit (16) via the terminal (15). You.

In the case of transmitting a digital video signal, no horizontal synchronization signal or vertical synchronization signal is transmitted. However, since the number of pixel samples per horizontal line is determined according to the sampling frequency, the head of the data for the horizontal line can be determined, and the field can be identified from the number of horizontal lines, and the signal ID can be obtained from this. Also, a clock CLK ₂ by the signal ID and the clock CLK ₂ and the constant phase relationship can be synchronized with the pixel data.

Note that a signal ID for identifying these horizontal sections and fields may be transmitted together with the data.

From this signal ID and the clock CLK ₂ Prefecture, conversion control signals corresponding to the selection signal SEL of the transmission apparatus side is obtained.

The conversion circuit (13) outputs the 5-bit data as it is to the D / A converter (17) when the pixel data is 5 bits by this conversion control signal. Is shifted so that the 3-bit data becomes the upper 3 bits of the 5-bit shift register, and the data "0" is stored in the lower 2 bits.
Are filled into a total bit, which is output to the D / A converter (17). The clock CLK ₂ is supplied to the D / A converter (17), the 5-bit pixel data is returned to an analog signal, and a demodulated video signal is obtained at the output terminal (18).

FIG. 15 is a block diagram of another example of the transmission apparatus. In this example, the video signal through the input terminal (21) is converted into a 5-bit A / D converter (22) and a 3-bit A / D converter (23). ), And each pixel is sampled by a clock signal CLK passing through a terminal (24), and is converted into digital data. In this case, 5-bit pixel data is obtained from the A / D converter (22) and supplied to one input terminal of the selection circuit (25), and 3-bit data is supplied from the A / D converter (23). Pixel data is obtained and supplied to the other input terminal of the selection circuit (25). Then, this selection circuit (25), similar to the FIG. 11 example, the selection signal forming circuit from (26), pin (24) and through the clock signal CLK ₁ and the terminal (27) a horizontal period of the signal through The selection signal SEL formed from SH is supplied and the eleventh
In the same manner as in the example of FIG.
The 5-bit data and the 3-bit data are alternately extracted for each pixel from the selection circuit (25) such that the pixel data of the bit is at the position of the 5th grid, and transmitted through the output terminal (28). .

FIG. 16 is a block diagram of another example of a receiver for a transmitted digital video signal, in which transmission data is supplied to a selection circuit (32) through an input terminal (31).

On the other hand, the clock signal CLK ₂ and the signal
The ID is supplied to the timing signal generation circuit (35), from which a selection signal SEL 'for inverting the state for each pixel data is obtained and supplied to the selection circuit (32). The selection circuit (32) is selectively controlled by this selection signal SEL '),
Bit pixel data is stored in a 5-bit D / A converter (3
6), the 3-bit pixel data is supplied from the selection circuit (32) to the 3-bit D / A converter (37). Then, from the timing signal generation circuit (35),
Clock signal CK synchronized with the cycle of 5-bit pixel data
₅ and the clock signal CK synchronized with the cycle of the 3-bit pixel data in a state where the signal CK ₅ is inverted in phase.
₃ is obtained and the clock signal CK ₅ is used as a D / A converter (36)
The clock signal CK ₃ is the D / A converter (37), are supplied. Then, each D / A converter (36) and (3
In 7), the pixel data is converted into an analog signal, and a combined output signal, that is, a reproduced video signal is obtained at an output terminal (38).

The transmission data from the transmission device in FIG. 11 may be received and decoded by the reception device in FIG. 16,
Further, the transmission data from the transmission device in FIG. 15 may be received and decoded by the receiving device in FIG.

In the case of the example of FIG. 11 and the example of FIG. 15, the pixel data is transmitted by 5 bits and 3 bits. Therefore, when viewed on a spatially integrated screen, it is equivalent to transmitting all the pixel data by 4 bits. The resolution is substantially the same as that of the conventional example shown in FIG. 9 in which 8-bit pixel data is thinned out and transmitted to a 5-mesh grid.

However, in the case of the conventional example shown in FIG. 9, only the compression in the spatial direction is considered, and an image that cannot be reproduced occurs as described at the beginning because some pixels do not send any data. Not only compression in the spatial direction,
In consideration of compression in the level direction, pixel data is always transmitted, so there is no disadvantage as in the conventional example,
Good balance compression.

By the way, when such a digital video signal is received and decoded, when the analog video signal is reproduced by simply decoding and synthesizing the 5-bit pixel and the 3-bit pixel as they are as in the above-described example, Such a problem arises.

That is, since the number of bits of the pixel data of the mark “○” and the number of bits of the pixel data of the mark “△” are different, for example, even if the pixels have the same luminance level, the decoded luminance levels are different.

For example, even on a screen having a uniform brightness level, the brightness level of the pixel marked with a circle and the brightness level of the pixel marked with a triangle differ as shown by the waveform SY in FIG. Appears on the screen. This becomes more remarkable as the difference in the number of bits increases, which leads to deterioration in image quality.

SUMMARY OF THE INVENTION It is an object of the present invention to improve this drawback so that a good video signal can be reproduced.

[Means for solving the problem]

In the digital video signal receiving apparatus according to the present invention, when receiving the digital video signal from the above-described novel digital video signal transmission apparatus, a plurality of peripheral reference pixel data on the screen of the received pixel data are extracted. Extracting means (81) for performing, when any one of the plurality of reference data is pixel data having a bit number greater than the bit number of the received pixel data, the level of the reference pixel data is Reference pixel correction means for determining whether or not the level is within a level range, and when the value is within the range, the reference pixel data itself; (87
B) (87C) (87D) (87E) (88B) (88C) (88D) (88
E), and a correction means (89) for correcting the received pixel data using the output data of the reference pixel correction means.

[Action]

The decoded value of the pixel data transmitted with a large number of bits is
Since the correction is performed by referring to the pixel data transmitted with a small number of bits in the surrounding area, the difference in the decoding level due to the difference in the number of bits for each pixel is reduced, and the difference in the number of bits for each pixel is displayed on the screen. Appearing noise is less noticeable.

〔Example〕

The present inventors have proposed an adaptive dynamic range coding method (hereinafter, referred to as a compression method for digital video signals in the level direction).
The ADRC method was proposed (December 11, 1986, The Institute of Electronics, Communication Engineers, MR 86-43).

The ADRC method is an encoding method that uses a strong spatiotemporal correlation of a television signal.

That is, when an image is divided into blocks, each block often has only a small dynamic range due to local correlation. Therefore, in this ADRC method, the image is divided into blocks, and the dynamic range of each block is obtained.
By adaptively re-encoding the pixel data, each pixel data can be compressed to a smaller number of bits than the original number of bits.

As a method of dividing an image into blocks, division is performed only in a horizontal line direction (one-dimensional ADRC), division by a rectangular region in both horizontal and vertical directions (two-dimensional ADRC), and division considering a spatial region over a plurality of frames (three-dimensional ADRC) ADRC) has been proposed (for example, JP-A-61-144990, JP-A-61-144990).
144989 and JP-A-62-92620).

In three-dimensional ADRC, motion between two frames is detected for each block, and in still blocks, so-called frame dropping is performed without sending data of a subsequent frame, for example, so that more efficient encoding can be performed. However, in this case,
Each block requires a 1-bit motion information code, but in a still area, 1/2 data compression can be performed.

Allocation of the number of bits for each block during re-encoding is as follows:
In addition to the method of changing the quantization step width according to the dynamic range of each block as a constant value smaller than the number of bits of the original pixel data (hereinafter referred to as fixed-length ADRC; see the above-mentioned publication), the dynamic A method of changing the number of bits assigned to each block according to the size of the range (hereinafter referred to as variable length ADRC) has also been proposed (for example, see Japanese Patent Application Laid-Open No. 61-147689).

If the above-described novel transmission system is applied to the ADRC digital video signal transmission system that performs compression in the level direction as described above, it is possible to perform more balanced and more efficient compression.

Therefore, in the embodiments described below, a case where the present invention is applied to this ADRC system will be described as an example.

 First, the transmission device will be described.

FIG. 2 shows a configuration example in the case where the above-described new transmission system is applied to a fixed-length ADRC system.

That is, the video signal through the input terminal (41) is supplied to the A / D converter (42), each pixel for example, by the clock signal CLK ₁ from the terminal (43) is converted into 8-bit digital data. The digital data is supplied to a blocking circuit (44) and divided into two-dimensional small blocks of, for example, 3 lines × 6 pixels. Data for each block is supplied to a maximum / minimum value detection circuit (45), and a maximum value MAX and a minimum value MIN of pixel data in each block are obtained.

The data for each block from the blocking circuit (44)
The signal is supplied to the subtraction circuit (47) through the delay circuit (46) for the delay time in the detection circuit (45). The subtraction circuit (47) is supplied with the minimum value MIN within the block from the detection circuit (45), and subtracts the minimum value MIN within the block from each pixel data of this block to obtain difference data ΔDATA
Is obtained. Then, the difference data ΔDATA is supplied to the adaptive encoder (48).

On the other hand, the maximum value MA for each block from the detection circuit (45)
The data of X and the minimum value MIN are supplied to a subtraction circuit (49) as a dynamic range detection circuit, and MAX-MIN = DR
As a result, the intra-block dynamic range DR is detected, and the dynamic range DR is supplied to the adaptive encoder (48). In the adaptive encoder (48),
The number of bits BITS allocated in the block is selected according to the dynamic lens DR input thereto, and the difference pixel data ΔDATA from the subtraction circuit (47) is compressed to a bit number smaller than the original 8 bits, for example, 2 bits. The data is re-encoded into a BPL, and the data BPL is obtained from the adaptive encoder (48).

All pixel data in one block belong to the dynamic range DR from the minimum value MIN to the maximum value MAX.
In the adaptive encoder (48), the dynamic range DR in the block is divided according to the number of allocated bits BITS in the block (same for all blocks in fixed-length ADRC), and a code corresponding to each division level range is set. It determines to which level range the data belongs, and for each pixel, outputs a code corresponding to the level range to which it belongs to the output data BPL.
And

As an example of the encoding method in this case, two methods as shown in FIGS. 4 and 5 are proposed depending on which representative level is used as decoded data in each level range at the time of decoding. However, in the examples of both figures, the number of bits of the output data BPL is 2 bits.

In the example of FIG. 4, the dynamic range DR in the block is 2
^BITS = ^equally divided into 4 parts, and the median L0, L of each division level range
1, L2 and L3 are used as values at the time of decoding. With this method, quantization distortion can be reduced. This encoding method is called no edge matching, and is hereinafter abbreviated as NEM.

In the example of FIG. 5, the representative minimum level L0 is the minimum value MIN, and the representative maximum level L3 is the maximum value MAX. That is, in this case, the dynamic range is divided into (2 ^{BITS + 1} -2) = 6, the minimum value MIN is used as a representative level of the division level range on the minimum level side, and the division level on the maximum level side is used. The maximum value MAX is used as the representative level of the range. In the meantime, the division level is divided into two division levels, and the boundary levels between the two division levels are respectively represented by the representative levels L1 and L2.
And

According to this method, the pixel data having the minimum value MIN and the maximum value MAX always exist in one block, and therefore, there is an advantage that the number of encoded codes having an error of 0 can be increased. This encoding method is called edge matching,
Hereinafter, it is abbreviated as EM.

The output data BPL of the encoder (7) is defined by the following equation.

For NEM, For EM, (In the case of the fixed-length ADRC, the number of allocated bits BITS is constant.) The output data BPL thus obtained is supplied to the selection circuit (50). Then, the selection circuit (50) uses the selection signal SEL from the selection signal forming circuit (51) so that the number of bits in horizontal and vertical adjacent pixels is different from 2 bits and 1 bit in this example in the same manner as described above. Data is obtained. In the case of this example, the selection signal forming circuit (51)
Together with the clock signal CLK ₁ through the terminal (43) is supplied to the leading time point of the horizontal section to be used in the blocking from the blocking circuit (44), the horizontal direction of the block delimiter and vertical The information at the time of the break is supplied, and the selection signal SEL is formed based on the information.

One pixel obtained from the selection circuit (50) has 4 bits and 3 bits.
Bit data and dynamic range DR in the block
And the minimum value MIN in the block is the framing circuit (5
2) and the selection signal SEL from the circuit (51)
Is supplied to the framing circuit (52) to be framed, and data from the framing circuit (52) is transmitted through the output terminal (53).

In this case, ΔDATA is added to the adaptive encoder (48).
To a 2-bit output data BPL (for example, RO
M) and a circuit (for example, a ROM) for converting ΔDATA into 1-bit output data BPL.
The output BPL from the bit and 1-bit conversion circuit may be switched and output. In this case, the selection circuit (50) becomes unnecessary, and instead, a selection circuit for selecting one of the outputs of the 2-bit and 1-bit conversion circuits may be provided for the output of the adaptive encoder (48).

In this case, the additional code to be transmitted in addition to the data BPL may be the dynamic range DR and the maximum value MAX in the block, or the minimum value MIN and the maximum value MAX in the block.

FIG. 3 shows an example of a device for receiving data from the encoder shown in FIG.

That is, the transmitted data is supplied to the frame decomposing circuit (62) through the input terminal (61). Then, the image data from the frame decomposition circuit (62) is supplied to the adaptive decoder (63). The transmitted intra-block dynamic range DR is supplied from the frame decomposition circuit (62) to the adaptive decoder (63). Adaptive decoder (63)
Then, the number of allocated bits BITS according to the intra-block dynamic range DR is obtained, and adaptive decoding is performed using this information BITS.

The minimum value MIN in the block from the frame decomposition circuit (62) is supplied to the addition circuit (66).

In this case, the adaptive decoder (63) is provided with means I (for example, ROM) for adaptively decoding 2-bit data and means II (for example, ROM) for adaptively decoding 1-bit data. 2 for means I and II
Bits and one bit are provided.

A signal related to the selection signal of the selection circuit (50) on the encoder side is supplied from the frame decomposition circuit (62) to the timing signal formation circuit (64), and the two bits transmitted from the formation circuit (64) are transmitted. And a switching control signal synchronized with 1-bit pixel data. Then, this switching control signal is supplied to the adaptive decoder (63), and means I and means
II is switched, 2-bit pixel data and 1-bit pixel data are adaptively decoded, respectively, and 8-bit difference data ΔDATA ^* is obtained from the adaptive decoder (63).

In this case, in the adaptive decoder (63), the encoding code BPL (2 bits and 1 bit data) of each division level range as the input pixel data is obtained. As shown in FIG. 5, difference data ΔDATA ^* obtained by subtracting the minimum value MIN from each of the representative levels L0, L1, L2, and L3 is supplied to the addition circuit (65) to obtain decoded pixel data DATA ^* . . This decoded pixel data
Since DATA ^* is data for each block, the block is decomposed in the block decomposing circuit (66) to return to the original time-series pixel data.

The digital video signal from the block decomposition circuit (66) is supplied to an adjacent pixel adaptive decoding circuit (67). Further, the intra-block dynamic range DR from the frame decomposing circuit (62) is supplied to the block decomposing circuit (68) and is adjusted to the time series of the digital video signal. That is, the dynamic range DR of the block to which the pixel data belongs is assigned to each pixel data. The dynamic range DR from the block decomposition circuit (68) is supplied to the adjacent pixel adaptive decoding circuit (67).

The adjacent pixel adaptive decoding circuit (67) corrects the pixel data transmitted in 2 bits by referring to the pixel data transmitted in the surrounding 1 bit as described later.

In this example, pixel data transmitted by 1 bit is also corrected by referring to pixel data transmitted by surrounding 2 bits as described later.

Since the correction process for the 2-bit pixel data and the correction process for the 1-bit pixel data are switched in synchronization with the input pixel data of the adjacent pixel adaptive decoding circuit (67), the adjacent pixel adaptive decoding circuit (67) Is supplied with a conversion control signal from the timing signal forming circuit (64).

Each correction value from the adjacent pixel adaptive decoding circuit (67) is
Is supplied to the D / A converter (69), back into an analog signal in accordance with the clock CLK ₂ from the timing signal generation circuit (64), it is derived to the output terminal (70).

The operation performed by the decoder (63) can be represented by the following equation.

For NEM, For EM, However, when BITS = 0, NEM and EM are the same.

FIG. 1 shows an embodiment of an adjacent pixel adaptive decoding circuit (68), which will be described below with reference to FIGS.

In FIG. 1, the pixel data (8 bits) from the block decomposition circuit (66) is supplied to a peripheral pixel data extraction circuit (81). The extraction circuit (81) includes delay circuits (811) and (8) each comprising a memory of pixel data for one line.
It is composed of the series circuit of 12). In this case, the delay circuit (81
Considering the pixel position of the output pixel data SA in 1),
The input pixel data SB of the delay circuit (811) is the pixel data at the position directly above it, the output pixel data SC of the delay circuit (812) is the data of the pixel at the position immediately below it, and the delay circuit (811) ) Is the data of the pixel at the position on the left side of the output data SD, and the pixel data SE one pixel before the input data SA from the delay circuit (812) is on the right. This is the data of the pixel at the next position.

The dynamic range DR in the block that has been decomposed by the block decomposing circuit (68) is supplied to the corresponding dynamic range generating circuit (82) for each pixel data.
The corresponding dynamic range generating circuit (82) is composed of a serial circuit of delay circuits (821) and (822) each composed of a memory for one line, and a dynamic circuit corresponding to pixel data SA as output data of the delay circuit (821). Range DRA,
A dynamic range DRB corresponding to the pixel data SB as input data of the delay circuit (821), a dynamic range DRC corresponding to the pixel data SC as output data of the delay circuit (822), and a dynamic range DRC corresponding to the pixel data SC from the delay circuit (821). The dynamic range DRD corresponding to the pixel data SD as output data one pixel after the output data corresponds to the dynamic range DRE corresponding to the pixel data SE as the output data one pixel before the input data from the delay circuit (822). Are obtained respectively.

When the pixel data SA is 2-bit pixel data indicated by a circle, (83) indicates the upper limit value Uθ of the quantization level range.
In the upper limit lower limits forming circuit for obtaining a A ₂ and the lower limit value LθA _2, corresponding dynamic range DRA from pixel data SA and generator from the extraction circuit (81) (82) is supplied.

Also, (84) indicates pixel data SA, SB, SC, SD, SE indicated by a triangle (1).
Upper limit value lower limit value forming circuit for obtaining upper limit values UθA ₁ , UθB, UθC, UθD, UθE and lower limit values LθA ₁ , LθB, LθC, LθD, LθE of the respective quantization level ranges when it is bit pixel data. Then, the pixel data SA, S from the extraction circuit (81)
The corresponding dynamic ranges DRA, DRB, DRC, CRD, and DRE are supplied from B, SC, SD, SE and the generation circuit (82).

For example, formation of an upper limit value and a lower limit value when data BPL is encoded by the NEM method will be described.

Fig. 7 shows NEM and BITS = 2, and Fig. 8 shows BITS
= 1, and MIN = 0, MAX = 4. As apparent from FIGS. 7 and 8, the decoded values L ₀ , L
_{Since 1} , L ₂ , and L ₃ are the median values of each quantization level range, if the number of divisions of the dynamic range DR is x, the upper limit value and the lower limit value are the decoded value of the pixel, DR × 1 / 2x. The value k is obtained by adding or subtracting the value k. As described above, in the case of the NEM, the division number x is x = 1/2 ^BITS , so the value k for the pixel data of the bit number BITS is k = DR × 1/2 ^{BITS + 1} . Therefore, in the formation circuit (83), the corresponding dynamic range DRA for the 2-bit pixel data SA from the delay circuit (821) is supplied to the calculation circuit (831), and the calculation of DRA × 1/8 is performed. than this value k ₂ is obtained. This value k ₂ are supplied to the addition circuit (832) and the ALU (833). On the other hand, pixel data SA (this is a decoded value) from the extraction circuit (81) is supplied to the addition circuit (832) and the arithmetic circuit (833). Therefore, from the addition circuit (832), the upper limit value of the quantization level range for the pixel data SA of 2 bits Yushitaei ₂ is subtraction circuit (833)
, The lower limit LθA ₂ is obtained.

In the forming circuit (84), the arithmetic circuit (84) for reducing the corresponding dynamic range from the generating circuit (82) to 1/4.
1), the circuit composed of the the arithmetic output k ₁ addition circuit for performing addition and subtraction of each pixel data from the extraction circuit (81) and (842) and the subtraction circuit (843) is, pixel data SA, SB, S
Five circuits are provided corresponding to C, SD, and SE, and the upper limit value UθA ₁ , UθB, UθC, UθD, UθE and the lower limit value LθA ₁ ,
LθB, LθC, LθD, and LθE are obtained.

In FIG. 1, (85B) (85C) (85D) (85
E) and (86B), (86C), (86D), and (86E) are switch circuits that are switched in synchronization with the pixels marked with a circle and the pixels marked with a triangle by a control signal from the timing signal forming circuit (64). When SA is a pixel marked with a circle, the state is switched to the state shown in the figure. When pixel data SA is a pixel marked with a triangle, the state is switched to the state opposite to the state shown in the figure. These switch circuits (85B) (85C) (85D) (85E) and (86B) (86
C), (86D), and (86E) selectively obtain the pixel data and the information of the upper limit and the lower limit, respectively.

That is, when switching to the state shown in the figure, pixel data SA is obtained as pixel data from the switch circuits (85B) (85C) (85D) (85E), respectively, and the upper limit values UθB, UθC, UθD, UθE and Lower limit LθB, LθC, Lθ
D and LθE are obtained.

Further, the switch circuits (86B), (86C), (86D), and (86E) both provide the pixel data SA as the pixel data, the upper limit value UθA ₂ as the upper limit output, and the lower limit LθA ₂ as the lower limit output. can get.

Also, when switching to the opposite state from the state shown in the figure,
The pixel data from the switch circuit (85B) (85C) (85D ) (85E), the pixel data SB, SC, SD, with SE is respectively obtained, the upper limit Yushitaei ₁ is respectively obtained as information of the upper limit value, The lower limit value LθA ₁ is obtained as the lower limit information.

Further, Erushitaei ₁ switch circuit (86B) (86C) (86D ) pixel data SB as the pixel data output from the (86E), SC, SD, with SE is obtained respectively, Yushitaei ₁ as the upper limit value output, as the lower limit value the output Are obtained respectively.

(87B) (87C) (87D) (87E) are judgment circuits, these are switch circuits (85B) (85C) (85D) (85E)
Circuit that compares the pixel data output from the
1B) (871C) (871D) (871E), and a comparison circuit (872B) (872C) (872)
D) (872E) and switching signals SWB and SW of switching circuits (88B) (88C) (88D) (88E) to be described later from the outputs of these comparing circuits.
Switching signal forming circuit (873) for forming C, SWD and SWE respectively
B) (873C) (873D) (873E).

The switching circuits (88B), (88C), (88D), and (88E) are switched from the switching circuits (86B), (86C), (86D), and (86E) by switching signals from the determination circuits (87B), (87C), (87D), and (87E). One of the three data, that is, the pixel data, the upper limit value, and the lower limit value is selected, output, and supplied to the weighted average circuit (89).

In the weighted average circuit (89), each switching circuit (88B) (8
8C) (88D) (88E)
The average of these is calculated and output to the output terminal (90) as corrected pixel data.

Next, the adaptive decoding operation of the adjacent pixel adaptive decoding circuit (67) will be described.

First, a case will be described in which 2-bit pixel data indicated by a circle is corrected with reference to 1-bit pixel data indicated by a circle around the pixel data.

In the following description, in FIG. 6A, the decoded value of the pixel A transmitted by 2 bits at the position of the hatched circle in FIG. A case where correction is performed using c, d, and e will be taken as an example. In FIG. 6, thin lines indicate block division lines. In FIG. 6A, pixels A, b, and d belong to the same block, but pixels e and c belong to separate blocks.

Here, it is assumed that the pixel data SA from the extraction circuit (81) is 2-bit pixel A data indicated by a circle in FIG. 6A. Then, the pixel data SB, S from the extraction circuit (81)
In FIG. 6A, C, SD, and SE indicate 1 indicated by a triangle, respectively.
It becomes data of bit pixels b, c, d, and e. For convenience of explanation,
These are referred to as pixel data Sb, Sc, Sd, Se.

At this time, the switch circuit (85B) (85C) (85D) (85
(E) and (86B) (86C) (86D) (86E) are switched between the states shown in the figure.

Therefore, in the judgment circuit (87B), the comparison circuit (871B)
In (872B), the received pixel data SA is the data Sb of the pixel b.
Is compared with the upper limit value UθB and the lower limit value LθB of the quantization level range, the received pixel data SA is within the quantization level range of the data Sb of the pixel b, is larger than the upper limit value UθB, or is smaller than the lower limit value LθB. It is determined whether or not the switching signal is smaller than the switching signal SW based on the determination result.
B is obtained. When the received pixel data SA is within the quantization level range of the pixel data Sb from the switching circuit (88B) by the switching signal SWB, the received pixel data SA itself is obtained, and the received pixel data SA becomes the upper limit UθB If larger, the upper limit U of the quantization level range of the received pixel data SA
.theta.A ₂ is obtained, when receiving the pixel data SA is smaller than the lower limit LθB lower limit Erushitaei ₂ quantization level range of the received pixel data is obtained.

When receiving the pixel data SA is out of the quantization level range of the pixel data Sb, to obtain the upper limit Yushitaei ₂ or the lower limit Erushitaei ₂ quantization level range of the received pixel data SA, the pixels around the received pixel data SA This is because to obtain the correction value of b, the correction value is considered to be within the quantization level range of the received pixel data SA.

Similarly, in the determination circuits (87C), (87D), and (87E), the received pixel data SA is the upper limit value UθC, UθD, UθE and the lower limit value of the quantization level range of the data Sc, Sd, Se of the pixels c, d, e. LθC, L
θD, LθE, the received pixel data SA is within the quantization level range of the pixel data Sc, Sd, Se, or the upper limit U
θC, UθD, UθE, or lower limit LθC, LθD, LθE
It is determined whether they are smaller than each other, and the switching signals SWC, SWD, and SWE are obtained as the determination outputs. Then, the switching circuits (88C) (88D) (88
From E), when the received pixel data SA is within the quantization level range of the pixel data Sc, Sd, Se, the received pixel data SA itself is obtained, and the received pixel data SA becomes the upper limit value UθC, UθD, U
When θE larger than the upper limit Yushitaei ₂ quantization level range of the received pixel data SA is obtained, receiving pixel data SA lower limit LθC, LθD, when less than LθE receiving pixel data SA
Lower limit Erushitaei ₂ quantization level range can be obtained.

And the switching circuit (88B) (88C) thus obtained
The corrected pixel data from (88D) and (88E) is supplied to a weighted average circuit (89), and a weighted average is calculated, and the pixel data is calculated.
The correction value of SA is derived from the output terminal (90).

The weighting coefficient in the weighted average circuit (89) is
Referring to the distance and the like between the pixel A and the peripheral pixels b, c, d, and e, the pixel A
The value that is considered to be strongly correlated with is set to a value closer to 1.

In this case, if the decoded value of the pixel A is L ₃ = 3.5 in FIG. 7 and the decoded values of the surrounding pixels b, c, d, and e are all L ₁ = 3 in FIG. 8, the switching circuit (88B ) Since the outputs of (88C), (88D), and (88E) all become L ₃ = 3.5, the output of the weighted average circuit (89) has a value substantially equal to 3.5. If a simple average is taken, the correction values are exactly equal to 3.5.

Also, the decoded value of the pixel A is L ₃ = 3.5 in FIG. 7, the decoded values of the pixels b, c, and d are L ₁ = 3 in FIG. If L ₀ = 1 in FIG. 8, the switching value (L ₃ ) of the pixel A is obtained from the switching circuits (88B), (88C), and (88D).
3.5, but it obtained from the switching circuit (85E) in place of the decoded value 1, the lower limit value LθA ₂ = 3 can take a decoded value L ₃ in FIG. 7 can be obtained. The correction value of the decoded value of the pixel A at this time is (3.5 × 3 + 3) /4=3.375.

Next, the output pixel data SA from the extraction circuit (81)
Consider a case where the data is 1-bit pixel a data indicated by a hatched hatch in FIG. At this time, the pixel data SB, SC, SD, SE from the extraction circuit (81) are shown in FIG.
This is 2-bit data of C, D, and E. For convenience of the following description, the data of pixel a is Sa, and the data of pixels B, C, D, E are SB, S
C, SD, SE.

In this case, switch circuit (85B) (85C) (85D) (85
(E) and (86B) (86C) (86D) (86E) are switched to states opposite to those in the figure.

Therefore, each judgment circuit (87B) (87C) (87D) (87
In E), the comparison circuits (871B) (872B) and (871B)
C) According to (872C), (871D), (872D), (871E), and (872E), the level of each input pixel data SB, SC, SD, SE is within the quantization level range W of the pixel data Sa. range W or a higher level than the upper limit value Yushitaei ₁ of either lower than the lower limit value Erushitaei ₁ of this range W level is determined,
The switching signal forming circuit (873B),
Switching signals SWB and SW at (873C), (873D) and (873E)
C, SWD and SWE are formed.

The switching circuits (88B), (88C), (88D), and (88E) are controlled by the switching signals SWB, SWC, SWD, and SWE from the determination circuits (87B), (87C), (87D), and (87E), respectively. In the circuits (87B), (87C), (87D), and (87E), the level of the input pixel data SB, SC, SD, SE
When the input pixel data SB, SC, SD, SE are within the quantization level range W of a, and are outside the range W,
Moreover when the upper limit Yushitaei ₁ greater than the upper limit Yushitaei ₁
But also it is outside the range W, yet is smaller than the lower limit Erushitaei ₁ This lower limit Lθ are each switching circuit (88B)
(88C), (88D), and (88E).

The outputs of the switching circuits (88B), (88C), (88D), and (88E) are supplied to a weighted average circuit (86), respectively. In the weighted average circuit (86), the pixel a and the peripheral After weighting the outputs of the switching circuits (88B) (88C) (88D) (88E) in consideration of the strength of correlation with the pixels B, C, D, and E, the average is calculated and output. . Thus, the correction data of the pixel a is obtained from the weighted average circuit (86).

In this case, if the decoded value of the pixel a is L ₁ = 3 in FIG. 8 and the decoded values of the surrounding pixels B, C, D, and E are all L ₃ = 3.5 in FIG. 7, the switching circuit ( output of 88B) (88C) (88D) ( weighted average circuit the output also becomes all L ₃ of 88E) (86) is L ₃ =
It is almost equal to 3.5. If a simple average is taken, the correction values are exactly equal to 3.5.

The decoded value of the pixel a is L ₁ = 3 in FIG. 8, the decoded values of the pixels B, C, and D are L ₃ = 3.5 in FIG. When L ₀ = 0.5 in FIG. 8, the decoded value L ₃ = 3.5 from the switching circuits (88B), (88C), and (88D).
But although it obtained from the switching circuit (88E) in place of the decoded value 0.5, the lower limit value can take a decoded value L ₁ in FIG. 8 LθA ₁ = 2 is obtained. This is because it is considered that the decoded value of the pixel A is if L _1, the decoded value of the pixel A is present only in the quantization level range of the decoded value L _1. The correction value of the decoded value of pixel A at this time is (3.5 × 3 + 2) /4=3.1
It becomes 25.

Similarly, when the decoded value of the pixel A is L ₀ = 1 in FIG. 8 and any of the peripheral pixels B, C, D, and E is larger than the upper limit of the decoded value L ₀ , the decoded value of the pixel A is The largest of the values that exist as
That is, the upper limit value UθA ₁ of the quantization level range is the pixel B,
It is used instead of the decoded values of C, D, and E.

The above is the case of the NEM, but in the case of the EM, the arithmetic circuit (831) (841) in the upper limit and lower limit forming circuits (83) (84) has DR × 1 / (2 ^{BITS +} By performing the operation of ^1-2 ), the values k ₂ and k ₁ can be obtained.

In the case of edge matching, the decoded value is the maximum value MA
X, or when the minimum value MIN, the upper and lower limit values may be added or subtracted k ₁ or k ₂ to the decoded value, the upper limit value and the lower limit value, k ₁ or k ₂ by more than MAX, Or smaller than MIN. Therefore, when the decoded values are MAX and MIN in the circuits (83) and (84), MAX and MIN are output as the upper limit value and the lower limit value. At this time, MIN
Is the minimum value MIN in the block from the frame decomposition circuit (62)
Is obtained by the block decomposition, and MAX is obtained as the sum of the dynamic range DR obtained by the block decomposition and the minimum value MIN obtained by the block decomposition.

In the above example, data with a high number of bits and data with a low number of bits are transmitted in the form of a five-mesh grid as shown in FIG. 6, but in particular such a pixel arrangement is used. Such a consideration may not be taken into consideration, and the data may be transmitted by simply switching between data having a high bit number and data having a low bit number periodically.

Instead of changing the number of bits for each pixel, the number of bits may be changed for each of a plurality of pixels. Further, the number of bits of a plurality of pixels may be changed for one pixel or a plurality of pixels.

Further, the number of bits is not limited to two, but may be three or more, and these may be switched periodically.

In the above example, only the upper, lower, left, and right pixels are referred to as the peripheral pixels. However, if there is a pixel having a smaller bit and a larger bit in the diagonal direction, that pixel is also referred to as the peripheral pixel. The correction may be performed as shown in FIG. 1, and a weighted average may be performed including that pixel to obtain a correction value. In this case as well, taking into account the distance between the pixel in the oblique direction and the pixel of interest to be corrected, the pixels in the oblique direction are weighted and a weighted average is performed.

〔The invention's effect〕

According to the present invention, in receiving a digital video signal transmitted with compression balanced in both the spatial direction and the level direction, pixel data having a large number of bits are converted into pixels having a small number of bits around the pixel data. Since the decoding is performed with reference to the data, the noise on the screen due to the difference in the number of bits of the pixel data becomes inconspicuous, and a good received image can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a main part of the present invention, and FIG.
FIG. 1 is a block diagram of an example of a digital video signal transmission apparatus to which the present invention is applied, FIG. 3 is a block diagram of an embodiment of the present invention apparatus, and FIGS. 4 to 8 are diagrams of an embodiment of the present invention. FIG. 9 is a diagram for explaining a conventional transmission method, FIG. 10 is a diagram for explaining a conventional restoring operation on the receiving side, and FIG. 11 is an application of the present invention. Block diagram of an example of a transmission apparatus of a digital video signal, FIG. 12 is a timing chart for explaining the same, FIG. 13 is a diagram for explaining transmission pixel data, and FIG. 14 is a block diagram of an example of a receiving side thereof FIG. 15 is a block diagram of another example of the transmission apparatus, and FIG. 16 is a block diagram of an example of the receiving side. (81) is a peripheral pixel extraction circuit, (87B) (87C) (87D)
(87E) is a decision circuit, (83) and (84) are circuits for forming upper and lower limit values of a quantization level range, and (88B) (88C) (88
D) (88E) is a switching circuit, and (86) is a weighted average circuit.

Claims (1)

(57) [Claims] A selecting means for selecting one of a plurality of digital video signals which are digitized signals of the same video signal and have the same pixel period but different numbers of bits per pixel; A selection signal forming unit that forms a selection signal of the selection unit based on a signal related to the transmission unit; and a transmission unit that transmits an output of the selection unit. In a receiving apparatus for receiving a digital video signal transmitted from a digital video signal transmitting apparatus in which a digital video signal having a different number of bits is supplied to the transmitting means with a cycle according to a selection signal, Extracting means for extracting a plurality of peripheral reference pixel data on the screen of the above, wherein any one of the plurality of reference pixel data is the received pixel data. When the pixel data has a smaller number of bits than the number of bits of the reference pixel data, it is determined whether or not the level of the received pixel data is within the quantization level range of the reference pixel data. Reference pixel correction means for generating the upper limit value or lower limit value of the quantization level of the received pixel data when the pixel data itself is not within the range; and A receiving device for a digital video signal, comprising: correcting means for correcting.