JPS6359312B2 - - Google Patents

Description

[Detailed description of the invention]

(Field to which the invention pertains) The present invention relates to a motion compensated interframe encoding device that performs accurate prediction even for moving images and encodes them with high efficiency. (Prior Art) An interframe coding method is a method for highly efficient coding using interframe correlation of a video signal. The interframe coding method uses the pixel value of one frame before as the predicted value of the input video signal,
The prediction error is encoded and transmitted, and is based on the assumption that the movement of the image is small, making it suitable for situations such as video conferences where the movement of the subject is small. For this reason, if the motion of the image is large, the prediction will not be accurate, and the encoding efficiency will decrease. Motion compensated interframe coding improves prediction accuracy even when there is large motion. In this method, the input signal is set to a predetermined size, for example, 7 lines x
Divide into blocks of 7 pixels, and create blocks at the same position one frame before this block, or ±m lines vertically one frame before (for example, m = 1 to 6).
Then, blocks at positions shifted by ±n pixels (for example, n=1 to 6) in the horizontal direction are extracted, and the block with the smallest prediction error with the input signal is selected.
In order to express how far this block is shifted in the vertical and horizontal directions, vector information of this block is transmitted to the receiving side, and predictive coding is performed using pixel values within this block as predicted values. In this way, with conventional methods of this type, for example, if a meeting participant moves, the person's movement is compensated for, but the prediction is not accurate for background images such as walls that are projected later. This method has the disadvantage that a large amount of information is generated in the region, reducing encoding efficiency. In addition, there are also methods that use background memory for the background that appears after the movement of a person (for example,
157696), but this only stores the background and does not have the concept of sequentially correcting the contents of the background memory according to changes in the background to improve prediction accuracy. Additionally, there is currently no way to gradually compensate for changes in camera switching or conference room brightness, and unless you consciously rewrite the background memory,
The drawback was that it was not possible to respond. Furthermore, although it is important to predict the background that appears after movement, no suitable means has been found so far, and high-efficiency encoding has not been achieved. (Purpose of the Invention) In order to eliminate such drawbacks, the present invention installs a frame memory for the background and performs predictive coding on the background displayed after a person moves with high accuracy. will be explained in detail. (Structure and operation of the invention) FIG. 1 is a block diagram showing the structure of an embodiment of the invention, in which in the transmitting section, 1 is a video input terminal, 2 is a low-pass filter that limits the band of the input signal, 3 is a synchronous separation circuit that separates the synchronous signal from the output of the low-pass filter 2; 4 is a clock generation circuit that generates various clock information that is phase-synchronized with the output of the synchronous separation circuit 3 and outputs it to each circuit that requires a clock. , 5 is an A/D converter circuit that converts the analog video signal output from the low-pass filter 2 into a digital signal, and 6 is an A/D converter circuit before dividing the output of the A/D converter 5 into blocks of a predetermined size and outputting them. A processing circuit, 7 is a first storage circuit that stores the encoded/decoded processed image, 8 is a second storage circuit that stores the background image, and 9 is used for input signals supplied from the preprocessing circuit 6. an optimal prediction block detection circuit for detecting a block with the smallest prediction error from among the outputs of the first storage circuit 7 and the second storage circuit 8;
10 is a selection circuit that selects and outputs the signal of the corresponding block from the outputs of the first storage circuit 7 and the second storage circuit 8 based on the output of the optimal prediction block detection circuit 9; 11 is a preprocessing circuit; A subtraction circuit that subtracts the output of the selection circuit 10 as a predicted value from the output of the circuit 6 and outputs a prediction error, and 12 quantizes the output of the subtraction circuit 11 to output a quantized representative value. Prediction error processing circuit 13 is prediction error processing circuit 1
a code assignment circuit 14 for assigning a predetermined code to the output of the optimum prediction block detection circuit 9 and the output of the optimum prediction block detection circuit 9;
15 corresponds to the contents of the first storage circuit 7 and the second storage circuit 8 and the receiving section, respectively. an error control information sending circuit that sends out information for matching the contents of the storage circuit; 16 an encoding control information generating circuit that generates information representing the encoding control state;
17 is a multiplexing circuit which takes timing with the output of the clock generation circuit 4 and multiplexes the outputs of the code allocation circuit 13, the address information generation circuit 14, the error control information transmission circuit 15 and the encoded control information generation circuit 16 in a time division manner; 18 is a buffer memory that temporarily stores the output of the multiplex circuit 17 and reads it out using the output clock of the transmission clock generation circuit 19; 20 is a frame configuration circuit that configures a transmission frame for the output of the buffer memory 18; and 21 is a frame configuration circuit that stores the output of the frame configuration circuit 20. A digital interface converts the transmission path code into, for example, an AMI code and sends it out to the digital transmission path via the data output terminal 22, and 23 is a locally decoded signal obtained by adding the output of the prediction error processing circuit 12 and the output of the selection circuit 10. an adder circuit that outputs 24
25 is a background detection circuit that detects the background of an image based on the output of the prediction error processing circuit 12, and 25 is the addition circuit 2.
This is a storage control circuit that receives the outputs of the second storage circuit 3 and the second storage circuit 8, corrects the pixel values of the area designated by the output of the background detection circuit 24, and outputs the corrected pixel values. On the receiving side, 26 is a data input terminal, 27
28 is a digital interface that receives an input transmission path code, such as an AMI code, and converts it into a signal that can be decoded, such as a unipolar signal; 28 receives the output of the digital interface 27 and regenerates the transmission path clock; A clock regeneration circuit that regenerates various clock signals necessary for decoding, 2
9 is a frame disassembly circuit for disassembling transmission frames from the output of the digital interface 27;
0 temporarily stores the output of the frame decomposition circuit 29,
A buffer memory 31 reads out stored data according to the decoding speed, and a word identification circuit 3 identifies address information from the output of the buffer memory 30.
3, an address information identification circuit 32 identifies error control information from the output of the buffer memory 30, and supplies this information to a third storage circuit 35, a storage control circuit 40, and a first storage circuit 7 of the transmitting section, which will be described later. , a control information identification circuit that supplies the storage control circuit 25 and the error control information sending circuit 15, identifies control information for decoding, and supplies it to each circuit necessary for decoding;
33 is a word identification circuit 34 that identifies information representing the optimal prediction block from the output of the buffer memory 30 and outputs it to a selection circuit 37 to be described later, and also identifies a word representing a prediction error and outputs it to the prediction error decoding circuit 34; is a prediction error decoding circuit that receives the output of the word identification circuit 33 and decodes the prediction error;
35 is a third storage circuit that stores decoded images; 36 is a fourth storage circuit that stores background images;
37 is a third memory circuit 35 and a fourth memory circuit 36
A selection circuit 38 selects and outputs the signal of the block specified by the output of the word identification circuit 33 from among the outputs of the word identification circuit 33. A selection circuit 38 adds the output of the selection circuit 37 and the output of the prediction error decoding circuit 34 to generate a decoded signal. 39 is a background detection circuit that detects the background based on the output of the prediction error decoding circuit 34; 40 is a background detection circuit that receives the outputs of the fourth storage circuit 36 and the addition circuit 38 and uses the output of the background detection circuit 39; a memory control circuit that corrects and outputs pixel values in a designated area; 4;
1 is a post-processing circuit that receives the output of the adder circuit 38 and performs processing such as rearrangement and noise removal; 42 is a D/A conversion circuit that converts the digital signal supplied from the post-processing circuit 41 into an analog signal; 43 is a D/A conversion circuit; The output of the A conversion circuit 42 is band-limited and output to the video output terminal 4.
This is a low-pass filter that outputs to 4. Next, these operations will be explained. Video signal input from video input terminal 1, e.g. NTSC
The signal is limited to a predetermined band, for example 4.2MHz, by a low-pass filter 2 and an A/D conversion circuit 5, and is
(sc is the subcarrier frequency), and is encoded into a digital signal of 8 bits per sample, for example, and supplied to the preprocessing circuit 6. FIG. 2 is a diagram showing an example of the configuration of the preprocessing circuit 6, in which 601 is a color separation TDM circuit, 602 is a noise removal circuit, and 603 is a scan conversion circuit. The present invention is directed to a composite signal composed of a luminance signal and a color signal, such as an NTSC signal or a PAL signal, as an input signal. In such a signal, the subcarrier modulated by the chrominance signal is frequency multiplexed into the high frequency range of the luminance signal, and the phase of this subcarrier is shifted by 180° for each frame, so the frame is processed as is. Even if the difference between data is encoded, it cannot be encoded with high efficiency.
The color separation TDM circuit 601 is a circuit for converting the signal format to enable high-efficiency encoding.
The luminance signal Y is separated into two color signals C ₁ and C ₂ (for example, an I signal and a Q signal), and a time-compressed signal for the color signal is time-division multiplexed during the blanking period of the luminance signal. Figure 3 shows the output of the color separation TDM circuit 601.
FIG. 3 is a diagram showing the relationship between the TDM signal format and sample points, in which (a) shows the signal of one horizontal scanning line of the NTSC signal, and (b) shows the TDM color TV signal format. 455 samples per line,
The amplitude value of the color burst is transmitted in the first 7 samples, and the color signal and luminance signal are transmitted in the following 63 and 385 samples, respectively. In the figure, the C ¹ and C ² signals divide the sample value of the odd line into two lines, odd and even, and send them out. The _C1 signal is transmitted only for odd lines, and the _C2 signal is transmitted only for even lines. The noise removal circuit 602 can be realized by the circuit configuration of a normal noise reducer. That is, minute differences between frames are regarded as noise and suppressed. The scan conversion circuit 603 is composed of memory for multiple lines. FIG. 4 shows the format of input and output signals of the scan conversion circuit 603, where (a) shows the output of the noise removal circuit 602, and (b) shows the scan conversion output. The figure shows a case where scan conversion is performed between 7 lines, and the noise removal circuit 6
The outputs of 02 are sequentially written from the 1st line to the 7th line memory. The written data consists of samples arranged vertically as shown in the scan conversion output column of the figure.
X ₁ ¹ , X ₁ ² , ......X ₁ ⁷ , X ₂ ¹ , X ₂ ² ......X ₂ ⁷ ,
Read out in the order of X ₃ ¹ ...... However, m in X ^m _o is a line number and n is a sample number. This scan conversion has a memory for 14 lines, and during the 7-line period when writing to the 7-line memory, it reads from the other 7-line memory, and in the next 7-line period, it reads from the memory to which it is written. This can be achieved by switching memory. After the scan-converted data is delayed by a predetermined time, it is sent to the optimal prediction block detection circuit 9 and the subtraction circuit 11. The optimal prediction block detection circuit 9 inputs the value supplied from the preprocessing circuit 6, and stores the block with the smallest prediction error for one block of this signal, for example, data for 7 lines x 7 samples, in the first storage circuit 7. and the output of the second memory circuit 8. FIG. 5 shows an example of the configuration of the optimal prediction block detection circuit 9, in which 901 is an expansion circuit, 902--
914 is a prediction error accumulation circuit (ACM), 915 to 9
27 is a vertical optimum block detection circuit (VBD), 92
8 is a background prediction error accumulation circuit, and 929 is a horizontal optimum block detection circuit. Note that the number inside ▽ in the figure indicates the number of bits. FIG. 6 shows an example of a detailed configuration of the expansion circuit 901 shown in FIG.
2 and scan conversion circuits 9103 to 9115. FIG. 7 is a pixel arrangement diagram for explaining the processing operation of the expansion circuit 901, in which (a) shows the pixel arrangement of the current signal and the background signal, and (b) shows the pixel arrangement of the signal one frame before. . Here, at x ^m _o , y ^m _o , m
indicates the line number within the block, and n indicates the pixel number within the block. In FIG. 5, a signal from the first storage circuit 7 is supplied to the expansion circuit 901. This signal is the signal output via the 7 line memories 9101 and 9102 in FIG.
1 and the scan conversion circuit 9 as an output that does not pass through the 7-line memory.
103 to 9115, and the scan conversion circuit 91
From 03 to 9115, converted signal strings d ₂ to _{d 14}
An 8-bit signal is output, and the prediction error accumulation circuit 9
14. FIG. 8 shows a signal time chart of the expansion circuit 901, and ~ is the scan conversion circuit 9103-9.
115, _d2 to _d14 indicate the converted signals. In addition, in FIG. 5, for the 8-bit signal of 49 time slots input from the scan conversion circuit 603 of the preprocessing circuit 6, the prediction error accumulation circuits 902 to
At 914, the error with the signal corresponding to the position moved by ±6 pixels in the vertical and horizontal directions is accumulated, and 13 calculation outputs corresponding to the movement of ±6 pixels in the vertical direction are obtained in one prediction error accumulation circuit. . The obtained calculation result is 13
It is converted into time-slot time-series data and sent to vertical optimum block detection circuits 915-927. Figure 9 shows the prediction error accumulation circuit (ACM) 902~
An example of the configuration of one circuit (lth) in 914 is shown, in which 9116 to 9128 are subtraction circuits, 9129 to 9141 are ROM, 914
2 to 9154 are adder circuits, 9155 to 9180 are flip-flops, 9181 to 9193 are tri-state output flip-flops, and 9194 is a 7
This is a sample delay circuit. First, the signal x input from the scan conversion circuit 603
are supplied to subtraction circuits 9116 to 9128, where the outputs of prediction error accumulation circuits 902 to 904 or expansion circuit 901 are subtracted. ROM9129～
9141 outputs "1" when the absolute value of the output of each connected subtraction circuit is equal to or higher than a predetermined threshold value, and "0" otherwise. Next, adder circuits 9142 to 91
54 and the corresponding flip-flop 9155
9167 constitutes an accumulation circuit, and each ROM 9129 to 9141 has a predetermined size for one block period.
Accumulate the output values of The cumulative results for each block are stored in flip-flops 9168 to 9180.
The results are time-division multiplexed into one signal series by tri-state (TS) output flip-flops 9181-9193, and output to corresponding vertical optimum block detection circuits 915-927, respectively. The 7-sample delay circuit 9194 delays the signal supplied from the prediction error accumulation circuit or expansion circuit by 7 sample periods and outputs the delayed signal to the next prediction error accumulation circuit. FIG. 10 shows a signal time chart of the prediction error accumulation circuits 902 and 903. As shown in this figure
After 49 time slots, cumulative prediction error data g is 13
You can get one. This is converted into time series data h of 13 time slots and output to the vertical optimum block detection circuit. There are 13 vertical optimal block detection circuits (VBD) (915 to 927), and one VBD circuit has 13 types (±6 lines) in the vertical direction with a certain value in the horizontal direction.
Block data corresponding to the movement of is input. Figure 11 shows the vertical optimal block detection circuit (VBD)
9195 is a comparison circuit, 91
96 is a counter, 9197 and 9198 are selection circuits, 9199 to 9202 are flip-flops, 9
203 and 9204 are tri-state output flip-flops. The comparison circuit 9195 compares the input value from the prediction error accumulation circuit with the flip-flop 919.
The output values of 9 are compared every time slot, and the comparison results are output to selection circuits 9197 and 9198. The selection circuit 9197 selects the smaller of the two inputs based on the results of the comparison circuit 9195. Flip-flop 9199 outputs the maximum value that can be represented at the beginning of the block, and thereafter stores the output of selection circuit 9197. Therefore, this output becomes the smallest data among the input circuits from the prediction error accumulation circuit after 13 time slots. Flip-flop 9201 stores the output of flip-flop 9199 for each block. Flip-flop 92 with tri-state output
03 is connected by a wired OR to a similar tri-state output flip-flop in another vertical optimum block detection circuit, and each output is time-division multiplexed into one signal sequence and sent to the horizontal optimum block detection circuit 929.
Output to. Counter 9196 outputs information representing the time slot number within the block. This output is connected to the selection circuit 9198, flip-flops 9200 and 92
02, flip-flop 9 with tri-state output
204 and is output to the horizontal optimum block detection circuit 929 as address information of data finally selected by the selection circuit 9197. At this time, the counter 9196 is
5, when the two inputs are equal, up and down,
For the motion compensation range of 6 samples each in the left and right directions,
Priority selection is performed to select the value closer to the center. FIG. 12 shows an input/output signal sequence of the vertical optimum block detection circuit shown in FIG. 11. Moreover, the prediction error accumulation data for the background is calculated in the background prediction error accumulation circuit 928.
The configuration of this circuit is comprised only of the circuit surrounded by the broken line in FIG. 9, and its operation is the same as that described with reference to FIG. Next, the output of 13 vertical optimal block detection circuits,
The smallest one must be selected from a total of 14 outputs from one background prediction error accumulation circuit. Therefore, 14 pieces of data are first converted into time series data of 14 time slots and output to the horizontal optimum block detection circuit 929. FIG. 13 shows the configuration of the horizontal optimum block detection circuit 929, in which 9205 is a comparison circuit, 9206 is a counter, 9207 and 9208 are selection circuits, and 920
9,9210,9212 are flip-flops, 9
211 is a decoder. One optimum block is detected by the same operation as the vertical optimum block detection circuit (FIG. 11). In this case, the selection circuit 9208 selects one of the data supplied from the tri-state output flip-flop group (9204 and others) of the vertical optimum block detection circuit in synchronization with the operation of selecting the output of the counter 9206 and the output of the flip-flop 9210. Select. As a result, flip-flop 9210 outputs information representing the optimal prediction block in both the vertical and horizontal directions. The decoder 9211 decodes this information and assigns codes as shown in the table to each of the vertical and horizontal areas. flipflop 9212
stores the output motion blocks and background blocks of the decoder 9211 block by block, and stores the output motion blocks and background blocks of the decoder 9211,
and is supplied to the code allocation circuit 13. The signal at the position corresponding to the detected optimal block is outputted to the subtraction circuit 11 and addition circuit 23 as a predicted signal after adjusting the delay time in the selection circuit 10.

【table】

[Table] FIG. 14 shows an example of the configuration of the selection circuit 10,
101 to 104 are memories, 105 is an address control circuit, 106 is a flip-flop, and 107 is an inverter. The data shown in FIG. 7 is stored in the memory 101.
Of (b), the upper 1/3 is written, the center part is written to the memory 102, the lower 1/3 is written to the memory 103,
The background (output of the second memory circuit 8) is written in the memory 104. Reading of the memories 101 to 103 is supplied from the address control circuit 105, and the memory 1
Regarding 04, the written data is sequentially read out after being delayed by a predetermined fixed period of time. FIG. 15 shows an example of the configuration of an address control circuit for writing and reading, in which 1501 and 1506 are counters, 1502 is a multiplication circuit, and 1503 and 150 are counters.
4 is an adder circuit, 1505 is a selection circuit, and 1507 is a decoder. Writing to the memories 101 to 104 is performed using the output of the counter 1501 that counts up the sampling clock _fs as an address. The read address is controlled so that pixels corresponding to the optimal prediction block are read out in order. That is,
Multiplying circuit 1 by horizontal address of optimal block
The value is multiplied by 7 by 502 and added to the vertical address by an adder circuit 1503, and the value obtained by adding the delay amount and the write address to this value becomes the read address. The delay amount is the time required for the quantity-appropriate prediction block detection circuit 9 to detect an optimal block, and this is a value determined by the device design, and is realized by setting this value. Selection circuit 1
505 is the output of the counter 1501 and the addition circuit 15
The output of 04 is alternately switched and output to each memory. A counter 1506 counts lines based on the line at the head position of the optimal block, that is, the vertical optimal block vector, and selects a memory to be read from among the three memories 101-103 based on the counted value. Each of the memories 101 to 104 is controlled using a chip select terminal CS, and output is output only from the designated memory. These outputs are supplied to the flip-flop 106 by wired OR, where they are waveform-shaped and output as predicted values to the subtraction circuit 11 and addition circuit 23. The prediction error outputted by the subtraction circuit 11 is quantized into representative values of, for example, 15 levels in the prediction error processing circuit 12 based on predetermined quantization characteristics. Although a case has been described here in which the prediction error processing circuit 12 is composed of a quantization circuit, it is also possible to include a frame difference suppression circuit/expansion circuit. FIG. 16 is a diagram showing an example of the configuration of the prediction error processing circuit 12, in which 121 is a suppression circuit, 122 is a quantization circuit, and 123 is an expansion circuit. The prediction error supplied from the subtraction circuit 11 is suppressed in the suppression circuit 121 based on predetermined nonlinear characteristics. Several types of characteristics are prepared and controlled according to the storage capacity of the buffer memory 18. The larger the amount of memory, the higher the suppression rate characteristics are switched to. At this time, it is also possible to distinguish the characteristics based on the color signal and the luminance signal. The suppressed data is quantized in a quantization circuit 122 based on predetermined characteristics. In this case, it is also possible to switch the characteristics depending on the storage capacity of the buffer memory 18. The quantized data is sent to the code assignment circuit 13, and is also sent to the decompression circuit 1.
23, the signal is expanded based on the inverse characteristic of the suppression circuit 121. Suppression circuit 121, quantization circuit 12
2. The decompression circuit 123 can all be realized with a ROM. Furthermore, as another embodiment, it is also possible to replace the quantization circuit 122 with a previous value DPCM circuit.
In this case, the inter-frame difference value is further subjected to intra-frame previous value DPCM processing, resulting in inter-frame composite prediction. Furthermore, as another embodiment, the prediction error processing circuit 12 may be configured with an orthogonal transform encoding circuit. FIG. 17 is a diagram showing another configuration of the prediction error processing circuit 12 in this case, in which 124 is an orthogonal transform circuit, 125 is a quantization circuit, and 126 is an orthogonal inverse transform circuit. The orthogonal transform circuit 124 can be configured using any method such as Hadamard transform or cosine transform. For example, to explain the Hadamard transform, the data input from the subtraction circuit 11 is divided into blocks every n samples, and this block is associated with the vector X = (x ₁ , x _{2 .} . . , and each component is quantized in the quantization circuit 125. The quantization characteristic may be changed depending on the amount of information measured by the orthogonal transform circuit 124 or the amount of storage in the buffer memory 18. The orthogonal inverse transform circuit 126 performs inverse transform according to the relationship X= ^AT Y and outputs the result. Next, the code assignment circuit 13 will be explained. FIG. 18 is a diagram showing an example of the configuration of the code assignment circuit 13, in which 131 and 134 are encoding circuits;
32 is a delay circuit, 133 is a subtraction circuit, and 135 is a multiplex circuit. The data supplied from the prediction error processing circuit 12 is divided into blocks every 49 samples, for example, and when the values of all samples in the block are zero, it is considered an invalid block and output is prohibited. The other blocks are treated as valid blocks, and a predetermined variable length code is assigned to each sample data and output. Information representing the type of block is supplied to the address information generation circuit 14, where one bit of "1" is set for an invalid block.
Outputs 1 bit “0” for the valid block,
A multiplexing circuit 17 performs time division multiplexing on the beginning of the block. Here, we have described the case where data is transmitted in blocks, but there is also the so-called run-length method, in which consecutive numbers of zero values are transmitted as codes, and for data of other values, the addresses are transmitted as codes. There is a way to do it. In this case as well, these address information are generated from the address information generation circuit 14.
The signal is output to multiplex circuit 17. The motion vector information supplied from the optimal prediction block detection circuit 9 is delayed by a predetermined time by a delay circuit 132, subtracted from the current signal by a subtraction circuit 133, and the difference value is converted into a predetermined variable length by an encoding circuit 134. A code can be assigned. The multiplexing circuit 135 time-division multiplexes the outputs of the encoding circuits 131 and 134 and outputs the multiplexed signal to the multiplexing circuit 17. Delay circuit 1
The amount of delay at 32 can be one block, one field, one frame period, etc. Further, the contents of the delay circuit 132 are reset, for example, at the beginning of the line. Although a method of transmitting motion vector information in the form of a difference has been described here, there is also a method of encoding and transmitting the data as it is without taking the difference. The multiplexing circuit 17 time-division multiplexes the outputs of the code allocation circuit 13, address information generation circuit 14, error control information transmission circuit 15, and encoding control information generation circuit 16. The buffer memory 18 temporarily stores irregularly input data, and transmits the data to the transmission clock generating circuit 19.
Read with a constant clock provided by Transmission clock generation circuit 19, frame configuration circuit 20, and digital interface 21 are conventional circuits that can be easily implemented by those involved in this type of equipment. The encoding control information generation circuit 16 detects the storage capacity of the buffer memory 18, and according to the storage capacity, 1
A coding mode such as sub-sample coding in which every sample is coded or field frame dropping in which every other field is coded is determined, and control information representing the mode is supplied to various necessary circuits. Further, the data outputted from the prediction error processing circuit 12 is added to the output value of the selection circuit 10 in the addition circuit 23, and outputted to the first storage circuit 7 and the storage control circuit 25 as a local decoded signal. Next, the background detection circuit 24 and storage control circuit 25, which are features of the present invention, will be explained. The background detection circuit 24 receives the value supplied from the prediction error processing circuit 12, and when this value is less than a predetermined threshold, it considers it to be the background and outputs background information “1” indicating that it is the background to the storage control circuit 25. . This is an example in which the background detection circuit 24 is composed of only a threshold circuit, but the output of the threshold circuit is also stored for, for example, 6 frame periods, and an area that is "1" for 6 consecutive frame periods is stored. may be regarded as the background and background information may be output. Furthermore, although the embodiment described above has been described in which the background area is identified in units of samples, there are other cases where the background area is identified in units of blocks of, for example, 7 lines x 7 samples. In this case, when all samples in a block are less than a predetermined threshold, this block is regarded as a background area and background information is output. In addition, in this embodiment, when all samples in a block are less than a predetermined threshold, the background is used, but in other embodiments, when the number of samples in a block that exceeds a predetermined threshold is less than or equal to a predetermined value, Consider this block as the background. FIG. 19 is a diagram showing an example of the configuration of the storage control circuit 25, in which 251 is a subtraction circuit, 252 is a difference discrimination circuit, 253 is an addition value control circuit, 254 is an addition circuit, and 255 is a switch. Subtraction circuit 251
subtracts the output value of the second storage circuit 8 from the locally decoded value supplied from the adder circuit 23 and outputs the difference.
The difference discrimination circuit 252 discriminates whether the output of the subtraction circuit 251 is zero, positive, or negative, and outputs discrimination information. The addition value control circuit 253 switches the output value according to the output of the difference discrimination circuit 252 when the output of the background detection circuit 24 is "1". In other words, when the output of the difference discrimination circuit 252 is positive, it is +m (+m/256V expressed with 8-bit accuracy), and when it is negative, it is -m.
, outputs 0 when it is zero. Also, the background detection circuit 24
When the output of is “0”, it outputs 0. The value of m is, for example, 1. Also, when the data supplied from the encoding control information generation circuit 16 represents the sample mode,
The video field period is determined by the addition value control circuit 253.
outputs 0. Similarly, when representing the field frame drop mode, 0 is output for the field period during which the frame is dropped. In the above example, the addition value control circuit 253 is connected to the background detection circuit 2.
4. Although the explanation has been given of a system that operates only in response to the outputs of the difference identification circuit 252 and the encoded control information generation circuit 16, the following configuration may also be possible. FIG. 20 is a diagram showing another configuration of the addition value control circuit 253, in which 2531 is a counter and 2532 is a counter.
is an AND circuit, and 2533 is a ROM. The counter 2531 counts the frame pulses supplied from the clock generation circuit 4, and outputs, for example, "1" for one frame period as a control enable signal to permit execution of addition value control every n frames (n is, for example, 6). Output. When this signal is "0", even if the output of the background detection circuit 24 is "1", it is made "0" by the AND circuit 2532,
ROM2533 outputs 0. ROM2
Reference numeral 533 has the function of the addition value control circuit described with reference to FIG. The output of the addition value control circuit 253 is sent to the addition circuit 254.
is added to the output of the second storage circuit 8,
The signal is supplied to the second storage circuit 8 via the switch 255. The time constant for modifying the contents of the second storage circuit 8 is determined by the values of m and n. In the above embodiment, a case has been described in which one memory having a storage capacity for one frame is installed in the second storage circuit 8. In this case, the contents of the second memory circuit 8 for the background are corrected with a relatively short time constant, so if the person who is the subject is stationary, this person is also regarded as the background, and this signal is also used as the second memory circuit 8. memory circuit 8
will be remembered. As a result, the background will be displayed next time the person moves, but since the correct background signal is not stored in the second storage circuit 8, prediction accuracy cannot be improved. In order to improve this drawback, some embodiments include a plurality of background memories. One memory is, for example, 6
There is also a method in which modification control is allowed for every frame (n=6), and the other memory is set to n=∞ as an extreme example, and the background is written once when the power is turned on and is retained. The switch 255 in FIG. 19 is used to prevent errors in the transmission path and to start up the device when the power is turned on, and will be explained together with the error control information sending circuit 15. The error control information sending circuit 15 is connected to the first storage circuit 7
It is supplied with parity information of the stored data constituted by the receiver, and sends it out to the receiving side via the multiplexing circuit 17. This parity information is received by the receiving section of the communication partner device, and is compared there with the parity information of the stored data in the storage circuit of the receiving section. When the power is turned on, the data stored on the transmitting side and the data stored on the receiving side are different, so a mismatch occurs when the parity information is compared. For this reason, the receiving side sends demand refresh information to the transmitting side requesting a refresh of the stored data since the parity information does not match. This demand refresh information is sent from the transmitter of the communication partner device and received by the receiver of the own device shown in FIG. This demand refresh information is identified by the control information identification circuit 32 in FIG.
5, and is sent to the storage control circuit 25. After receiving this demand refresh information, the first storage circuit 7 sets the output to a predetermined value, for example, 127/256V, for one frame period from the start of the video frame, and performs a predetermined interframe encoding process. conduct.
Information for identifying a frame with a value set, that is, memory set information, is sent from the error control information sending circuit 15 and received by the receiving section of the communicating party via the multiplexing circuit 17. Here, the received memory set information is detected, and the output of the storage circuit is set to the same predetermined value as the transmitter for one video frame period following this information, for example, 127/
It is set to 256V and predetermined interframe decoding processing is performed. As a result, after one frame, the data stored on the transmitting side and the data stored on the receiving side completely match, and thereafter, even when the parity information of the stored data is checked, no mismatch occurs unless a transmission path error occurs. In order to reduce the interval between occurrences of this demand refresh, it is also possible to install a circuit for performing error correction encoding and decoding on the encoded data to be transmitted. In this embodiment, the case where the demand refresh is performed in units of one video frame has been described, but it may also be performed in units of blocks of a predetermined size. Further, in this embodiment, the case where the stored data is set for one video frame period has been described, but the stored data is set by the method described above only for the first field period of the two fields constituting one frame, and then the stored data is set for the second field period. During the field period, predetermined encoding may be performed by switching to an inter-field encoding method that uses the locally decoded value for the first field as a predicted value. The method for setting the first memory circuit 7 has been described above, and now the method for setting the second memory circuit 8 will be described. Setting of this circuit is performed by a switch 255 shown in FIG. Switch 255
is the first due to the day refresh described above.
Starting from the video frame in which the memory circuit 7 is set, for example, the data supplied from the adder circuit 23 is connected for a period of 30 frames. Due to this,
Regarding the second storage circuit, there is no need to check parity information between the transmitter and the receiver. In the above embodiment, a case has been described in which a demand refresh method is used as a countermeasure against transmission errors.
For example, the contents of the storage circuit on the receiving side may be forced to match the contents on the transmitting side by periodically transmitting the stored data for one line per video frame. In addition, only the data stored in the first storage circuit 7 is periodically transmitted as described above,
The second memory circuit 8 may be set using the data of the first memory circuit 7 at predetermined regular intervals. The transmitter has been described above in detail. The receiving section has the configuration shown in FIG. 1, and each section operates with a function opposite to that of the corresponding section of the transmitting section. In the receiving section, the data decoded by the adding circuit 38 is subjected to predetermined processing by a post-processing circuit 41. FIG. 21 shows an example of the configuration of the post-processing circuit 41, in which 411 is a scan conversion circuit, 412 is a noise removal circuit, and 413 is a D/TDM and modulation circuit. The scan conversion circuit 411 is the scan conversion circuit 603 on the transmission side.
Perform the inverse transformation of . The noise removal circuit 412 can be realized by the configuration of a normal noise reducer, and removes block-like noise generated due to motion compensation encoding.
The D/TDM and modulation circuit 413 separates the time-division multiplexed luminance signal Y and color signals C ₁ , C ₂ , and outputs C ₁ ,
After time-stretching the _C2 signal, it is converted to the same format as the input signal, ie, a composite signal format such as an NTSC signal or a PAL signal. The output is converted from a digital signal to an analog signal in a D/A conversion circuit 42, limited to a predetermined band in a low-pass filter 43, and then sent to a video output terminal 44. (Effects) As explained above, the present invention makes accurate predictions even for moving images, and the second memory circuit that stores the background even when the background is displayed after the movement is controlled by the memory control circuit. Since the contents are corrected sequentially, the background displayed after the subject moves can be predictively encoded with high accuracy. That is, if high efficiency encoding or bit rate is specified, there is an advantage that high quality can be achieved. Furthermore, the second memory circuit, which can respond to camera switching and changes in conference room brightness, can be sequentially corrected, allowing highly accurate predictive coding.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing an example of the configuration of a preprocessing circuit, FIG. 3 is a diagram showing the relationship between the TDM signal format and sample points, and FIG. Figure 4 shows the format of the input and output signals of the scan conversion circuit, Figure 5 shows the configuration of the optimal prediction block detection circuit, Figure 6 shows the configuration of the expansion circuit, and Figure 7 shows the configuration of the expansion circuit. A pixel layout diagram for explaining processing operations, FIG. 8 is a signal time chart of the expansion circuit, FIG. 9 is a diagram showing the configuration of one circuit of the prediction error accumulation circuit, and FIG. 10 is a signal of the prediction error accumulation circuit. Figure 11 shows the configuration of the vertical optimum block detection circuit, Figure 12 shows the signal train of the vertical optimum block detection circuit, and Figure 13 shows the configuration of the horizontal optimum block detection circuit. 14 shows the configuration of the selection circuit, FIG. 15 shows the configuration of the address control circuit, FIGS. 16 and 17 show an example of the configuration of the prediction error processing circuit, and FIG. 19 is a diagram showing an example of the configuration of the code allocation circuit, FIG. 19 is a diagram showing an example of the configuration of the storage control circuit, FIG. 20 is a diagram showing the configuration of the addition value control circuit, and FIG. 21 is the configuration of the post-processing circuit. It is a figure showing an example. 1...Video input terminal, 2...Low pass filter,
3...Synchronization separation circuit, 4...Clock generation circuit,
5... A/D conversion circuit, 6... Preprocessing circuit, 7...
...first memory circuit, 8...second memory circuit, 9...
...optimal prediction block detection circuit, 10, 37, 15
05,9197,9198,9207,9208
...Selection circuit, 11,133,251,9116
~9128... Subtraction circuit, 12... Prediction error processing circuit, 13... Code assignment circuit, 14... Address information generation circuit, 15... Error control information sending circuit,
16...Encoded control information generation circuit, 17,135
...Multiple circuit, 18,30...Buffer memory,
19...Transmission clock generation circuit, 20...Frame configuration circuit, 21, 27...Digital interface, 22...Data output terminal, 23, 38,
254, 1503, 1504, 9142-915
4... Addition circuit, 24, 39... Background detection circuit,
25, 40...Storage control circuit, 26...Data input terminal, 28...Clock regeneration circuit, 29...Frame decomposition circuit, 31...Address information identification circuit, 32...Control information identification circuit, 33...Word Identification circuit, 34... Prediction error decoding circuit, 35...
Third memory circuit, 36...Fourth memory circuit, 41
... Post-processing circuit, 42 ... D/A conversion circuit, 43
...Low-pass filter, 44...Video output terminal, 1
01-104...Memory, 105...Address control circuit, 106,9155-9180,9199
~9202, 9209, 9210, 9212...
Flip-flop, 107... Inverter, 12
1... Suppression circuit, 122, 125... Quantization circuit, 123... Expansion circuit, 124... Orthogonal transform circuit, 126... Orthogonal inverse transform circuit, 131, 134
... Encoding circuit, 132 ... Delay circuit, 252 ...
...Difference identification circuit, 253...Addition control circuit, 25
5...Switcher, 411, 603, 9103-91
15...Scan conversion circuit, 412, 602...Noise removal circuit, 413...D/TDM and modulation circuit,
601...Color separation TDM circuit, 901...Development circuit, 902-914...Prediction error accumulation circuit, 91
5-927...Vertical optimum block detection circuit, 92
8...Background prediction error accumulation circuit, 929...Horizontal optimum block detection circuit, 1501, 1506, 2
531,9196,9206...Counter, 15
02... Multiplication circuit, 1507, 9211... Decoder, 2532... AND circuit, 2533, 91
29-9141...ROM, 9101, 9102
...7 line memory, 9181 to 9193, 92
03,9204...Flip-flop with tri-state output, 9194...7 sample delay circuit,
9195, 9205... Comparison circuit.

Claims (1)

[Scope of Claims] 1. An input video signal divided into blocks of a predetermined size is divided into blocks of a predetermined size, and for each block, both the background area and the foreground area of the previous frame stored in the first storage circuit 7 are divided into blocks of a predetermined size. In an interframe coding device that performs predictive coding using a signal of a block obtained from a containing image signal as a predicted value, in addition to the first storage circuit 7, the entire image of only the background is stored, and its contents are sequentially stored. A second memory circuit 8 to be corrected and a memory control circuit 25 for correcting the contents of the second memory circuit are provided, and the content obtained from the first memory circuit 7 is provided for each block of the input video signal divided into blocks. At least one block located in the background image corresponding to the position in the image of the block of the input video signal obtained from the second storage circuit 8 is respectively detected by the optimal predictive block detection circuit 9. The feature is that each prediction error when used as a predicted value is calculated, the block with the smallest calculated prediction error is determined to be the optimal block, and the optimal block is selected as the predicted value and predictive coding is performed. motion compensated interframe coding device. 2 The background detection circuit 24 is connected to the prediction error processing circuit 12.
Claim 1, characterized in that the sample is configured to receive a value supplied from the sample, and when the value is less than a predetermined threshold value, it is regarded as a background, and information indicating that it is a background is outputted in units of samples. The motion compensated interframe coding device as described. 3 The background detection circuit 24 is the prediction error processing circuit 12
When the values of all samples in a block of a predetermined size are less than a predetermined threshold value, the block is considered to be background, and information indicating that it is background is output for each block. A motion compensated interframe coding device according to claim 1, characterized in that: 4 The background detection circuit 24 is the prediction error processing circuit 12
When the number of samples in a block of a predetermined size whose value is less than a predetermined threshold is greater than or equal to a predetermined value, this block is considered to be the background. 2. The motion compensated interframe coding device according to claim 1, wherein the motion compensated interframe coding device is configured to output information representing each block. 5 The background detection circuit 24 is connected to the prediction error processing circuit 12.
It is characterized by being configured to receive data supplied from the computer, and when this data continues to be less than a predetermined threshold value for a predetermined plurality of frames, it is regarded as a background and outputs information indicating that it is a background. A motion compensated interframe coding device according to claim 1. 6. If the storage control circuit 25 includes a subtraction circuit 11 that subtracts the output of the second storage circuit 8 from the output of the addition circuit 23, and the output of the background detection circuit 24 indicates the background, the subtraction circuit The second storage circuit 8 stores predetermined positive and negative values corresponding to the positive and negative outputs of the outputs 11 and 11.
2. The motion compensated interframe encoding device according to claim 1, wherein the motion compensated interframe coding device is configured to write the result into the second storage circuit 8 in addition to the output of the motion compensation interframe coding device. 7. The storage control circuit 25 is configured to enable the storage control circuit 25 to modify the data stored in the second storage circuit 8 at predetermined intervals. Motion compensated interframe coding device. 8. The motion compensated interframe encoding device according to claim 1, wherein the second storage circuit 8 includes a plurality of frame memories.