JPS59194588A - Encoding device between movement compensating frames - Google Patents

Abstract

PURPOSE:To raise an encoding efficiency by installing the second storing circuit for storing a background, and contituting a titled device so that the background which is projected after an object moves can also be forecast and encoded with high accuracy. CONSTITUTION:A background detecting circuit 24 receives a value supplied from a forecasting error processing circuit 12, and when it is below a prescribed threshold, it is regarded as a background, and background information 1 is outputted to a storage controlling circuit 25. An adding value controlling circuit 253 of the storage controlling circuit 25 switches an output value in accordance with an output of a difference discriminating circuit 252, when the background information is ''1''. Also, said circuit outputs ''0'', when the background information is ''0''. The output of the adding value controlling circuit 253 is added to an output of the second storing circuit 8, in an adding circuit 254, and supplied to the second storing circuit 8 through a switch 255. The switch 255 starts its operation from a video frame to which a storing circuit 7 is set by a demand refreshment, and data from an adding circuit 23 is maintained in prescribed plural frame periods.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field to which the invention pertains) The present invention relates to a motion compensated interframe encoding device that performs accurate prediction even for moving images and encodes them with high efficiency.

(Prior Art) An interframe coding method is a method for highly efficient coding using interframe correlation of a video signal.

The interframe coding method is a pre-processing method for input video signals.
The pixel value of one frame before is used as the 111 value, and the '
]'Iil'l lj, 'j ;4+', K
It is encoded and transmitted, and is intended for images where the movement of the subject is small, such as on TV, on the premise that the movement of the image is small. If the motion of the image is large, the prediction (1) will not be suitable, and the encoding efficiency will decrease.

The motion compensated interframe coding method improves the pre/A11 accuracy even when there is large motion. In this method, the input signal is divided into blocks of a predetermined size, for example, 7 lines of pixels. 1 to 6) and blocks at positions shifted by ±n pixels (for example, n = 1 to 6) in the horizontal direction are extracted, and the block with the smallest prediction error with the input signal is selected.

In order to express how far this block is shifted in the vertical and horizontal directions, vector information of this block is transmitted to the receiving side, and predictive coding is performed using pixel values within this block as predicted values.

In this way, with conventional methods of this type, for example, when a conference participant moves, the system is only sensitive to the movement of the person.
Since predictions are not accurate for background images such as walls that are projected later, a large amount of information is generated in this area, resulting in a reduction in encoding efficiency. (Objective of the Invention) The present invention solves this drawback. In order to eliminate this, a frame memory for the background is installed, and the background displayed after the person moves is also predictively encoded with high accuracy.The drawings will be explained in detail below.

(Structure and operation of the invention) FIG. 1 is a block diagram showing the structure of an embodiment of the invention, in which in a transmitting section, 1 is a video input terminal, 2 is a low-pass filter that limits the band of the input signal; 3 is a synchronous separation circuit that separates the synchronous signal from the output of the low-pass filter 2; 4 is a clock generator that generates various clock information that is phase-synchronized with the output of the synchronous separation circuit 3 and outputs it to each circuit as necessary for the clock. 5 is an A/D that converts the analog video signal, which is the output of the filter 2, into a digital signal.
a conversion circuit, a preprocessing circuit that divides the output of the 6-digit A/D conversion circuit 5 into blocks of a predetermined size and outputs the same; 7 is a first circuit that stores encoded and decoded processed images; 8 is a second storage circuit for storing a background image @; 9 is a storage circuit that stores the background image @; 9 is a storage circuit that stores a background image;
111 The block where the error is small is the first notationttt
4 circuit 7 and the second storage circuit 8, and 10 detects the optimal prediction block from among the outputs of the first storage circuit 7 and the second storage circuit 8.
A selection circuit 11 selects and outputs the signal of the corresponding block from the output of the storage circuit 8, and a selection circuit 11 subtracts the output of the selection circuit 10 as a predicted value from the output of the preprocessing circuit 6 to calculate the total prediction error. 13 is a prediction error processing circuit that outputs the output of the prediction error processing circuit 12 and the optimal prediction block detection circuit 9. 14 is a code assignment circuit that assigns a predetermined code to the output; 14 is an address information generation circuit that generates information representing a position on the screen, that is, an address; 15 is a first storage circuit 7. An error control information sending circuit that sends out information for matching the contents of the second storage circuit 8 with the contents of the corresponding storage circuits of the receiving section; 16 is a code that generates information representing the encoding control state; 17 is a clock generation circuit 4
The timing is determined by the output of the code assignment circuit 13. Address information generating circuit 14゜A multiplexing circuit that multiplexes the outputs of the error control information sending circuit 15 and the encoding control information generating circuit 16 in a time division manner; 18 temporarily stores the output of the multiplexing circuit 17;
A buffer memory is read out using the output clock of the transmission lock generation circuit 19, 20 is a frame configuration circuit that configures a transmission frame for the output of the buffer memory 18, and 21 is a frame configuration circuit that converts the output of the frame configuration circuit 20 into a transmission line code, for example, an AMI code. A distal interface that sends data to the digital transmission line via the data output terminal 22, and 23,
An adder circuit that adds the output of the prediction error processing circuit 12 and the output of the selection circuit 10 to output a locally decoded signal; 24 is a background detection circuit that detects the background of the image based on the output of the prediction error processing circuit 12; 2! is a storage control circuit which receives the outputs of the addition circuit 23 and the second storage circuit 8, corrects the pixel values of the area designated by the output of the background detection circuit 24, and outputs the corrected values.

On the injured side, 26 is a data input terminal, 27 is a desotal interface that receives an input transmission path code, such as an AMI code, and converts it into a signal that can be processed by square code, such as a unipolar signal, and 28 is a desotal interface. In addition to generating a transmission line clock by receiving the output of 27,
29 is a frame decomposition circuit that decomposes the transmission frame from the output of the digital interface 27; 30;
3 is a buffer memory that temporarily stores the output of the frame decomposition circuit 29 and reads it out in accordance with the stored slow speed of the booter;
1 is an address information identification circuit that identifies address information from the output of the buffer memory 30 and supplies it to the word identification circuit 33; 32 identifies error control information from the output of the panzer memory 30, which will be described later. The third memory circuit 3
5. Storage control circuit 40 and first storage circuit 7 of the transmitter.
Memory control circuit 25. A control information identification circuit 33 supplies the error control information to the control information sending circuit 15 and also identifies control information for decoding and supplies it to each circuit necessary for decoding. A word identification circuit 34 receives the output of the word identification circuit 33 and detects a prediction error. Prediction error decoding circuit for decoding, 3
5 is a third storage circuit that stores decoded images, 36 is a fourth storage circuit that stores background images, and 37 is a third storage circuit 35. A selection circuit 38 selects and outputs the signal of the block specified by the output of the word identification circuit 33 from among the outputs of the fourth storage circuit 36; 39 is a background detection circuit that detects the background based on the output of the prediction error decoding circuit 34; 40 is a background detection circuit that receives the outputs of the fourth storage circuit 36 and the addition circuit 38; 39 is a storage control circuit that corrects and outputs the pixel values in the designated area; 41 is a post-processing circuit that receives the output of the adder circuit 38 and performs rearrangement, noise removal, etc.; 42;
Reference numeral 43 indicates a conversion circuit that converts the digital signal supplied from the post-processing circuit 41 into an analog signal, and 43 a low-pass filter that limits the band of the output of the D/A conversion circuit 42 and outputs it to the video output terminal 44.

Next, these operations will be explained. Video input terminal 1
If the video signal is processed manually, such as NTSC, low-pass filter 2. A predetermined band, for example, 4
．． 2 MHy, sampled at a frequency of 4 fsc (fsc is the subcarrier frequency), for example 1
The signal is encoded into a 98-bit dinotal code and supplied to the preprocessing circuit 6.

FIG. 2 is a diagram showing an example of the configuration of the preprocessing circuit 6,
601 is a color molecule 4 (r TDM circuit), 602 is a noise removal circuit, and 603 is a scan conversion circuit.The present invention uses a composite signal composed of a luminance signal and a chrominance signal, such as an NTSC signal or a PAL signal, as an input signal. In such signals, the subcarrier modulated by the chrominance signal is frequency multiplexed into the high frequency range of the luminance signal.
Moreover, the phase of this sag carrier is 1800 per frame.
Since it is shifted, even if the inter-frame difference is encoded as it is, it cannot be encoded with high efficiency. The color separation TDM circuit 601 is a circuit that converts the signal format to enable high-efficiency encoding. The time-compressed signal is time-division multiplexed during the blanking period of the luminance signal.

FIG. 3 is a diagram showing the relationship between the format of the TDM signal that is the output of the color separation TDM circuit 601 and the sample points. (a) shows the signal of one horizontal scanning line of the NTSC signal;
(b) shows a TDM color TV signal format. 1
The first 7 samples transmit the amplitude value of the color burst, and the subsequent 63 samples and 385 samples transmit the color (number 8, brightness 1\ information), respectively.In the figure, C1, The C2 signal transmits the Zanzol value of the odd line divided into two odd and even lines.The C1 signal transmits only the odd line, and the C2 signal transmits only the even line.

The noise removal circuit 602 can be realized by the circuit configuration of a normal noise reducer. That is, it is regarded as a minute inter-frame difference total noise and is suppressed.

The scan conversion circuit 603 is made up of a memory for a plurality of lines.

FIG. 4 shows the format of the input/output signals of the scan conversion circuit 6030, (a) is the output of the noise removal circuit 602, (b)
) indicates the scan conversion output. The figure shows a case where scan conversion is performed between seven lines, and the output of the noise removal circuit 602 is sequentially input from the first line to the seventh line memory by =2.1. The written data is written as x% t x, 2.・・・・・・
・Xl7IX21. X22...X27. X31...
Read out in the order of... However, m of X stomach is line code, n
is a sample fragrance name. This scan conversion has a memory for 14 lines, and during the 7-line period written in the 7-line memory, it is read from the other 7-line memory, and the next 7-line period is written in the 7-line memory.
This can be realized by switching between the memory for writing and the memory for reading during the line period. After the scan-converted data is delayed by a predetermined time, it is sent to the optimal predicted block detection circuit 9 and the subtraction circuit 11.

The optimal prediction block detection circuit 9 receives the value supplied from the preprocessing circuit 6 as input, and stores the block with the smallest prediction error for one block of this signal, for example, data for 7 lines x 7 samples, in the first storage circuit 7. and second storage circuit 8
Detect from the output of

FIG. 5 shows an example of the configuration of the optimum predicted block detection circuit 9, in which 901 is an expansion circuit, 902 to 914 are prediction error accumulation circuits (ACM), 915 to 927 are vertical optimum block detection circuits (VBD), 928 is a background prediction error accumulation circuit, and 929 is a horizontal optimum block detection circuit.

Note that the numbers in the figure indicate the number of bits.

FIG. 6 shows an example of a detailed configuration of the expansion circuit 901 shown in FIG. 5, which is composed of a 7-line memory 910L9102 and scan conversion circuits 9103-9115.

FIG. 7 is a pixel arrangement diagram for explaining the processing operation of the expansion circuit 901, in which (a) shows the pixel arrangement of the current signal and the background signal, and (b) shows the pixel arrangement of the signal one frame before. show. Here, X';! ;” In VW, m indicates a line number within a block, and n indicates a pixel number within a block.

In FIG. 5, a signal from the first storage circuit 7 is supplied to the expansion circuit 901. This signal is the signal output through the 7-line memory 9101 and old 02 in FIG.
, a signal ■ outputted via the 7-line memory 910.1'i, and an output ■ that does not pass through the entire 7-line memory are supplied to the scan conversion circuits 9103 to 9115, respectively, and the converted signal is output from the scan conversion circuits 9103 to 9115. signal string d2
An 8-bit signal of ~d14 is output and input to the prediction error accumulation circuit 914.

FIG. 8 shows a signal time chart 1 of the expansion circuit 901, where ■ to ■ are signals supplied to the scan conversion circuits 9103 to 9115, and d2 to d14 are converted signals.

In addition, in FIG. 5, prediction error accumulating circuits 902 to 914 calculate ±6 pixels in each of the vertical and horizontal directions for the 8-bit signal of 49 time slots inputted from the horizontal and vertical conversion circuit 603 of the preprocessing circuit 6. - Errors from the signal corresponding to the position are accumulated, and 13 calculation outputs corresponding to the movement of ±6 pixels in the vertical direction are obtained in one prediction error accumulation circuit. The obtained calculation results are converted into time series data of 13 time slots and sent to vertical optimum glock detection circuits 915-927.

FIG. 9 shows an example of the configuration of one (second) circuit among prediction error accumulation circuits (ACM) 902 to 914, in which 9116 to 9128 are subtraction circuits, 9129 to 9128 are subtraction circuits;
9141 is ROM, 914.2 to 9154 are adder circuits =
, 9155-9180 are Frigg Flossop, 9181-
9193 is a tri-state output 7 linoghuronode, 9
194 is a 7-sample delay circuit.

First, the signal X that is input to the scan conversion circuit 603 is
'; Supplied to circuits 9116-9128, where the pre-dI
j11,1:,NTI. γ)-circuit or the output of the expansion circuit 901 is subtracted. ROM 9129-9141
outputs "o" when the absolute value of the output of each connected subtraction circuit is above a predetermined threshold. Next, the adder circuits 9142 to 9154 and the corresponding fringe flops 9155 to 9167 constitute an accumulator circuit, and each ROM 912 for one bronch period of a predetermined size
Accumulate the output values of 9 to 9141. The accumulation results for each block are stored in fritsuno flops 9168 to 9180, and the results are time-division multiplexed into one signal sequence by fritsuno flops 9181 to 0193, which output tris date (TS). 7j is output to the corresponding vertical pass block detection circuit 1) 15-027. A 7-sample delay circuit KO] 94 delays the signal supplied from the prediction error accumulation circuit or the expansion circuit by 7 samples j-1J1 and outputs it to the next difference accumulation circuit.

FIG. 10 shows a signal time chart of the prediction error accumulation circuits 902 and 903. As shown in this figure, 13 cumulative prediction error data g are obtained after 49 time slots. This is converted into time series data h of 13 time slots and output to the vertical optimization processor and the 7-point detection circuit.

There are 13 vertical optimum detection circuits (VBD) (915
~927), and block data corresponding to 13 kinds of movements (±6 lines) in the vertical direction is input to the 1-game VBD circuit at a certain constant value in the horizontal direction.

FIG. 11 shows the configuration of the vertical optimum block detection circuit (VBD), where 9]95 is a comparison circuit, 9196 is a counter, 9197.9198 is a selection circuit, and 9199 to 92
02 is a Frisoge flop, and 9203 and 9204 are tri-state output flip-flops. Comparison circuit 91
95il-1: Compares the input value of the prediction error accumulation circuit with the output value of the frisogen flop 9199 every 7 times, and outputs the comparison result to the selection circuits 9197 and 9198. The selection circuit 9197 selects the smaller force of the two inputs based on the results of the comparison circuit 9195. Frisoge flop '9199 was at the beginning of the professional 7 rip, and it was obvious! Output the maximum value of J, and after that (
d Stores the output of the A selection circuit 9197.

Therefore, after 13 times, this output becomes the smallest data among the input signals from the prediction error accumulation circuit. Furi, Pfron 09201 stores the output of Nori, Zoflozzo 9199 for each bronc. The tri-state output flip-flop 9203 is connected to a similar tri-state output 7 flip-flop 7) in another vertical optimum plotter detection circuit by wired CIR, and each output is time-division multiplexed into one signal sequence to generate the horizontal optimum plotter. Block detection circuit 929 performs input and output.

Counter 9196 outputs one signal representing the time slot number within the block. This output is the selection circuit 919
8, Norirag Flow = f9200. −9202, is output via the tri-state output free run 0 flozozo 9204, and is finally selected by the predicate selection circuit 9197, “j
It is output to the horizontal optimum block detection circuit 929 as an address report of the data. At this time, the counter 9196 controls the comparison circuit 9195, and when the two inputs are equal,
For the motion compensation range of 6 samples each in the vertical and horizontal directions,
Priority selection is performed to select the value closer to the center.

FIG. 12 shows an input/output signal sequence of the vertical optimum block detection circuit shown in FIG. 11.

Moreover, the prediction error accumulation data for the background is calculated in the background prediction error accumulation circuit 928.

The configuration of this circuit is comprised only of the circuit surrounded by the broken line in FIG. 9, and its operation is the same as that described with reference to FIG.

Next, the smallest one must be selected from a total of 14 outputs, including the outputs of the 13 vertical optimum block detection circuits and the output of one background prediction error accumulation circuit. Therefore, first 1
The four data are converted into time series data of 14 time slots and output to the horizontal optimum block detection circuit 929.

FIG. 13 shows the configuration of the horizontal optimum block detection circuit 929, in which 9205 is a comparison circuit, 9206 is a counter, and 920
7.9208 is a selection circuit, 9209, 9210, 921
2 is a flip-flop, 9211m decoder. ξ
These operate in the same manner as the vertical optimum block detection circuit (FIG. 11), and one optimum block is detected. In this case, the selection circuit 9208 selects the output of the counter 920G and the flip-flop, f92. In synchronization with the operation of selecting the output of the IQ, one of the data supplied from the Norig float group (9204, etc.) of the tri-state output of the vertical optimum block detection circuit 1 is selected. As a result, the flip-flop 9210 outputs a report representing the optimal prediction block in both the vertical and horizontal directions. Decoder 9
211 decodes these reports and assigns codes as shown in the table to each of the vertical and horizontal directions. The flip floor 7'' 9212 stores the output motion blocks and background blocks of the decoder 9211 for each program and selector circuit 10.
and is supplied to the code allocation circuit 13.

The signal at the position corresponding to the detected optimal block is J441.
i,: delay time in circuit 10! M-adjusted second move 1
Subtraction circuit 11 and addition circuit 23 as fil148
Output to.

FIG. 14 shows an example of the configuration of the selection circuit 1o, and Ic1l
-104 is memory, 105 is address control circuit, J06
is a 7-lip filter, and 1o7 is an inverter. Memory 1o1 contains the data in Figure 7 (b) Nonouchi 1.11/3
Input 9, memory 1.02KiJ: medium heat section, memo l
) 103 K has the lower J/3 inserted 9, memo 'J,
, 104 is written with the background (how the second memory circuit 8 is output).
In. The reading of the memo IJIOI~], 03 is supplied from the address control circuit 105, and the memory 104K
For that matter, see 5. All the packed data are given a predetermined constant value i1-'f
The items that have been delayed will be explained one by one.

Sewing 15191 indicates the address control circuit for pushing/reading.
．． 1506 is a counter, 1502 is a circuit without multiplication, 150
3. 1504 is an addition circuit, 1505 is a selection circuit, 150
7 is a decoder.

Writing to memo UIOI-104 is done using sampling clock f8.
4. The output of the counting counter 15o1 is directly used as an address.

The read address is controlled so that pixels corresponding to the optimal at1+ block are read out in order. That is, the horizontal address of the optimum block is shifted and multiplied by the multiplier 1502, added to the vertical address by the adder 1503, and this value plus the delay amount and the write address is used as the read address. The amount of delay is the time required for the appropriate prediction block detection circuit 9 to detect the optimal block, and this value is determined by the device design, and is realized by setting this value. . Selection circuit 150
5, the output of the counter 1501 and the output of the adder circuit 1504 are all alternately switched and outputted to each memory.

Counter 15o6Fi Counts lines based on the line at the start position of the optimal block, that is, the vertical optimal block vector, and based on that value! l13 memories 101~1
03, select the memory to be read. Each of the memories 101 to 104 is controlled using a chip select terminal CS, and output is output only from the designated memory. These outputs are wired OR, Pflozzo 106
Here, the waveform shaped predicted value is outputted to the subtraction circuit 11 and the addition circuit 23.

[Subtraction circuit] The prediction error output by 1 is calculated by the prediction error processing circuit 12 based on predetermined quantization characteristics.
It is quantized into five levels of representative values.

Here, the prediction error processing circuit 12 k? j Construct a quantization circuit" ↓ Although I talked about the combination, there are also f1/-
It is also possible to include a suppression circuit/expansion circuit for the system difference.

"I 6 [RJ is a diagram showing an example of the configuration of the prediction error processing circuit J2, in which 121 is a suppression circuit, 122 is a boarding circuit, and 123 is an expansion circuit. The prediction error is suppressed in the suppression circuit 121 based on predetermined nonlinear characteristics.

Several types of this characteristic are available, buffer memory 18 notes 1
．． (It is controlled according to the amount of storage. The larger the memory capacity is, the higher the suppression characteristic is switched to. At this time, it is also possible to distinguish the characteristics from the color signal and the luminance signal V. Suppression IF
The obtained data is quantized in a quantization circuit 122 based on a predetermined &'l characteristic. In this case panofanomo+r i
It is also possible to change the characteristics based on the 8 iL storage capacity. The quantized data is sent to the code allocation circuit 13 and expanded in the expansion circuit 123 based on the inverse characteristic of the suppression circuit 121. The suppression circuit 121, the quantization circuit 122, and the expansion circuit 123 can all be realized with a ROM. Alternatively, as another embodiment, the quantization circuit 122 can be replaced with a previous value DPCM circuit. In this case, in addition to the inter-frame difference value, the previous value DP within the frame
0M processing is performed, and interframe composite prediction is performed.

Furthermore, as another embodiment, the prediction error processing circuit 12 may be configured with an orthogonal transform encoding circuit.

FIG. 17 is a diagram showing another configuration of the prediction error processing circuit 12 in this case, in which 124 is an orthogonal transform circuit, 125 is a quantization circuit, and 126 is an orthogonal inverse transform circuit. The orthogonal transform circuit 124 can be configured using any method such as Hadamard transform or cosine transform. For example, to explain the Agemar transformation, the data input from the subtraction circuit 11 is divided into blocks every n samples, this block is associated with the vector X=(Xt + X2...xn)t, and Y= The components are converted according to the relationship of AX, and each component is quantized in a quantization circuit 125. In some cases, the orthogonal transform circuit 124 has a function of converting the data into two or more elements (switching according to a predetermined amount of information or the amount of storage in the buffer memory 18). [The f1 sentence inverse transformation circuit 126 inversely transforms according to the relationship X=ATY] and outputs it.

Next, the code assignment circuit 13 will be explained.

gH): Figure 1-8 shows an example of the configuration of the code assignment circuit 13, in which 131, 1:34 is an encoding circuit, 132 is a delay circuit, 133 is a subtraction circuit, and 135 is a multiplex circuit. It is. The data supplied from the prediction error processing circuit 2 is divided into blocks, for example, every 49 samples, and when 1115 of all samples in the block are zero, it is considered an invalid block.
All output is prohibited. When the other blocks are selected, a variable length code of W is assigned to the data of each sample and output. Pro, l'i'j+ representing yuri's Kakizuki'1
lx to the address h'i alerting circuit 14;
Here, one bit of "l" is output to the effect block, one bit of "0" is output to the effect block, and the multiplexing circuit 17 time-division multiplexes it at the beginning of the program.

Here, we have described the case where data is transmitted in blocks, but there is also the so-called run-length method, in which continuous numbers of zero values are transmitted as codes, and for data of other values, the addresses are transmitted as codes. There is a way to do it.

In this case as well, these address reports are output from the address information generating circuit 14 to the multiplexing circuit 17.

The motion vector information supplied from the optimal predicted block detection circuit 9 is delayed by a predetermined time by a delay circuit 132, and then subtracted from the current signal by a subtraction circuit 133, and the difference value is sent to an encoding circuit 134. A predetermined variable length code is assigned at . The multiplex circuit 135 is an encoding circuit 131.134
The outputs are time-division multiplexed and output to the multiplexing circuit 17. The delay amount determined by the delay circuit 132 can be 1 field, 1 frame period, etc. Also, the delay circuit 132
For example, the contents are reset at the beginning of the line.

Although a method of transmitting motion vector information in the form of a difference has been described here, there is also a method of encoding and transmitting the -4 dimension data without taking the difference.

The multiplex circuit 17 includes a code assignment circuit J3, an address m-report generation circuit 14, an error control clear-report transmission circuit 15, and a code assignment circuit J3.
The output of the 7fl information generating circuit 16 is time-division multiplexed.

The buffer memory 18 temporarily stores and transmits data that is manually processed, and reads it out at a constant clock rate supplied from the signal generation circuit 19 and transmits 1-0 to the lock generation circuit t9 and the frame configuration circuit 20. , digital interface 21 is a conventional circuit readily implemented by those skilled in the art of this type of equipment.

r January control information generation circuit 16 / X y failure memo 1)
Detects 18 memory blocks. Depending on the memory, it determines the encoding mode, such as (1) sub-sample code to be encoded in the sampling device, and (3) to encode in the field (9). , supplies control information representing the mode to each necessary glaze circuit.

Further, the data outputted from the prediction error processing circuit 12 is added to the output 11 of the selection circuit 10 in the addition circuit 23, and is sent to the first memory circuit 7 and the memory control circuit 25 as a local decoded signal. Lami and IJ are performed.

Next, the background detection circuit 24 and storage control circuit 25, which are features of the present invention, will be explained.

The background detection circuit 24 receives a value supplied from the prediction error processing circuit 12, and when this value is less than a predetermined threshold value, it considers it to be a background,
Background information "1"' indicating that it is a background is output to the storage control circuit 25. This is an example in which the background detection circuit 24 is composed of only a threshold circuit, but in addition, the output of the threshold circuit described above is stored for, for example, 6 frame periods, and "°1" is stored continuously for 6 frame periods. Considering the area as a background,
Background information may also be output.

Furthermore, although the embodiment described above has been described in which the background area is discriminated in units of pixels, there is also a case where the background area is discriminated in units of blocks of, for example, 7 lines x 7 samples. In this case, when all samples in a block are less than a predetermined threshold, this block is regarded as a background area and background information is output. In addition, in this embodiment, when all samples in a block are less than a predetermined threshold, it is considered as a background, but in other embodiments, when the number of samples exceeding a predetermined threshold among samples in a block is less than or equal to a predetermined value, This block is considered the background.

FIG. 19 is a diagram showing an example of the configuration of the storage control circuit 25, in which 251 is a subtraction circuit, 252 is a difference identification circuit, 25
3 is an addition value control circuit, 254 is a Calorie calculation circuit, and 255 is a switch. The subtraction circuit 251 subtracts the output value of the second storage circuit 8 from the locally decoded value supplied by the addition circuit 23 and outputs the difference.

The difference identification circuit 252 determines whether the output of the subtraction circuit 251 is zero, positive or negative, and outputs identification information. When the output of the addition value control circuit 253Fi and the background detection circuit 24 is "1", the output value i-11 increases in accordance with the output of the difference identification circuit 252. That is, when the output of the difference discrimination circuit 252 is positive,
/256V), -m to represent a negative value, zero 〇[IJJO
Output. Also, when the output of the background detection circuit 24 is 0'', it outputs 0 '-, 1L. The candy of m is, for example, 1. Also, the data supplied from the encoding control information generation circuit 16 is in sub-sampling mode. At time t, the image field period is an addition (rl'j control circuit 253 outputs O).

Similarly, when representing the field eradication mode, 0 is output for the field period to be eradicated.

Although the addition value control circuit 253 has been described above as operating only in response to the outputs of the background detection circuit 24, the difference identification circuit 252, and the encoded control information generation circuit 16, it may also be configured as follows.

FIG. 20 is a diagram showing another configuration of the addition value control circuit 253, in which 2531 is a counter, 2532 is an AND circuit,
2533 is a ROM. The counter 2531 counts the frame clocks supplied from the clock generation circuit 4, and outputs, for example, one frame as a III control enable signal for permitting execution of addition value control every n frames (n is 6, for example). 1m old 1・pa 1″' is output. When this signal is 11011, the output of the background detection circuit 24 is “
1”, it is determined by the AND circuit 2532.
OII is output from the ROM2533. The ROM 2533 has the function of the addition value control circuit when the 19th time is used. The output of the addition value control circuit 253 is sent to the addition circuit 254, in addition to the output of the second storage circuit 8. and is supplied to the second storage circuit 8 via the archival mold 255. The time constant for modifying the contents of the memory circuit 8 of Q'/2 is the above m and Q'n.
Determined by the time.

In the embodiment of '-Ran', we have described the case where one memory having 61.1 billion capacity, which is equivalent to 121 nodes, is used as the second memory circuit. In this case, the contents of the memory circuit 8 for background δ゛, 2 are modified in a relatively short period of time or with one time constant, so if the subject is stationary, this person is also considered to be tall and this In the memory circuit 8 of I Shukan Momo 12;j12 ”l
:'ll be done. As a result, the background will be displayed after this person moves, but the second 31
1. Since the correct background signal is not stored in the storage circuit 8, prediction accuracy cannot be improved.

In order to improve the shortcomings of
There are also several examples. One memory is, for example, 671 gnomes (
There is also a method in which the correction control is fully permitted every time n=6), and the other memory is set to n= as an extreme example, and the background is written once at the time of inputting the source and is retained.

The 19th switch 255 is used to prevent errors in transmission and to start up the device when current is turned on. This will be explained together with the outbound information sending circuit 15.

The error control information sending circuit 15 is supplied with the ., 01, 1 information of the stored data configured in the first storage circuit 7, and sends it out to the receiver 11M side via the multiplexing circuit 17. This parity information is received by the receiver of the communication partner '14, where it is compared with the TE_IJ_TY information of the data stored in the memory circuit of the receiver. Frost: When the source is turned on, the data stored on the transmitting side and the data stored on the receiving side are different, so a discrepancy occurs when comparing the data.

For this reason, the receiving side sends to the transmitting side demant refresh information requesting that the stored data be refreshed due to the mismatch in parity information. This demand refresh information is sent from the transmitting section of the communication partner device, and is received by the receiving section of the self-equipped camera shown in FIG. This demant refresh information is 1lilJ (
i='ll information YJA identified in the discrimination circuit 32,
The first 11. of the transmitter. French circuit 7, error control information sending circuit 15, and memory? Ii1. The signal is sent to the control circuit 25.

After receiving the demant refresh information from the first storage circuit 7, the output is set to a predetermined value, for example, 127/256V, for one frame period from the starting point of the next movie frame, and the output is set to a predetermined value, for example, 127/256V, and the output is set to a predetermined value, e.g., 127/256V. Performs encoding processing. Information for identifying a frame with a value set, that is, memory set information, is sent from the error control information sending circuit 15 and received by the receiving section of the communication partner device via the multiplexing circuit 17.

The received memory set information is detected here, and this
During one video frame period following the signal, the output of the storage circuit is set to the same predetermined value as that on the transmitting side, for example, 127/256V, and a fixed interframe decoding process is performed.

As a result, after one frame, the data stored in the transmit (14+1) and the data stored in the receive i 11j completely match.
9 Inconsistency does not occur unless .

In order to reduce the interval between occurrences of this command refresh, error correction coding and
It is also possible to install a circuit for decoding.

In this embodiment, the case has been described in which the demant refresh is performed in units of one video frame, but it may also be performed in units of blocks of a predetermined size.

Furthermore, in this embodiment, a case has been described in which the storage data is set for one video frame period, but the storage data is set using the method described above only for one field period of the inner box of two fields constituting one frame, and then the second The field period is the above-described first] (-) predetermined encoding may be performed by switching to an inter-field encoding method that uses the locally decoded value for the field as a predicted value.

The method for setting the first memory circuit 7 has been described above, and the method i for setting the second memory circuit 8 will now be described.

This circuit setting is performed by a switch 255 shown in FIG. The switch 255 starts the video frame in which the first memory circuit 7 is set by the above-mentioned demant refresh, and for example, during the 0 frame period, the adder circuit 23 changes the data to be stored. Connecting. In this case, it is not necessary to match the parity information between the 11-i transmission and reception for the 11α storage circuit of 9.52.

In the above embodiment, demand drift 1 is used as a countermeasure against transmission errors.
In the case of using one type, for example, if i, l-): Periodically for one line per video frame As mentioned above, only the data stored in the first 1j121' and f5 circuits 7 are transmitted every predetermined period, and the second record 1. (for the winter circuit 8, the data of the first 1j121', It is also used to clean and wipe the paper.

The details of the transmitting section have been explained above. The receiving section is shown in Figure 1 (A).
, l l;1'X, each part operates with the opposite function.

In the receiving section, the T-event decoded by the adding circuit 38 is subjected to predetermined processing by a post-processing circuit 41.

FIG. 21 shows an example of the configuration of the post-processing circuit 41.
1 is a scan conversion circuit, 412 is a noise removal circuit, and 413 is D
- TDM and modulation circuits. The scan conversion circuit 411 performs inverse conversion of the scan conversion circuit 603 on the transmission side. The noise removal circuit 412 can be realized by the configuration of a normal noise reducer, and removes block-like noise generated due to motion compensation encoding. The D-TDM and modulation circuit 413 separates the time-division multiplexed luminance signal Y and color signal CI+02, and
,, After time expanding the C2 signal, it is converted to the same format as the input signal, that is, a composite signal format such as NTSC (bin or PAL signal).The output is converted from a digital signal to an analog signal in the D/A conversion circuit 42. The signal is then subjected to a predetermined band redundancy restriction in a low-pass filter 43 and then sent to a video output terminal 44.

(Effects) As explained above, the present invention installs a second memory circuit that stores the background, and enables highly accurate predictive coding even for the background that appears after the subject has moved. There are 711 points where high quality can be achieved in case of 1/1 match where bit 1/F or bit l/F is specified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing an example of the configuration of a preprocessing circuit, and FIG.
is a diagram showing the relationship between the TDM fM format and sample points, rj? : Figure 4 shows the input/output signals of the scan conversion circuit.
Figure 5 is a diagram showing the configuration of the optimum predicted block detection circuit, Figure 86 is the 8i format of the expansion circuit.
Figure 7 shows the processing operation of the expansion circuit. Figure 8 is a signal time chart of the expansion circuit, Figure 9 is a diagram showing the configuration of one circuit of the prediction error accumulation circuit, and Figure 10 is the diagram of the prediction error accumulation circuit. FIG. 11 is a diagram showing the configuration of the retake optimal block detection circuit, FIG. 12 is a diagram showing the signal train of the vertical optimal block detection circuit, and FIG. 5IIV13 is a diagram showing the configuration of the horizontal optimal block detection circuit. Figures 14 and 14 are diagrams showing the configuration of the selection circuit, Figure 15 is a diagram showing the configuration of the address control circuit, and Figures 16 and 17 are diagrams showing an example of the configuration of the prediction error processing circuit. The figure shows an example of the configuration of the code allocation circuit, FIG. 19 shows an example of the configuration of the storage control circuit, FIG. 20 shows the configuration of the addition value control circuit, and FIG. 21 shows the configuration of the post-processing circuit. It is a figure showing an example of composition. 1...Video input terminal, 2...Low pass filter, 3...
...Synchronization separation circuit, 4...Clock generation circuit, 5...
- Wire conversion circuit, 6... Preprocessing circuit, 7... First storage circuit, 8... Second storage circuit, 9... Optimal prediction block detection circuit, 10.37.9197.9198 ,9
207°9208...Selection circuit, 11,133,25
1゜9116-9128... Subtraction circuit, 12... Prediction error processing circuit, 13... Code assignment circuit, 14...
Address information generation circuit, 15...Error control information transmission circuit, 16...Encoded control information generation circuit, 17,135
...Multiple circuit, 18.30...Buffer memory, 1
9... Transmission lock generation circuit, 20... Frame configuration circuit, 2]. 27...Digital interface, 22...Data output terminal, 23, 38, 251, 1503, 1504
゜9142-9154...addition circuit, 24.39...
・Background detection circuit, 25, '40... memory control circuit,
26...Data input terminal, 28...Clock regeneration circuit, 29...Frame decomposition circuit, 31...Address information identification circuit, 32...Control information identification circuit, 33...
・Word application circuit, 34...Prediction error decoding circuit, 3
5... Third memory circuit, 36... Fourth memory circuit,
41... Post-processing circuit, 43... D/A conversion circuit, 4
:3...Low pass filter, 44...Video output control, 101-104...Memory, 105...Address control circuit, 106.9155-9180°9399-
9202, 9209.9210.9212... flip-flop, 107... inverter, 121... suppression circuit, 122, 125... halving circuit, 123...
- Extension circuit, 124... Orthogonal transformation circuit, 126...
Orthogonal inverse transform circuit, 131.134...encoding circuit,]
32...Delay circuit, 252...Difference identification circuit, 2.
53...addition? ij', control circuit, 255...switcher, 411,603°9] 0: U~9115...
・Scan conversion circuit, 4-12,602...A::Sound l"l
': Left circuit, 413...D-TDM and modulation circuit, 6
01...Color separation TDM circuit, 901...Development circuit,
902-914...Prediction error accumulation circuit, 915-92
7... Vertical optimum block detection circuit, 928... Background prediction error accumulation circuit, 929... Horizontal optimum block detection circuit, 1501.1506', 2531.9196°9206... Counter, 15o2...・Multiplication circuit, 1
507゜9211...decoder, 2532...AN
D circuit, 2533°9129-9141-ROM, "9
101.9102-7 line memory, 9181-919
3,9203.9204 - L-listate output flip-flop, 9194...7 sample delay circuit, 9195.9205... Comparison circuit.

Claims (1)

[Claims] (1) In the transmission section, an A/D conversion circuit that converts an input analog video signal into a digital signal;
/1) A preprocessing 1'tij path that receives the output of the conversion circuit, rearranges it into signals for each block of a predetermined size, and outputs the signals;
a first storage circuit that stores the processed image that has been converted into a symbol; a second storage circuit that stores the background image; and the first and second storage circuits that store the background image.
Optimal prediction that detects the most suitable prediction signal with the smallest prediction error for each block signal input from the 2nd preprocessing circuit in response to the output of the storage circuit of fj'll '4. a block detection circuit; a selection circuit that receives the outputs of the first and second storage circuits and selects and outputs the signal of the block designated by the optimal prediction block detection circuit; a subtraction circuit that outputs a prediction error by subtracting it from the output of the preprocessing circuit; a prediction error processing circuit that quantizes this prediction error value and outputs a quantized representative value; and a prediction error processing circuit that quantizes this prediction error value and outputs a quantized representative value; an adder circuit that outputs a locally decoded signal in addition to the output of the
A background detection circuit receives the quantized representative value and detects the background of the image, and receives the outputs of the addition circuit and the second storage circuit. a storage control circuit that corrects the contents of the storage circuit No. 2; a code assignment circuit that assigns a predetermined code to the outputs of the prediction error processing circuit and the optimal prediction block detection circuit; an address information generation circuit that specifies an address at a position above; an error control information transmission circuit that receives outputs from the first and second storage circuits and transmits error control information; and an address information generation circuit and code assignment circuit. A multiplex circuit that time-division multiplexes the outputs of circuits, etc., a speed smoothing buffer memory that temporarily stores the output of the multiplex circuit and reads it out using a clock on the transmission line, and detects the storage capacity of the buffer memory and encodes it according to the storage capacity. 1. An encoding control information generation circuit that determines the encoding mode and generates encoding control information, and a receiver. In the τ section, a buffer memory that once reads and reads the received data at the writing and decoding speed using the transmission line clock;
Various controls are performed from the output of the buffer memory.In @3.
a control information identification circuit for identifying address information, an address information identification circuit for identifying address information, a word identification circuit for identifying a word representing an optimal prediction block and a word representing a quantization representative value, and a control information identification circuit for identifying address information. An error shungo circuit for the first 6 that receives the output of the circuit and decodes the prediction error, a -73 memory circuit that stores the decoded 11 houses, and a fourth note that stores the background image @1.0 times 1 a selection circuit that receives the outputs of the third and fourth storage circuits and outputs a signal of the block specified by the optimal prediction block information that is the output of the word identification circuit; and an output of the tracing circuit. an adder circuit that adds the output of the prediction error iso signal circuit;
a background detection circuit that receives the output of the pre-6111 error kernel code circuit and detects the background of the image; the addition circuit; and the fourth section 1. (c) A memory control circuit which receives the output of the circuit and corrects the contents of the fourth memory circuit in the area designated as the background by the output of the background detection circuit; and a memory control circuit which receives the output of the adder circuit and rearranges the data. It includes a post-processing circuit and a VA conversion circuit that converts the digital signal output from the post-processing circuit into an analog signal, and is characterized by accurately predictive encoding of the background that is displayed after the subject moves. Motion compensated interframe coding device.
'(2) The background detection circuit receives the value supplied from the prediction error processing circuit, and when this value is less than a predetermined threshold value, it considers it to be the background, and outputs information indicating that it is the background in sample units. A motion compensated interframe coding apparatus according to claim 1, characterized in that the apparatus is configured as follows. (3) The background detection circuit considers the data supplied from the prediction error processing circuit or the code allocation circuit to be background when the values of all the samples within a block of a predetermined size are less than a predetermined threshold; The motion compensated interframe coding apparatus according to claim 1, wherein the apparatus is configured to output information indicating that the background is a background on a block-by-block basis. (4) The K-scene detection circuit receives data supplied from the prediction error processing circuit or the code allocation circuit, and the number of Zangle Ω for which the sample value in a block of a predetermined size is less than a predetermined threshold is greater than or equal to a predetermined value. When this occurs, this block is regarded as a background, and information indicating that it is a background is output for each block. Encoding device. (5) When the background detection circuit receives data supplied from the prediction error processing circuit or this circuit, and this data continues to be at a predetermined threshold value Jd for a predetermined plurality of frames. The tl'Q+ compensated interframe coding apparatus according to item (1) of Kawakawa's item (1) of claim 41, characterized in that the apparatus is configured to output information indicating that the image is a background. (6) If the storage control circuit includes a subtraction circuit that subtracts the output of the second notation circuit from the output of the addition circuit, and the output of the first floor of the background detection circuit indicates that the background is )1
A predetermined positive or negative 1 corresponding to the positive or negative output of the C^C attraction circuit.
1. Motion compensated interframe coding according to claim 1, characterized in that the result is written in the second storage circuit in addition to the output of the second storage circuit. Device. (7) The storage control circuit is configured to enable the storage control circuit to modify the data stored in the second storage circuit at predetermined intervals.
) The motion compensated interframe coding device according to item 1. (8) The motion compensated interframe encoding device according to claim (1), wherein the second storage circuit includes a plurality of frame memories.