JPS5915438B2 - Interframe encoding processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an interframe encoding processing method, in particular, uses the outputs of 210 frame memories as predicted values for input pixel values, and adaptively switches the frame memory with the smaller prediction error. This invention relates to an interframe encoding processing method that increases encoding efficiency by suppressing the generation of information.

The interframe coding method that performs band compression using the interframe correlation of the No. 15 television signal quantizes and encodes the interframe difference value and transmits it, and information is generated in areas where the image moves.

FIG. 1 is a diagram showing an example 20 of image movement on a television monitor, and the broken line indicates the position of a person one frame before.
The solid line represents the position of the person in the current frame.

That is, a case is shown in which the object moves from the position of the broken line to the position of the solid line during one frame. If the brightness level of the person is uniform, the inter-frame difference value will be 25 in the shaded area, but area A is the area where the person has moved, and area B is the area where the person has moved.
The area is the area where the background screen appears when the person disappears. In the conventional interframe coding method, area A and area B
It was difficult to distinguish between the two areas, and information was generated in both areas.

In this way, in the area B, information was generated even though there were no people, so there was a drawback that the encoding efficiency decreased. In order to eliminate such drawbacks, the present invention provides a first frame memory 35 in which only the background image is stored in advance, so that an area like the area B in FIG. 1, where the person disappears and the background appears. By using the output of the first frame memory as a predicted value for the area that is coming, information generation in this area is suppressed.
The drawings will be explained in detail below.

FIG. 2 shows an embodiment of the present invention, in which 1 is a signal terminal, 2 and 4 are frame memory terminals, 5 is a differential circuit, 6 is a differential comparison circuit, 7, 8, and 21 are switching circuits, 9 is a quantization circuit, 10 is an addition circuit, 11 is a variable length encoding circuit, 12 is a control signal generation circuit, 13 is a multiplexing circuit, 14 is a buffer memory 18, 15 is a data output terminal, 16 and 17 are absolute value circuits , 18 is a comparison circuit, 19 is a control circuit, and 20 is a memory section.

A digitized image signal input from a signal input terminal 1 is supplied to difference circuits 3 and 5.

Both difference circuits 3 and 5 subtract the outputs of the connected frame memories 2 and 4 from this input signal, and supply the difference values to the switching circuit 7 and the difference comparison circuit 6. In this difference comparison circuit 6, absolute values for the signals supplied from the difference circuits 3 and 5 are created in absolute value circuits 16 and 17, and the magnitudes of both absolute values are compared in a comparison circuit 18, and the absolute value circuit 16 outputs. When the output of the comparator circuit 18 is smaller or equal, it is ``1゛゛, otherwise it is 60゛.It generates a signal and outputs it to the switching circuits 7 and 8 and the multiplexing circuit 13. When the output of the comparison circuit is "1", the output of the differential circuit 3 is connected, and when the output is "10", the differential circuit 5 is connected.Similarly, the switching circuit 8 connects the output of the frame memory 2 when the output of the comparison circuit is "1", 01, the output of the frame memory 4 is connected.The output of the control circuit 19 for both switching circuits 7 and 8 is 6.
When it is 1, the outputs of the differential circuit 3 and the frame memory 2 are connected with the highest priority. The output of the switching circuit 7 is quantized in a quantization circuit 9 based on predetermined quantization characteristics, and is supplied to an addition circuit 10 and a variable length encoding circuit 11.

The output of the quantization circuit 9 is sent to the switching circuit 8 in the addition circuit 10.
After the outputs are added together, they are supplied to the frame memories 2 and 4. Further, the output of the quantization circuit 9 is output from the variable length encoding circuit 11.
The signal is subjected to predetermined encoding and supplied to the multiplexing circuit 13. The multiplexing circuit 13 includes a comparison circuit 18 and a control circuit 19.
Based on the outputs of the variable length encoding circuit 11 and the control signal generation circuit 12, the outputs of the variable length encoding circuit 11 and the control signal generation circuit 12 are multiplexed. When the output of the control circuit 19 reaches "1", a signal representing rewriting of the frame memory 2 is sent out from the output of the control signal generating circuit 12 at the rising edge. When the output of the comparator circuit 18 changes, a signal representing the rising and falling states is selected from among the outputs of the control signal generating circuit 12 and sent out at the rising and falling points, respectively. At other times, the output of the variable length encoding circuit 11 is sent out. The buffer memory 14 temporarily stores data supplied unevenly from the multiplexing circuit 13,
The data are read out sequentially while matching the transmission bit rate and output to the data output terminal 15. Next, the frame memory 2, that is, the memory 2 in which the background image is held, which is a feature of the present invention, will be described.

The frame memory 2 consists of a memory section 20 and a switching circuit 21. When writing the background image to the frame memory 2 in advance, the control circuit 19 emits "1°", and the switching circuit 21 is connected to the output of the adding circuit 10 to rewrite the contents of the memory section 20, After writing the image, the control circuit 19
The switching circuit 21 maintains the contents of the memory section by connecting the output of the memory section 20. That is, when the control circuit 19 wants to write only the background image to the frame memory 2, the control circuit 19 becomes "1" for a predetermined period, and the frame memory 2 becomes "60" after the writing is completed. The background image is then retained during communication.In the above explanation, the method of quantizing and encoding the inter-frame difference value was described, but the method of quantizing and encoding the composite difference value The applicability is clear.

As explained above, according to the present invention, there are two frame memories, and the output of the frame memory with the smaller prediction error value is adaptively switched, so that interframe encoding with high prediction accuracy is always performed. Therefore, there is an advantage that encoding efficiency can be increased.

The present invention is particularly effective for systems in which the background image does not change, such as a video conference system.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing an example of the movement of an image on a television monitor, and FIG. 2 shows the configuration of an embodiment of the present invention. 1... Signal input terminal, 2, 4... Frame memory, 3, 5... Differential circuit, 6...
...Difference comparison circuit, 7, 8, 21...Switching circuit, 9...Quantization circuit, 10...Addition circuit, 11...Variable length Encoding circuit, 12...
... Control signal generation circuit, 13... Multiplexing circuit,
14... Buffer memory, 15... Data output terminal, 16, 17... Absolute value circuit, 1
8... Comparison circuit, 19... Control circuit,
20... Memory section.

Claims (1)

[Claims] 1 A first frame memory in which an image that does not change over a relatively long period of time is written, a second frame memory in which a processed image one frame before the input image signal is written, and a digital a first difference circuit that subtracts the output of the first frame memory from an input pixel value that is a pixel value of the converted input image signal; and a second difference circuit that subtracts the output of the second frame memory from the input pixel value. a difference comparison circuit that compares the outputs of the first and second difference circuits and generates a signal designating the difference circuit with the smaller absolute value; , a switching circuit that switches the output of the second difference circuit, and a quantization circuit that quantizes the output value of the switching circuit based on a predetermined quantization characteristic;
a variable-length encoding circuit that variable-length encodes the output of the quantization circuit; a control signal generation circuit that generates a control signal for notifying a receiving side of the connection state of the switching circuit; and an output of the control signal generation circuit; a multiplexing circuit that multiplexes the output of the variable length encoding circuit, and a buffer memory that temporarily stores the output of the multiplexing circuit, matches the transmission bit rate, and sends it out to the transmission path, An interframe encoding processing method, characterized in that, in accordance with a command from the difference comparison circuit, one of the outputs of the first and second difference circuits, which has a smaller value, is selected and transmitted.