JPS61140289A - High efficient coding method of television signal - Google Patents

Abstract

PURPOSE:To improve the compressing rate by generating a representing flag at each block through the discrimination of majority decision logic without giving a flat to each of interpolation point and transmitting the representive flag in place of plural interpolation points in the block. CONSTITUTION:Picture element data of an interpolation point D is outputted as an output of a sample delay circuit 9 to form a flag relating to the interpolation point D. Picture element data at a sub-sample point (a) from a sample delay circuit 14 and picture element data at a sub-sample point (h) from an input terminal 1 are fed to and adder 15. Outputs 11-14 of adders 15, 18 are interpolation data in longitudinal, lateral and oblique directions, in total 4 directions with respect to the interpolation point D. A flag generating circuit 19 operates an absolute value being a difference between the true value and each of interpolation data 11-14 of the picture element data of the flag D from the sample delay circuit 9 to generate a flag in 2-bit representing the direction of the interpolation minimizing the value. The flag for 8 interpolation points is fed to a majority decision logic circuit 31 and a flag having the largest number is selected.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a highly efficient encoding method for a television signal that can reduce the sampling frequency of the digital television signal and narrow the transmission band of the digital television signal. .

[Conventional technology]

As a new system for television signals, a high-definition television system has been proposed that allows higher resolution in the horizontal and vertical directions than before.Each component (Y, U,

It is difficult to digitize each of (2) using a sampling method of (4, 2, 2) (meaning the ratio of sampling frequencies) and record it on a digital VTR because the transmission band becomes extremely wide.

Therefore, it is necessary to narrow the transmission band by highly efficient encoding of the digitized high-definition television signal.The transmission band is determined by (average number of bits per sample x sampling frequency). Either the average number of bits per sample or the sampling frequency may be reduced.

This invention is a high efficiency encoding method that reduces the sampling frequency.

As a highly efficient encoding method of this type, there is a method that thins out sample data to 172 and transmits data indicating the direction in which to interpolate the thinned data. FIGS. 6 and 7 show one example and another example of a conventional high-efficiency encoding method. In these figures, white dots indicate subsample points, ie, sample data to be transmitted, and black dots indicate interpolation points, ie, sample data to be thinned out. Solid lines and broken lines indicate lines, and the line indicated by the solid line is the line of the field to be processed.

In FIG. 6, adjacent sub-sample data B and C on the same line as the interpolation point X and sub-sample data A and D above and below the interpolation point X are shown. On the receiving side, data at an interpolation point is interpolated from the two sub-sample data in either the horizontal direction or the vertical direction. In the case of this interpolation, it is determined on the transmitting side which direction interpolation is better, and the result of the determination is transmitted as one additional bit in place of the interpolation point. (2) When samples are quantized to 8 bits, the compression ratio of the high efficiency encoding method shown in FIG. 6 is (8+1)/(8+8)=0.5625.

FIG. 7 shows not only sample data in the vertical and horizontal directions, but also sub-sample data (E, F) (G) located at interpolation points in different diagonal directions.

This is an example in which interpolation using H) is also possible. On the transmitting side, it is determined which direction is the best for interpolation out of a total of four directions, and the result of this determination is transmitted as two additional bits in place of the interpolation point.

■If the sample is quantized to 8 bits, the compression rate of the high-efficiency encoding method shown in Figure 7 is (8+2)/(
8+8)=0.625. Although the compression ratio is inferior to the method shown in FIG. 6, the method shown in FIG. 7 can improve the image quality.

[Problem that the invention seeks to solve]

The conventional high-efficiency encoding method described above is difficult to record digital high-definition television signals on a digital VTR because the compression ratio is still insufficient.

Therefore, an object of the present invention is to provide a high-efficiency encoding method that improves the compression rate and provides the same image quality as the conventional high-efficiency encoding method.

[Means for solving problems]

The present invention provides high-efficiency encoding of a television signal in which interpolation points are thinned out among a plurality of pixel data included in a two-dimensional block of a digital television signal, and the remaining sample points after the thinning are transmitted. The method comprises: determining for each of the interpolation points whether less vertical interpolation or horizontal interpolation is better; and generating a flag indicating the result of this determination; and generating a flag for each of the interpolation points. The step of determining the majority logic to select the flag with the largest number of flags from among them and generate a representative flag of the two-dimensional block, and the step of making the sample points and the representative flag the encoded output of the two-dimensional block. This is a highly efficient encoding method for television signals.

[Effect]

Television images have the property that a plurality of pixel data contained in a small two-dimensional area, that is, a block, are correlated with each other. Therefore, the direction of interpolation with respect to interpolation points in the same block is approximately the same. do. This invention focuses on this correlation, and without adding a flag to each interpolation point,
A representative flag is generated for each block by majority logic. This representative flag is transmitted instead of a plurality of interpolation points within the block. Therefore, unlike adding a flag to each interpolation point, the compression ratio can be improved.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG.
Processing is performed for each dimension block. Within this block, 8 is indicated by a white dot with a lowercase alphabetical order.
8 subsample points and 8 interpolation points, shown as black dots with uppercase letters. For each of these eight interpolation points, it is determined which of the four directions (vertical, horizontal, and diagonal directions) using the sample data of the subsample point is optimal for interpolation. FIG. 1 shows the four directions mentioned above regarding the interpolation points.

Since the optimal direction of interpolation is indicated by a 2-bit flag, eight flags are formed in one block. These eight hula knobs are subjected to majority logic, and the hula knob with the most number of hula knobs is determined as the representative flag of that block. Generally, in the case of a television image, directions with strong correlations approximately coincide within a small area within the same field, so that it is possible to determine representative flags for each block.

This representative flag and sub-sample point data are sent (
recorded). Thus, in this embodiment, eight subsample points and a two-bit flag are transmitted per block. The compression ratio in one embodiment when one sample is quantized to 8 bits is (8X8+2)/(8X4X4)=0.51625.

An encoder and decoder for implementing the high efficiency encoding method according to the present invention will be described below.

2 and 3 show the configuration of an encoder, and FIG. 2 shows a configuration that determines the quality of interpolation for each pixel data within one block of a digital television signal and generates a 2-bit flag. show.

FIG. 3 shows a configuration for thinning out processing within a block and forming a representative flag.

In FIG. 2, 1 indicates an input terminal for a digital television broadcast signal, 2 and 3 indicate one-line delay circuits, 4 to 14 indicate sample delay circuits having a delay amount of the sampling period, and 15 .16.17 and 18 are
An adder is shown. By supplying the input digital television signal to the one-line delay circuit 2.3 and the sample delay circuits 4'-14, one block of pixel data (see FIG. 1) is simultaneously output.

FIG. 2 shows a state in which the pixel data with alpha bend in FIG. 1 is output. That is, the pixel data of the interpolation point is outputted to the output of the sample delay circuit 9, and a flag regarding this interpolation point is formed. Adder 15
is supplied with pixel data at the subsample point a from the sample delay circuit 14 and pixel data at the subsample point from the input terminal 1. The adder 15 is configured to shift the addition output by 1 bit and generate a 1/2 output. The other adders 16, 17, and 18 are similarly configured to generate 172 addition outputs. The output (1) of the adder 15 is supplied to the flag generation circuit 19.

The adder 16 is supplied with the pixel data of the subsample point g from the sample delay circuit 5 and the pixel data of the subsample point g from the sample delay circuit 12. The output I2 of this adder 16 is supplied to a flag generation circuit 19.

The adder 17 is supplied with pixel data f at the subsample point from the sample delay circuit 7 and pixel data at the subsample point C from the line delay circuit 3. This adder 17
The output (3) is supplied to the flag generation circuit 19.

The adder 18 is supplied with pixel data at the sub-sample point e from the sample delay circuit 8 and pixel data at the sub-sample point d from the sample delay circuit 10. The output I4 of this adder 18 is supplied to a flag generation circuit 19.

Outputs 11 to I4 of the above-mentioned adders 15, 16, 17.18
is interpolation data in a total of four directions, vertical, horizontal, and diagonal directions, regarding the interpolation point. This interpolated data is expressed by the following equation.

1 1= (a+h)/2 I 2= (b+g)/, 2 13=(c+f)/2 1 4= (d+8)/2 The flag generation circuit 19 receives pixel data at the interpolation point from the sample delay circuit 9. The absolute value of the difference between the true value and each of the interpolated data 11 to I4 is calculated, and a 2-bit flag indicating the direction of interpolation in which this value is the smallest is generated. and pixel data are passed through registers 20 and 21, respectively, to output terminals 22.
23 and supplied to the next stage circuit (FIG. 3).

The calculation of the absolute value of the difference is expressed by the following equation.

X1=lD-111, X2=lD-I21°X3=lD
-1t, X4=1D-I41 Find the minimum value Y among these differences X1 to X4.

A flag is assigned depending on what is the minimum value. For example, the flags when (Y=X1) are (01), (Y=X2
), the flag is set as (11), (Y=X3) (7), (7), 7 ra/g is (1o), and (Y=X4), the flag is set as (00). .

Similar to the Hula knob for interpolation points above, 1
Flags for pixel data at each interpolation point within the block are generated in sequence. As shown in FIG. 3, a 2-bit flag is applied to a cascade of line delay circuits 24, 25.26. Sample delay circuits 27, 28, 29, and 30 having a delay time of two sampling periods are connected to the input and output sides of the line delay circuits 24, 25, and 26, respectively, and between the legs. Flags relating to each of the interpolation points within one block are simultaneously taken out at the input and output ends of each of the sample delay circuits 27-30.

Flags of these eight interpolation points are supplied to the majority logic circuit 31. The majority logic circuit 31 selects the flag with the largest number. For example, consider the case where the respective flags of interpolation points A to H are as follows.

A:00. s:oo, C:OO, D:00゜E:OO,
F:01. c:oo, H:01 In this example, the flag (00) is selected by the majority logic circuit 31 as the representative hula knob of that block. In other words, this block has a strong horizontal correlation, and it is determined that horizontal interpolation is optimal. The majority logic circuit 31 is configured to output a specific flag of the Jfi class, for example (10), when the decision of the majority logic cannot be determined because there are a plurality of identical flags.

A 2-bit flag output from majority logic circuit 31 is applied to a cascade of sample delay circuits 32, 33, and 34. The inputs and outputs of the sample delay circuits 32 to 34 and the outputs between stages are supplied to a register 35. This register 35 provides an 8-bit parallel output in which representative flags of each of the four blocks are parallelized. The output of this register 35 is written into the flag buffer memory 36.

The pixel data from the terminal 23 is transferred to the data buffer memory 3.
7 is written. Output data read from the flag buffer memory 36 and the data buffer memory 37 are input to the multiplexer 38. Thinning-out processing is performed during a write operation to the data buffer memory 37 or a read operation from the data buffer memory 37. The output data from the data buffer memory 37 is pixel data of sub-sample points whose data rate is lower than the original.

The multiplexer 38 adds 8-bit flag data consisting of representative flags of each of the four blocks at the beginning timing of the four blocks of pixel data. Highly efficient encoded output data is taken out to the output terminal 40 of the multiplexer 38 and recorded on a magnetic tape by a digital VTR. The order of the transmitted data may be the same as that of the television signal, or the pixel data of the sub-sample points and the representative flag may be transmitted together for each block.

8-bit parallel data reproduced by a digital VTR is supplied to the input terminals of the decoder shown at 5 and 41 in FIG. This input data is supplied to registers 42 and 43. By supplying a predetermined timing signal to each of the registers 42 and 43, the register 4
The flags for 4 blocks are taken into register 2 and
3, the pixel data of the sample point is taken in.

The output of register 43 is written to data buffer memory 44. The read output of the data buffer memory 44 is taken out to an output terminal 46 via a sample delay circuit 45.

The output of register 42 is supplied to multiplexer 47. This multiplexer 47 sequentially outputs flags (2 bits) for each block.

The 2-bit flag taken out at the output of multiplexer 47 is written into flag buffer memory 49 via sample delay circuit 48.

The output read from the flag buffer memory 49 in synchronization with the data at the sub-sample point is sent to the sample delay circuit 50.
It is taken out to the output terminal 51 via.

The terminals 46 and 51 are connected to a decoder shown in FIG. 5 that performs interpolation processing. Pixel data of sub-sample points from the terminal 46 are supplied to a cascade of line delay circuits 52 and 53 and a cascade of sample delay circuits 54 and 55 having a delay amount corresponding to the data rate from the terminal 46.

A sample delay circuit 56 is connected between the stages of line delay circuits 52 and 53. A cascade of sample delay circuits 57 and 58 is connected to the output of line delay 523.

These line delay circuits 52, 53 and sample delay circuits 54 to 58 simultaneously obtain pixel data of sub-sample points required for interpolating a 17" occ, for example, an interpolation point, as shown in the figure. .Line delay circuit 52
and pixel data e, f, g,
h is supplied to multiplexer 59.

Line delay circuit 53 and sample delay circuit 54゜57.
The pixel data a, b, c, d of the sub-sample points taken out at the respective outputs of 58 are supplied to a multiplexer 60. These multiplexers 59 and 60 are controlled by a 2-bit flag passed through a sample delay circuit 61. For example, when the flag is (00), the pixel data at subsample point e is selected by multiplexer 59, and the pixel data at subsample point d is selected by multiplexer 60.

The outputs of multiplexers 59 and 60 are provided to adder 62. The output of the adder 62 multiplied by 172 is supplied to one input terminal of the multiplexer 63. The sample delay circuit 5 is connected to the other input terminal of the multiplexer 63.
Pixel data of a sub-sample point from 6, for example d, is supplied.

The multiplexer 63 alternately selects and outputs interpolated data and subsample point data for each sample. The output of this multiplexer 63 is taken out to an output terminal 65 via a sample delay circuit 64.

In the embodiment described above, vertical, horizontal, and diagonal interpolation can be selected. However, the present invention can be applied even when interpolation is performed only in the vertical and horizontal directions.

〔Effect of the invention〕

According to this invention, the compression rate can be improved compared to conventional high-efficiency encoding methods. Therefore, it is possible to digitize high-definition television signals and record them on a VTR. Furthermore, the pixel data included in one block of a digital television signal has a strong correlation with each other.
Since the direction of interpolation coincides with respect to interpolation points within the same block, the image quality is hardly degraded compared to conventional high efficiency encoding methods.

[Brief explanation of the drawing]

Fig. 1 is a route map used to explain an embodiment of this invention, Figs. 2 and 3 are block diagrams of an encoder used in an embodiment of this invention, and Figs. 4 and 5 are block diagrams of an encoder used in an embodiment of this invention. A block diagram of a decoder used in one embodiment, FIG. 6 is a route diagram used to explain an example of a conventional high-efficiency encoding method, and FIG. 7 is a route diagram used to explain another example of a conventional high-efficiency encoding method. Rare on the route map: 1: Digital television signal input terminal, 19: Flag generation circuit, 31: Majority logic circuit, 40: Output terminal.

Claims (1)

[Scope of Claims] Interpolation points are thinned out among a plurality of pixel data included in a two-dimensional block of a digital television signal,
In the high-efficiency encoding method for television signals that transmits the remaining sample points after this thinning, it is determined for each interpolation point whether at least vertical interpolation or horizontal interpolation is better, and this determination is performed. a step of generating a flag indicating a result; a step of determining the majority logic of selecting the most flag among the flags for each of the interpolation points and generating a representative flag of the two-dimensional block; and a step of determining the sample point. and a step of using the representative flag as the encoded output of the two-dimensional block.