JP2583338B2 - Image coding device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image encoding apparatus for encoding image data with high efficiency, and more particularly to an image encoding apparatus useful for a video conference in which image data and audio data are transmitted simultaneously. The present invention relates to an encoding device.

[Conventional technology]

Conventionally, in this type of image encoding apparatus, a method is employed in which the delay between image data and audio data is fixedly delayed according to an average delay time of an image calculated in advance.

[Problems to be solved by the invention]

The conventional method of fixedly delaying the audio data described above is based on the movement of the image to be transmitted, the size and fineness of the subject, etc., which change the amount of information to be generated, and accordingly the amount of delay of the image changes. There is a disadvantage that the delay time between the image data and the audio data cannot be equalized.

[Means for solving the problem]

An image encoding apparatus according to the present invention comprises: an encoding circuit that encodes digital input image data with high efficiency; and outputs encoded image data. The image encoding apparatus temporarily stores the encoded image data and outputs the encoded image data at a constant speed. A buffer memory that outputs as a delayed image data and outputs a write clock and an encoded frame pulse, a voice delay circuit that delays digital input voice data in response to a voice delay control signal and outputs delayed voice data, A multiplexing circuit that multiplexes the delayed image data and the delayed audio data and outputs multiplexed data; and a multiplexing circuit that receives the write clock and the coded frame pulse and outputs the multiplexed data between the digital input image data and the delayed image data. An image delay amount calculation circuit for calculating an image delay amount, wherein the write clock and the encoded frame The image delay amount calculating circuit, comprising: means for calculating the amount of generated information between one encoded frame from the image data; and means for converting the amount of generated information into the amount of image delay. An audio delay control circuit that receives the encoded frame pulse and outputs the audio delay control signal, and calculates an average value of the image delay amount in a plurality of encoded frames from the image delay amount and the encoded frame pulse. And a means for converting the average value into the sound delay control signal.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an image encoding device according to one embodiment of the present invention.

Digital input image data a from the image data input terminal 1 is supplied to the predictive encoding circuit 2. The prediction encoding circuit 2 encodes the digital input image data a with high efficiency and supplies the encoded image data c to the buffer memory 3. The buffer memory 3 temporarily stores the encoded image data c, reads out the stored image data d at a constant speed, and supplies the read image data d to the multiplexing circuit 4 as delayed image data.

The buffer memory 3 further supplies the encoded frame pulse h to the audio delay control circuit 8 and the image delay amount calculating circuit 9, supplies the buffer memory occupation amount b to the predictive encoding circuit 2, and supplies the buffer memory write clock g. It is supplied to the image delay amount calculation circuit 9.

The image delay amount calculation circuit 9 calculates the image delay amount i for each encoded frame, and calculates the image delay amount i as the audio delay control circuit 8.
Supply to The audio delay control circuit 8 receives the image delay amount i and the coded frame pulse h, calculates an average value of the image delay amount i for each of N (N ≧ 2) coded frames, and calculates the audio delay control signal from the average value. f, and supplies the audio delay control signal f to the audio delay circuit 7.

On the other hand, digital input audio data e from the audio data input terminal 6 is supplied to the audio delay circuit 7. The audio delay circuit 7 delays the digital input audio data e by the audio delay control signal f and supplies the delayed audio data j to the multiplexing circuit 4.

The multiplexing circuit 4 includes the delayed image data d and the delayed audio data j.
And multiplexed data is output to the output terminal 5.

Referring to FIG. 2, the image delay amount calculating circuit 9 includes a counter 91, a register 92, and a ROM 93.

Referring to FIG. 7, image delay amount i of one encoded frame
The calculation method of will be described.

The range from one encoded frame to immediately before the next frame to be encoded is defined as one encoded frame. 1
The image delay amount i per coded frame is obtained by adding the fixed delay time p of the predictive coding circuit 2 and the delay time q that changes for each coding by the variable length coding and buffer memory 3.

The variable delay time q is a time from when writing of one frame of encoded image data to the buffer memory 3 is completed until reading of the written data is completed. Therefore, in order to obtain the variable delay time q, the amount of information generated between one encoded frame may be measured and divided by the transmission rate. From the above, the image delay amount i can be expressed by the following equation.

i = q + p = (S / R) + p (sec) (1) where R is the transmission rate and S is the amount of information generated between one encoded frame.

The generated information amount S is measured by the counter 91 and the register 92. The counter 91 is reset by the encoding frame pulse h, and counts the buffer memory write clock g. The register 92 captures the count number of the counter 91 immediately before resetting, and outputs the captured value to the ROM 93 as the generated information amount S between one encoded frame.

The calculation result of the image delay amount i by the equation (1) is written in the ROM 93 corresponding to the generated information amount S between one encoded frame. The ROM 93 stores an image delay amount i corresponding to the amount of generated information S between one encoded frame supplied from the register 92.
To the audio delay control circuit 8.

Referring to FIG. 3, the audio delay control circuit 8 includes an adder
81, a first register 82, a counter 83, a second register 84, a ROM 85, and a divider 86.

In this embodiment, the average value o of the image delay amount i for each of the N encoded frames is obtained by the following equation.

Here, N is an integer of 2 or more, and i (x) is the image delay amount i in the x encoded frame.

The adder 81 adds the image delay amount i supplied from the image delay amount calculation circuit 9 and the image delay amount up to one coded frame before supplied from the first register 82, and adds the result to the first register. Supply to 82. The counter 83 counts the encoded frame pulse h supplied from the buffer memory 3 N times, creates an N encoded frame period pulse 1 and outputs the pulse to the first register 82 and the second register 83.

The first register 82 holds the accumulated value of the image delay amount i and outputs the held value to the divider 86. Also, the first register 82 is reset by the N-encoded frame period pulse l. The divider 86 divides the output from the first register 82 by N, and outputs the result k of calculating the average value of the image delay amount to the second register 84.

The second register 84 takes in the average value calculation result k of the image delay amount i from the divider 86 once every N encoded frames by the N encoded frame period pulse 1 from the counter 83, and divides it into the average delay amount. Output to ROM85 as o.

The ROM 85 converts the average delay amount o into the audio delay control signal f according to the conversion table shown in FIG.

FIG. 5 shows an operation waveform diagram of the audio delay control circuit 8. In FIG. 5, the image delay amount i is parallel 8-bit data, and represents the value of the delay amount per encoded frame. The average value calculation result k is a value obtained by accumulating the image delay amount i between N encoded frames and calculating the average value. The average value calculation result k is fetched into the second register 84 by the N-encoded frame period pulse 1 and is output to the ROM 85 as the average delay amount o.

In this embodiment, since the average delay amount o indicates a value of “165”, the audio delay control signal f is converted into a value of “2” from FIG.

Referring to FIG. 4, the audio delay circuit 7 includes an n-bit shift register 71 and an m-input / 1-output selector 72. The digital input audio data e is supplied to an n-bit shift register 71. The n-bit shift register 71 converts the digital input voice data e from b1 to bm with different delay amounts.
And the m digital audio data b1 to bm are supplied to the m input / output selector 72.

The m input 1 output selector 72 selects one of m digital audio data b1 to bm having different delay amounts by controlling the audio delay amount control signal f, and outputs the delayed audio data j to the multiplexing circuit 4. .

FIG. 6 shows an n-bit shift register 71 of the audio delay circuit 7.
FIG. 7 is an operation waveform diagram in the case where is constituted by a 16-bit shift register and the m-input / one-output selector 72 is constituted by a 4-input / one-output selector.

The digital audio data b1 to b4 are data obtained by delaying the digital input audio data e by 4, 8, 12, and 16 bits, respectively. One of the four outputs is selected by the audio delay control signal f, and becomes the delayed audio data j.

As is apparent from FIG. 6, when the audio delay control signal f has a value of “0”, the digital audio data b1 is selected and “2” is selected.
When the value is 1, the digital audio data b3 is selected and the delayed audio data j is output.

As can be seen from this embodiment, when the user is listening to the voice and the amount of voice delay suddenly changes, the user feels unnatural. However, since the audio delay amount is changed as a result of averaging the image delay amount for a long time, there is no sudden change in the audio delay amount. Even if the user feels unnatural, there is no particular problem in a moment.
This sudden change in the audio delay amount can be suppressed by, for example, adopting a fade-in / fade-out method in which the audio signal before the change is faded out and the audio signal after the change is faded in.

〔The invention's effect〕

As described above, the present invention controls the amount of delay of an audio signal by the amount of image delay.
Even if the amount of information generated due to the size or fineness of the subject increases or decreases and the image delay amount changes, the delay time between the image data and the audio data can be made equal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an image encoding apparatus according to one embodiment of the present invention, FIG. 2 is a block diagram showing a configuration of an image delay amount calculating circuit in FIG. 1, and FIG. FIG. 4 is a block diagram showing the configuration of the audio delay control circuit of FIG. 1, FIG. 5 is a timing chart for explaining the operation of the audio delay control circuit, FIG.
FIG. 6 is a timing chart for explaining the operation of the audio delay circuit, FIG. 7 is a timing chart for explaining the image delay amount calculating method, and FIG. 8 is a conversion chart prepared in the ROM in FIG. It is a figure showing the contents of a table. 1 ... image data input terminal, 2 ... predictive coding circuit, 3
... Buffer memory, 4 multiplexing circuit, 5 output terminal, 6 audio data input terminal, 7 audio delay circuit,
8 audio delay control circuit 9 image delay amount calculation circuit
71: n-bit shift register, 72: m input, one output selector, 81: adder, 82: register, 83: counter, 84: register, 85: ROM, 86: divider, 91
... Counter, 92, register, 93, ROM, a, digital input image data, b, buffer memory occupancy, c, encoded image data, d, delayed image data,
e: Digital input audio data, f: Audio delay control signal, g: Buffer memory write clock, h:
Encoded frame pulse, i... Image delay amount, j... Delayed audio data, k... Average value calculation result, l... N encoded frame period pulse, o.

Claims (1)

(57) [Claims] An encoding circuit for encoding digital input image data with high efficiency and outputting encoded image data; temporarily storing the encoded image data; and converting the stored image data into delayed image data at a constant speed. A buffer memory that outputs a write clock and an encoded frame pulse, a voice delay circuit that delays digital input voice data in response to a voice delay control signal and outputs delayed voice data, A multiplexing circuit that multiplexes data and the delayed audio data and outputs multiplexed data; an image delay amount between the digital input image data and the delayed image data that receives the write clock and the encoded frame pulse. And an image delay amount calculating circuit for calculating 1 from the write clock and the encoded frame pulse. Means for calculating the amount of information generated between coded frames, and means for converting the amount of generated information to the amount of image delay, the image delay amount calculation circuit, the image delay amount and the coded frame pulse, Receiving
An audio delay control circuit that outputs the audio delay control signal, a unit that calculates an average value of the image delay amounts in a plurality of encoded frames from the image delay amount and the encoded frame pulse, An image delay control circuit comprising: means for converting the signal into the audio delay control signal.