JP3071579B2 - Encoding apparatus and decoding apparatus for two-screen multiplexed moving image - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a moving picture encoding apparatus that multiplexes and encodes various kinds of moving picture signals and a moving picture decoding apparatus that receives and decodes image data encoded by the moving picture encoding apparatus. Encoding apparatus that encodes two types of moving image signals into two-screen image data obtained by performing frame time division multiplexing on two types of moving image signals, and two types of moving image data obtained by performing two-screen image data frame time division multiplexed by one decoder The present invention relates to a video decoding device that decodes a signal.

[0002]

2. Description of the Related Art As shown in FIG. 11, there is a system for displaying two types of moving images on one screen. Here, one of the two types of moving images is referred to as screen A, and the other is referred to as screen B. Such a system has a video encoding device on the transmission side and a video decoding device on the reception side. In a conventional system, a moving image encoding device performs encoding processing by regarding two types of moving images as one type of moving image, and a moving image decoding device converts two types of moving images into one type of moving image. The decryption process was performed assuming that it was.

FIG. 10A shows an example of a predictive coding apparatus using inter-frame prediction as a conventional moving picture coding apparatus. FIG. 10B shows an example of a conventional moving picture decoding apparatus using inter-frame prediction. The example of the prediction decoding apparatus used is shown.

Referring to FIG. 10A, a conventional moving picture coding apparatus includes a coding circuit 100 and a buffer memory 10.
7 and an encoding control circuit 108. The encoding control circuit 108 controls the quantization characteristics and the like of the encoding circuit 100 according to the occupancy so that the buffer memory 107 does not overflow or underflow. In the encoding circuit 100, the selector 102 normally selects an image signal from the input terminal 101 according to the control of the encoding control circuit 108, and
When the occupancy is high, the output of the frame memory 105 is selected to perform frame thinning. The output signal of the selector 102 is subtracted by the subtractor 110 from the predicted value from the frame memory 105. The quantizer 103 includes a subtractor 110
Is quantized. The quantized prediction error signal is variable-length coded by the variable-length coding circuit 106 and then written to the buffer memory 107. The encoded image signal stored in the buffer memory 107 is output to an output terminal 1
09 and multiplexed audio information (not shown). The output of the quantizer 103 is the inverse quantizer 104
, And supplied to one input terminal of the adder 111. The prediction signal from the frame memory 105 is supplied to the other input terminal of the adder 111, and the adder 111 generates a local decoded signal. The locally decoded signal is written to the frame memory 105. Quantizer 1
03 and the quantization characteristics of the inverse quantizer 104 are controlled by the encoding control circuit 108. When the occupation ratio of the buffer memory 107 is high, coarse quantization is performed, and when it is low, fine quantization is performed. Thus, the conventional encoding device has
Even when there are two types of images on a screen, inter-frame predictive coding has been performed for each screen.

Referring to FIG. 10B, a conventional moving picture decoding apparatus comprises a decoding circuit 200 and a buffer memory 2.
02. The buffer memory 202 accumulates the written data until the image data received from the input terminal 201 can be sufficiently decoded. When it is determined that the image data can be decoded, the buffer memory 202 reads and outputs one frame of image data. In the decoding circuit 200, the variable length decoding circuit 203 restores the original prediction error signal from the variable length code of the image data output from the buffer memory 202.
The prediction error signal is inversely quantized by the inverse quantizer 204 and supplied to one input terminal of the adder 205. Adder 20
5, the other input terminal is supplied with a prediction signal from the frame memory 206, and the adder 205 generates a decoded image signal. The decoded image signal is output from the output terminal 207 and written to the frame memory 206. As described above, the conventional decoding apparatus performs inter-frame predictive decoding on a screen in which two types of images are synthesized on one screen in units of one screen.

[0006]

As described above, in the conventional encoding apparatus, even if one screen is composed of two types of moving images, the same encoding as that of encoding one type of moving image is performed. Are performed, the two moving images mutually affect the encoding of the other moving images. That is, the quantization characteristic is determined by the occupancy of the buffer memory, that is, the increase / decrease of the information amount of the coded signal per one screen, and does not consider the difference in the coded signal information amount of each moving image. For this reason, even if only one of the moving images largely moves, there is a problem that the quantization characteristic of the entire screen is roughly controlled.

[0007] Further, in the conventional decoding apparatus, one screen has two screens.
Even if it is composed of different types of moving images, the same decoding is performed as when one type of moving image is encoded, so that two moving images affect the decoding of other moving images. That is, in the coding apparatus on the transmission side, the quantization characteristic is determined by the occupancy of the buffer memory on the transmission side, that is, by increasing or decreasing the information amount of the coded signal per one screen. No difference in volume was taken into account. For this reason, in the decoding device on the receiving side, there is a problem that the quantization characteristic of the entire screen is roughly decoded even if only one of the moving images largely moves.

Accordingly, a technical object of the present invention is to provide an encoding apparatus capable of alternately and efficiently encoding two moving images in frame units when multiplexing and encoding moving images of two different pictures. Is to do.

Another technical object of the present invention is to multiplex two kinds of moving pictures of different patterns, receive and decode an encoded digital signal, and alternate two image data according to the received signal. Another object of the present invention is to provide a decoding device which can efficiently decode the original video and obtain the original two moving images.

[0010]

According to a first aspect of the present invention, there is provided an apparatus for encoding a two-screen multiplexed moving image, comprising a first screen and a second screen.
Image signal of two different patterns consisting of two screens
A digital video signal in which a first screen and a second screen are alternately multiplexed at every field time , and alternately inputted at every frame time. Convert to multiplexed two-screen multiplexed image data,
A format conversion circuit for outputting a two screen identification signal that identifies <br/> this dual-screen multiplexed image data and multiplexed two-stroke surface, dual-screen superimposed image data outputted from the format conversion circuit And an encoding permission signal, and when the encoding permission signal is input, the two-screen multiplexed image data is converted in accordance with an encoding parameter in accordance with an encoded image identification signal.
Te encoding, an encoding circuit for outputting the code length information of the encoded image data and encoded image data, and outputs the encoded image data output from the encoding circuit temporarily in memory to a constant speed, A buffer memory for outputting data occupancy information; a code length information output from an encoding circuit; and a generated information amount calculation circuit for calculating the generated information amount of a frame immediately after encoding. Based on the generated information amount output from the amount calculation circuit, the encoding circuit
A coding parameter control circuit for controlling the coding parameters necessary for the coding of the data, and determining whether or not the next frame can be coded based on the occupancy information immediately before the start of coding output from the buffer memory, and performing format conversion. Based on the two-screen identification signal output from the circuit,
The frame to be encoded is identified so that the frame of the first screen and the frame of the second screen are alternately encoded .
And an encoding timing control means for generating an encoded image identification signal and an encoding permission signal.

According to a second aspect of the present invention, there is provided an encoding apparatus for a two-screen multiplexed moving picture, wherein the encoding circuit is further provided.
Calculates the first locally decoded image data corresponding to the first screen
A first frame memory for storing and a second frame corresponding to the second screen are stored.
Frame storing second locally decoded image data
Obtained by the memory and the encoding timing control means.
Encoding prediction value selecting means for selecting encoding prediction values from the first and second frame memories in frame units in accordance with the encoding image identification signal, and encoding the prediction values selected by the encoding prediction value selecting means Encoding means for encoding the two-screen multiplexed image data according to the encoding parameter output from the parameter control circuit and outputting the encoded data,
Multiplexing for multiplexing encoded data , an identification signal indicating whether one of the first screen and the second screen has been encoded, and an encoding parameter, and outputting encoded image data
Means .

[0012] In the coding apparatus of the dual-screen multiplexed video of the invention of claim 3, wherein, in addition to the configuration of claim 1, encoding para
The meter control circuit temporarily holds the amount of generated information calculated by the generated information amount calculating circuit for each of the first screen and the second screen, and stores the stored amount of generated information and the encoding parameter at the time of previous encoding. Coding parameter control means for determining coding parameters separately for a first screen and a second screen based on the first screen and the second screen
If, then either frame to be encoded encoding parameter of the first screen or the second image <br/> face their <br/> respectively determined by the coding parameter control means depending on whether And encoding parameter selection means for selecting

[0013] A two-screen multiplexed moving image according to the fourth aspect of the present invention.
'S decrypted device, or two screens between the first screen and the second screen
Multiplexes and encodes two different types of image signals
Video that receives the converted digital signal and decodes it into an image signal
An image decoding apparatus, comprising: a buffer memory that writes input coded image data at a constant speed, temporarily stores the coded image data, and outputs coded image data and an image synchronization signal; and a code output from the buffer memory. image data decoded by entering a decoding circuit for outputting the multiplexed decoded image data and the secondary screen identification signal identifying two screenful were, the image data output from the decoding circuit And decodes the first screen and the second screen with the decoding timing signal.
Multiplexing and shaping alternately according to the first screen and the second screen
Two-screen multiplexing / shaping memory for outputting image data, and two-screen multiplexing image data output from the two-screen multiplexing / shaping memory type and outputs the dual-screen multiplexed image data, and format inverse conversion circuit for inversely converting the multiplexed image signals alternately every field time, from the image synchronization signal decoding circuit output from the buffer memory And input the first two-screen identification signal based on the two-screen identification signal .
And decoding timing control means for generating a decoding timing signal so as to alternately decode the frame of the second screen and the frame of the second screen .

According to a fifth aspect of the present invention, in addition to the configuration of the fourth aspect, the decoding circuit stores the first decoded image data for the first screen. You
A first frame memory and a second decoding for a second screen
A second frame memory for storing image data;
From the image data, either the first screen or the second screen
An identification signal indicating the frame and the encoding parameter used for encoding.
Means for separating the parameter and the encoded data, and an identification signal
Predicted value selection means for selecting the predicted values decoded from the first and second frame memories in frame units according to
When, is intended to include a means for decoding coded data according to the predictive value and the coding parameters selected by the decoded prediction value selection means.

According to a sixth aspect of the present invention, in addition to the configuration of the fourth aspect, the two-screen multiplexing / shaping memory further comprises a decoding unit which obtains the decoding obtained by the decoding timing control signal . The first screen according to the timing signal
And the second screen are once written to separate first and second frame memories, respectively, and the first and second frame memories are
And means for selecting such that the first screen and the second screen read out from the first screen are alternately multiplexed.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1A is a block diagram showing a two-screen multiplexed moving picture coding apparatus according to an embodiment of the present invention.
FIG. 1B is a block diagram showing a two-screen multiplexed video decoding device according to an embodiment of the present invention.

Referring to FIG. 1 (A), this encoding apparatus converts a digital video signal a in which two types of screens are multiplexed every field time inputted from input terminal 1 into two frames every frame time. A format conversion circuit 2 that converts the image data into screen-multiplexed image data b and outputs a two-screen identification signal c indicating one of two screens (hereinafter referred to as A-screen and B-screen); And an encoding circuit 3 for outputting encoded data d and a code length e of the encoded data d. The encoded data d output from the encoding circuit 3 is temporarily stored and encoded at a constant speed. Data f
And a buffer memory 4 for outputting to the output terminal 8. The buffer memory 4 also outputs the occupation amount g of the data stored in the memory.

The encoding apparatus further includes an encoding timing generation circuit 5 including encoding timing control means, an encoding parameter control circuit 6 including encoding parameter control means and encoding parameter selection means, And an information amount calculation circuit 7. The generated information amount calculation circuit 7 receives the code length e output from the encoding circuit 3 and adds the code length e generated in each frame period to calculate the generated information amount h. Output to The encoding timing generation circuit 5 receives the two-screen identification signal c output from the format conversion circuit 2 and the buffer memory occupancy g output from the buffer memory 4 and outputs the encoding permission signal i to the encoding circuit 3. And outputs the A screen selection signal k, the B screen selection signal 1 and the coded screen identification signal m to the coding circuit 3 and the coding parameter control circuit 6. Then, the coding parameter control circuit 6 controls the coding parameters based on the generated information amount h and the coding parameters of the frame, and outputs the A screen selection signal k and the B screen selection signal l.
A to be encoded next according to
The encoding parameter n of the frame of the screen or the screen B is determined and output to the encoding circuit 3.

The encoding timing generation circuit 5 compares the buffer memory occupancy g immediately before the start of encoding output from the buffer memory 4 with the determination threshold value, and determines whether the next frame can be encoded. Further, based on the two-screen identification signal c output from the format conversion circuit 2, the encoding permission signal i is controlled so as to alternately encode the frame of the screen A and the frame of the screen B, Also, A
The screen selection signal k, the B screen selection signal 1 and the coded screen identification signal m are also controlled. Encoding circuit 3
Encodes the image data b of the frame of the screen A or the screen B in which the encoding permission signal i is turned on according to the encoding parameter n.

Referring to FIG. 1B, a coded image reception signal p input from an input terminal 10 is written at a constant speed, temporarily stored, and then received coded data q and the coded data q of the coded data q. A buffer memory 11 that outputs a synchronization signal r indicating the beginning and coded data q are input and decoded,
A decoding circuit 12 that outputs a decoded image data s and a two-screen identification signal v indicating either of two screens (A screen and B screen), and the decoded image data s output from the decoding circuit 12 Screen A and screen B are stored separately separately,
A two-screen multiplexing / shaping memory 14 for outputting two-screen multiplexed image data t in which the A-screen and the B-screen are alternately multiplexed for each frame, and a two-screen multiplexing output from the two-screen multiplexing / shaping memory 14 Format image data t is input, and two screens (screen A and screen B) multiplexed for each frame time are converted into a digital video signal u in which two types of images are multiplexed for each field time. Conversion circuit 15
And a decoding timing generation circuit 13 including decoding timing control means. The decoding timing generation circuit 13 includes a synchronization signal r output from the buffer memory 11 and a two-screen identification signal v output from the decoding circuit 12.
And outputs the A-screen selection signal w and the B-screen selection signal y to the decoding circuit 12 and the two-screen multiplexing / shaping memory 14.

FIG. 2 is a block diagram showing a configuration example of the encoding timing generation circuit 5 in FIG. The encoding timing generation circuit 5 includes a comparator 51, a selector 52, an exclusive OR (EXOR) gate 53, first and second registers 54 and 55, a pattern generator 56, and first and second AND gates 57. And 58.

In FIG. 2, comparator 51 compares buffer memory occupancy g with a predetermined threshold value. For example, when buffer memory occupancy g is smaller than the threshold value, logic level "1" is set. The comparison result 5a at the logic "0" level is output. The first register 54 holds the two-screen identification signal c at the timing of the first register clock 5d and outputs the same as the pre-encoded screen identification signal 5b. EXO
The R gate 53 receives the two-screen identification signal c at one input terminal and the pre-encoded screen identification signal 5b at the other input terminal, and selects the exclusive OR result as the encoding permission selection signal 5c by the selector 52. Supply to terminal. That is, the encoding permission selection signal 5c is at the logic "1" level when the two-screen identification signal c and the previous encoding screen identification signal 5b have different values, and at the same value when they are the same value. The selector 52 outputs the output of the comparator 51 when the encoding permission selection signal 5c is at the logic “1” level, and outputs the output when the encoding permission selection signal 5c is at the logic “0” level.
And outputs it as an encoding permission signal i. As a result, the A screen (the two-screen identification signal c is at the logical “0” level)
And the B-screen (the two-screen identification signal c is at the logic “1” level) can be controlled by the encoding permission signal i so as to be alternately encoded.

The pattern generator 56 receives the two-screen identification signal c, the image data b, and the encoding permission signal i, and receives first and second pulse signals corresponding to the first pixel and the last pixel of each frame, and A, A screen selection signal k and a B screen selection signal 1 are generated.

The encoding permission signal i is input to one input terminal of the first and second AND gates 57 and 58. The first and second pulse signals from the pattern generator 56 are input to the other input terminals of these AND gates, respectively. The output of the first AND gate 57 is used as the first register clock 5d as the second register clock. Is supplied to the first and second registers 54 and 55 as a second register clock 5e, respectively. The second register 55 holds the two-screen identification signal c at the timing of the second register clock 5e and outputs it as an encoded screen identification signal m.

FIG. 3 is a block diagram showing an example of the configuration of the coding parameter control circuit 6 in FIG. The encoding parameter control circuit 6 includes third and fourth registers 61 and 63, a parameter ROM (A) 62, a parameter ROM (B) 64, and a second selector 65.

In FIG. 3, a third register 61 stores a generated information amount h from the generated information amount calculation circuit 7 and a parameter R.
The coding parameter 6b of the screen A output from the OM (A) 62 is held by the screen selection signal l. Similarly,
The fourth register 63 stores the generated information amount h and the parameter RO.
The coding parameter 6e of the B screen output from the M (B) 64 is held by the A screen selection signal k. The parameter ROM (A) 62 stores, based on the generated information amount 6a and the encoding parameter 6c for the previously encoded A screen output from the third register 61, the encoding parameter 6b of the next A screen to be encoded. Output. Similarly, the parameter ROM (B) 64 encodes the next screen to be encoded based on the generated information amount 6d and the encoding parameter 6f for the previously encoded screen B output from the fourth register 63. The parameter 6e is output. Second selector 65
Selects one of the coding parameter 6b for screen A and the coding parameter 6e for screen B according to the coding screen identification signal m, and outputs the selected parameter as a coding parameter n. When the generated information amount is large for each of the A and B screens, the encoding parameter n is coarser than the previous parameter. For example, the quantization step width is made coarse. Is set in advance in the parameter ROM so that
(A) 62 and parameter ROM (B) 64.

FIG. 4 shows the encoding circuit 3 in FIG.
FIG. 3 is a block diagram illustrating a configuration example of FIG. The encoding circuit 3 includes a third selector 31, a quantizer 32, an inverse quantizer 33, a variable length encoding circuit 34, a frame memory (A) 35, a frame memory (B) 36, a fourth selector 37, It comprises a multiplexing circuit 38, a subtractor 39 and an adder 40.

In FIG. 4, the third selector 31 selects one of the two-screen multiplexed image data b and the prediction signal 3b according to the encoding permission signal i. In the present embodiment, when encoding, that is, when the encoding permission signal i is at the logical “1” level, the third selector 31 sets the two-screen multiplexed image data b
Select The selected signal 3a is input to one input terminal of the subtractor 39. The subtractor 39 selects the selected signal 3
The difference between a and the prediction signal 3b is calculated, and the result of the subtraction is input to the quantizer 32 as a prediction error signal. The quantizer 32 quantizes the prediction error signal according to the encoding parameter n, and supplies the quantization result to the inverse quantizer 33 and the variable length encoding circuit 34 as a quantization level number 3c. The inverse quantizer 33 inversely quantizes the quantization level number 3c into a prediction error signal and outputs the result to the adder 40. The adder 40 adds the prediction signal 3b and the dequantized prediction error signal, and outputs the addition result as local decoded image data 3d. The local decoded image data 3d is input to a frame memory (A) 35 and a frame memory (B) 36. The variable length coding circuit 34 performs code conversion on the quantization level number 3c by entropy coding to perform compression coding, and outputs a code length e and code data 3g when the code conversion is performed. Multiplexing circuit 38
Multiplexes the encoding parameter n and the encoded screen identification signal m with the encoded data 3g, and outputs the multiplexed data as encoded data d.

The writing of the locally decoded image data 3d to the frame memory (A) 35 is performed when the A-screen selection signal k is at the logic "1" level. Similarly, the writing of the locally decoded image data 3d to the frame memory (B) 36 is performed when the B screen selection signal 1 is at the logic "1" level. Then, one of the A screen prediction signal 3e read from the frame memory (A) 35 and the B screen prediction signal 3f read from the frame memory (B) 36 is selected by the selector 37 in accordance with the encoded image identification signal m. The selected signal is supplied to the subtractor 39 as a prediction signal 3b for the next encoded frame. In this embodiment, when the coded screen identification signal m is at the logical “0” level, the selector 37 outputs the A screen prediction signal 3 e to the logical “1”.
At the level, the B screen prediction signal 3f is selected.

Next, the operation of the encoding apparatus shown in FIG. 1A will be described with reference to the timing chart shown in FIG.

FIG. 5A shows a field two-screen multiplexed digital image signal a, and "A" and "B" respectively denote field-multiplexed A and B screens. The two-screen multiplexed digital image signal a is decimated by one frame by the format conversion circuit 2 and, as shown in FIG.
Is converted to The format conversion circuit 2 also outputs a two-screen identification signal c indicating whether the two-screen multiplexed image data b is the A-screen or the B-screen as shown in FIG.

FIG. 5D shows the buffer memory occupancy g, which increases by encoding and decreases at a constant speed during the non-coding period. The encoding permission signal i at this time is shown in FIG.
It is determined as in (5). In FIG. 5 (5), the broken line indicates that the modification has been made so that the A screen and the B screen are alternately encoded.

FIG. 5 (6) shows the waveform of the register clock 5d in the encoding timing generation circuit 5, and FIG.
(7) shows the waveform of the register clock 5e.
FIG. 5 (8) shows that the two-screen identification signal c is
The pre-code screen identification signal 5b sampled at d is shown. FIG. 5 (9) shows a code screen identification signal m obtained by sampling the two-screen identification signal c with the register clock 5e. FIG. 5 (10) shows an output obtained when an exclusive OR of the two-screen identification signal c and the pre-coded screen identification signal 5b is obtained, and an encoding permission selection signal used for correcting the encoding permission signal. 5c is shown.

FIG. 5 (11) shows the generated information amount h of the encoded frame. The code length e output from the coding circuit 3 is input, and the amount of generated information h (in the figure, I _A0 , I _B0 , I _A1 ,
_IB1 ).

FIG. 5 (12) shows the B screen selection signal 1 output from the encoding timing generation circuit 5, which is input to the encoding parameter control circuit 6 and the encoding circuit 3. FIG. 5 (13) shows the A-screen selection signal k output from the encoding timing generation circuit 5, which is input to the encoding parameter control circuit 6 and the encoding circuit 3.

In the coding parameter control circuit 6, FIG. 5 (14) shows the generated information amount 6a of the A screen obtained by sampling the generated information amount h with the B screen selection signal l (I in the figure).
_A0, shown by the I _A1) shows the. 5 (15), the generated information amount 6d of B screen generated information quantity h and sampled at A screen selection signal k (in Fig., Indicated by _{I B1, I B0, I B1} )
Is shown. FIG. 5 (16) shows an A-screen coding parameter 6c (P in FIG. 5) obtained by sampling the coding parameter 6b obtained when the previous A-screen was coded by the B-screen selection signal l.
_A0, shown by P _A1) shows the. FIG. 5 (17) shows a B-screen coding parameter 6f obtained by sampling the coding parameter 6e obtained when the previous B-screen was coded using the A-screen selection signal k.
(In the figure, denoted by P _B-1 , P _B0 , and P _B1 ). FIG. 5 (18) shows a case in which the generated information amount 6a of the A-screen and the A-screen coding parameter 6c are input to the parameter ROM (A) 62, and the coding parameter 6b of the next frame to be output (see FIG. P _A1 , P _A2 ), the B-screen generated information amount 6d and the B-screen coding parameter 6f are input to the parameter ROM (B) 64, and the coding parameter 6e of the next frame to be coded (output). In the figure,
P _B0 and P _B1 ) are input to the selector 65, and the encoding parameter n selected and output by the encoded screen identification signal m is shown.

FIG. 6 is a block diagram showing a configuration example of the decoding timing generating circuit 13 in FIG. The decoding timing generation circuit 13 includes the frame synchronization generation circuit 1
31, gate circuit (A) 132, gate circuit (B) 13
3, and an inverting gate 134.

In FIG. 6, the frame synchronization generating circuit 13
1 receives the synchronization signal r output from the buffer memory 11, generates and outputs a frame synchronization signal 13a in synchronization with the frame period of the image and only for a valid period during which the received encoded data is decoded. This frame synchronization signal 13
a is the gate circuit (A) 132 and the gate circuit (B) 13
Enter 3 and so on. The two-screen identification signal v output from the decoding circuit 12 is input to an inversion gate 134, where it is converted to a two-screen identification inversion signal 13b. Gate circuit (A) 13
2 is a frame synchronization signal 13a and a two-screen identification inversion signal 1
3b, and when the two-screen identification inversion signal 13b is at the logic "1" level, the signal of the frame synchronization signal 13a as it is, and when it is at the logic "0" level, the signal of the logic "0" level is selected. Output as signal w. Similarly,
The gate circuit (B) 133 receives the frame synchronization signal 13a and the two-screen identification signal v, and when the two-screen identification signal v is at the logic "1" level, converts the frame synchronization signal 13a as it is to the logic "0". When the signal is at the level, a signal of logic "0" level is output as the B screen selection signal y.

FIG. 7 shows the decoding circuit 1 in FIG.
2 is a block diagram illustrating a configuration example of FIG. Decoding circuit 12
Is a separation circuit 121, a variable length decoding circuit 122, an inverse quantizer 123, an adder 124, a frame memory (A) 12
5, frame memory (B) 126, and selector 12
7 is comprised.

In FIG. 7, a separating circuit 121 converts a coded data q into a two-screen identification signal v and a coding parameter 12.
g, and outputs coded data q, two-screen identification signal v, and coding parameter 12g. Variable length decoding circuit 1
Numeral 22 reversely expands and decodes the encoded data 12a that has been subjected to code conversion by entropy encoding and compression-encoded, and outputs a quantization level number 12b. The inverse quantizer 123 inversely quantizes the quantization level number 12b into the prediction error signal 12c according to the encoding parameter 12g, and supplies the prediction error signal 12c to one input terminal of the adder 124. The other input terminal of the adder 124 has a selector 1
The prediction signal 12d output from 27 is supplied, and the adder 124 generates decoded image data s. The decoded image data s is input to the frame memory (A) 125 and the frame memory (B) 126.

The writing of the decoded image data s into the frame memory (A) 125 is performed when the A image selection signal w is at the logic "1" level. Similarly, writing of the decoded image data s to the frame memory (B) 126 is performed when the B image selection signal y is at the logical “1” level. Then, the A screen prediction signal 12 e read from the frame memory (A) 125 and the frame memory (B) 12
The B-screen prediction signal 12f read out from 6 is supplied to the selector 127. The selector 127 selects one of the A-screen prediction signal 12e and the B-screen prediction signal 12f according to the two-screen identification signal v, and outputs the selected signal as a prediction signal 12d of a frame to be decoded next. In this embodiment, the selector 127 selects the A-screen prediction signal 12e when the two-screen identification signal v is at the logic “0” level, and selects the B-screen prediction signal 12f when the two-screen identification signal v is at the logic “1” level.

FIG. 8 is a block diagram showing an example of the configuration of the two-screen multiplexing / shaping memory 14 in FIG. The two-screen multiplexing / shaping memory 14 includes a frame memory (C) 14
1, a frame memory (D) 142, a selection circuit 143, and a selection signal generation circuit 144.

In FIG. 8, the decoded image data s is stored in a frame memory (C) 141 and a frame memory (D) 142.
And enter When the A-screen selection signal w is at the logical “1” level, the data of the A-screen in the decoded image data s is output as it is while being written to the frame memory (C) 141. When the A-screen selection signal w is at the logic “0” level, the A-screen data written for each frame is repeatedly read from the frame memory (C) 141. Similarly, when the B screen selection signal y is at the logical “1” level, the data of the B screen in the decoded image data s is output as it is while being written to the frame memory (D) 142. When the B screen selection signal y is at the logical “0” level, the B screen data written for each frame is repeatedly read from the frame memory (D) 142. The decoded image data 14a of screen A read from the frame memory (C) 141 and the decoded image data 14b of screen B read from the frame memory (D) 142 are selected by the selection circuit 143.
Supplied to The selection signal generation circuit 144 receives the B screen selection signal y, and outputs a screen switching signal 14c for alternately selecting the A screen and the B screen for each frame. Selection circuit 14
Reference numeral 3 selects the decoded image data 14a of the A screen and the decoded image data 14b of the B screen for each frame according to the screen switching signal 14c, and newly outputs two-screen multiplexed image data t. In the present embodiment, the B screen selection signal y is input to the selection signal generation circuit 144, but the A screen selection signal w may be input.

Next, the operation of the decoding apparatus shown in FIG. 1B will be described with reference to the timing chart shown in FIG.

FIG. 9A shows the coded data p to be inputted. "A ₁ " and "A ₂ " indicate the A screen, and "B ₀ " and "B ₁ " indicate the B screen. FIG. 9 (2) shows the buffer memory occupancy, which increases as the coded data p is input at a constant speed, and when data is read from the buffer memory 11 and it is determined that there is no underflow, one frame is read. Being reduced. When the encoded data is read from the buffer memory 11, the buffer memory 11
Outputs a synchronization signal r indicating the head of the encoded data as shown in FIG. 9 (3).

In the decoding timing generation circuit 13,
FIG. 9 (4) shows the waveform of the frame synchronization signal 13a, and FIG. 9 (5) shows the two-screen identification signal v. FIG. 9 (6)
Indicates an A-screen selection signal w, and when the two-screen identification signal v is at the logical "0" level, a frame synchronization signal is output. FIG. 9 (7) shows the B screen selection signal y, and the two-screen identification signal v
Is a logical "1" level, a frame synchronization signal is output.

FIG. 9 (8) shows the decoded image data s. The decoded image data s indicates the A screen (indicated by A ₀ and A ₁ in the figure) when the A screen selection signal w is at the logic “1” level, and B when the B screen selection signal y is at the logic “1” level 5 shows a screen (in the figure, _denoted by B ₀ and B ₁ ). When the A-screen selection signal w and the B-screen selection signal y are both at the logic "0" level, indefinite data is output, or decoded screen data is repeatedly output for each frame.

In the two-screen multiplexing / shaping memory 14, FIG. 9 (9) shows decoded image data 14a of A-screen (A ₀ , A ₀ ,
Shows are shown in A _1). FIG. 9 (10) shows decoded image data 1 of screen B output from frame memory (D) 142.
4b (shown as B _-1 , B ₀ , and B ₁ in the figure).
FIG. 9 (11) shows the screen switching signal 14c output from the selection signal generation circuit 144. The selection circuit 143 selects the screen A when the screen switching signal 14c is at the logic “0” level, and selects the screen B when the screen switching signal 14c is at the logic “1” level. FIG.
(12) shows the result of alternately selecting the decoded image data 14a of the A screen and the decoded image data 14b of the B screen by the screen switching signal 14c, that is, the two-screen multiplexed image data t. FIG. 9 (13) shows a digital video signal u converted from the two-screen multiplex format in frame time units to the two-screen multiplex format in field time units by the format inverse conversion circuit 15.

[0050]

As described above, according to the encoding apparatus of the present invention, it is determined whether or not the next frame can be encoded based on the occupancy information immediately before the start of encoding output from the buffer memory. Further, based on the two-screen identification signal output from the format conversion circuit, the encoding timing signal and the encoding permission signal are controlled so that the frame of the screen A and the frame of the screen B are alternately encoded.
There is an effect that efficient predictive coding can be performed without deteriorating the following performance of each of the two screens (A and B).

Further, according to the decoding apparatus of the present invention, the two-screen identification signal is separated from the transmitted coded data, and the frame of the A screen and the frame of the B screen are separated based on the two-screen identification signal. Since the decoding timing signal is controlled so as to be alternately decoded, there is an effect that efficient predictive decoding can be performed without impairing the following performance of the two screens (A and B).

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a two-screen multiplexed moving picture encoding / decoding apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an encoding timing generation circuit in FIG.

FIG. 3 is a block diagram illustrating a configuration of an encoding parameter control circuit in FIG.

FIG. 4 is a block diagram illustrating a configuration of an encoding circuit in FIG.

FIG. 5 is a timing chart for explaining the operation of the encoding device for two-screen multiplexed moving images in FIG.

FIG. 6 is a block diagram showing a configuration of a decoding timing generation circuit in FIG.

FIG. 7 is a block diagram illustrating a configuration of a decoding circuit in FIG.

FIG. 8 is a block diagram showing a configuration of a two-screen multiplexing / shaping memory in FIG. 1 (B).

FIG. 9 is a timing chart for explaining the operation of the decoding device for two-screen multiplexed moving images in FIG. 1 (B).

FIG. 10 is a block diagram showing a configuration of a conventional two-screen split combined moving image encoding / decoding apparatus.

FIG. 11 is an explanatory diagram showing a conventional two-screen split composite screen.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input terminal 2 Format conversion circuit 3 Encoding circuit 4 Buffer memory 5 Encoding timing generation circuit 6 Encoding parameter control circuit 7 Generated information amount calculation circuit 8 Output terminal 10 Input terminal 11 Buffer memory 12 Decoding circuit 13 Decoding timing generation Circuit 14 Two-screen multiplexing and shaping memory 15 Format inverse conversion circuit 16 Output terminal

Continuation of the front page (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N 7 / 24,7 / 68 H04N 7 / 025,7 / 088 G06T 9/00

Claims (6)

(57) [Claims] 1. Two screens of a first screen and a second screen
In the moving picture coding apparatus for multiplexing and coding the two kinds of image signals of different pictures, the first screen and the second screen are alternately multiplexed every field time. receives the digital image signal, converted to double screen superimposed image data multiplexed alternately every frame time, and a dual-screen identification signal identifying this dual-screen multiplexed image data and multiplexed two screenful A format conversion circuit for outputting, and two-screen multiplexed image data and an encoding permission signal output from the format conversion circuit, and when the encoding permission signal is input, the two screens are input in accordance with the encoded image identification signal. the superimposed image data encoded according to the coding parameters, a coding circuit for outputting the code length information of the encoded image data and encoded image data, the code output from said coding circuit Kaga A buffer memory for temporarily storing data and outputting the data at a constant speed, and outputting data occupancy information; and a code length information output from the encoding circuit, and a generated information amount of a frame immediately after being encoded. And a coding parameter control circuit for controlling the coding parameters required for coding in the coding circuit based on the generated information amount output from the generated information amount calculation circuit. When the next frame by fullness of encoding just before the start output from the buffer memory to determine whether it encodes, based on the dual-screen identification signal outputted from the format conversion circuit, the reference numeral The first in the conversion circuit
The method for identifying a screen to be encoded, such that a frame of the screen and a frame of the second screen are alternately encoded.
An encoding apparatus for a two-screen multiplexed moving image, comprising: an encoding timing control unit that generates an encoded image identification signal and the encoding permission signal. 2. The encoding circuit according to claim 1 , wherein the first local decoded image data corresponding to the first screen is encoded.
A first frame memory for storing, and a second locally decoded image data corresponding to the second screen.
A second frame frame memory for storing the marks obtained by the encoding timing control means
Coding prediction value selecting means for selecting coding prediction values from the first and second frame memories in frame units according to a coding image identification signal; and Encoding means for encoding the two-screen multiplexed image data according to the selected prediction value and the encoding parameter output from the encoding parameter control circuit to output encoded data; wherein the screen with either the frame of the second screen has a multiplexing means for multiplexing said encoding parameters and identification signal indicating whether the encoded outputs the encoded image data 2. A circuit for encoding a two-screen multiplexed moving image according to claim 1, wherein 3. The coding parameter control circuit according to claim 1 , wherein the generated information amount calculated by the generated information amount calculation circuit is a first information value .
And the second screen are temporarily stored, and the coding parameters are determined separately for the first screen and the second screen based on the generated amount of generated information and the coding parameters of the previous coding. Encoding parameter control means; and each of encoding parameters determined by the encoding parameter control means depending on whether a frame to be encoded next is a first screen or a second screen. dual-screen multiplexed video coding apparatus according to claim 1, characterized by including an encoding parameter selecting means for selecting whether. 4. A two-screen system comprising a first screen and a second screen.
In a moving picture decoding apparatus that receives a digital signal obtained by multiplexing and encoding an image signal of two kinds of different pictures and decodes the digital signal into an image signal, the input encoded image data is written at a constant speed and temporarily stored. A buffer memory that outputs the encoded image data and the image synchronization signal; and a two-screen identification signal that identifies and decodes the multiplexed two-screen by inputting and decoding the encoded image data output from the buffer memory. And a decoding circuit that outputs decoded image data and image data output from the decoding circuit .
And the second screen are alternately multiplexed and shaped according to the decoding timing signal , and the first screen and the second screen are
A secondary screen multiplex shaping memory bets outputs the multiplexed dual-screen multiplexed <br/> image data alternately for each frame time, the dual-screen multiplex image output from the two-screen multiplex shaping memory enter the data, the dual-screen multiplexes image data, and format inverse conversion circuit for inversely converting the multiplexed image signals alternately every field time, the decoded image synchronizing signal outputted from the buffer memory Input the two-screen identification signal output from the circuit,
The frame of the first screen and the frame of the first screen are
And 2 of the screen frame to decode alternately decoding of dual-screen multiplexed video which is characterized by comprising a decoding timing control means for generating said <br/> decoded timing signal apparatus. 5. The decoding circuit according to claim 1, wherein the decoding circuit stores first decoded image data for the first screen.
And a second frame memory for storing the second decoded image data for the second screen.
2 and a first screen and a second screen from the encoded image data.
An identification signal indicating either frame and used for encoding
For separating encoded data and encoded data
When, in accordance with the identification signal, said first and said and decoding prediction value selecting means for selecting a frame decoding prediction value from the second frame memory, the prediction value selected by the decoded prediction value selection means and said encoding parameter and the secondary screen multiplexed video decoding apparatus according to claim 4, characterized in that and means for restoring <br/>-coding the encoded data in accordance with. Wherein said dual-screen multiplex shaping memory, in accordance with the decoded data <br/> timing signal obtained by the decoding timing control signal, separate the first screen and the second screen each of the first once written to first and second frame memories, comprising means for selecting as a first screen and read from the first and the second frame memory and the second screen is multiplexed alternately 5. The apparatus for decoding a two-screen multiplexed moving image according to claim 4, wherein: