JP3535549B2 - Image signal coding and multiplexing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal coding / multiplexing apparatus for coding and multiplexing image signals of a plurality of channels.

[0002]

2. Description of the Related Art In recent years, in the fields of storage media (software and data media using tapes, disks, etc.) and communications, international standardization of high-efficiency coding of moving image signals has been under study. FIG. 12 shows the configuration of a typical image signal encoding device used for high-efficiency encoding of a moving image signal according to the related art. In FIG. 12, the image signal applied to the input terminal 1 of the image signal encoding device is converted into encoded data by the encoding circuit 2, and the buffer memory 3
And is output to the code amount counter 6. The code data input to the buffer memory 3 is temporarily stored in the buffer memory 3, then read out from the buffer memory 3 at a constant fixed rate, output to the output terminal 4, and transmitted to the transmission system. On the other hand, the code amount counter 6 to which the code data is input from the encoding circuit 2 counts the code data and outputs the generated code amount of the code data in the current field obtained by the counting to the complexity calculation circuit 5. The complexity calculation circuit 5
The generated code amount in the current field input from the code amount counter 6 and the quantization step used in the encoding of the current field output from the encoding circuit 2 (a parameter for adjusting the generated code amount. Then, the complexity X of the image signal of the current field is calculated and output to the quantization step calculation circuit 7.

Further, the code amount counter 6 counts and stores the total code amount in the buffer memory 3 separately from the input code data and the generated code amount in the current field. The total code amount in the above is output to the quantization step calculation circuit 7. As a result, the quantization step calculation circuit 7 is supplied with the total code amount in the buffer memory 3 from the code amount counter 6, the complexity X calculated by the complexity calculation circuit 5, and the transmission rate designation terminal 8 separately. The target code amount to be generated in the next field and the quantization step value used therefor are calculated and output to the encoding circuit 2. That is, the quantization step calculation circuit 7 uses the encoding circuit 2 when the image is complicated and the code amount is likely to increase, or when a large amount of codes is accumulated in the buffer memory 3.
In order to reduce the amount of generated code and restore the normal state, the calculation is performed so as to output a large quantization step. Then, the encoding circuit 2 is reset with the obtained quantization step value, and the encoding of the next field is started. Hereinafter, the encoding is similarly repeated.

The application of this image signal coding apparatus to a broadcasting system is being advanced, but the broadcasting system has unique requirements. One is that in a broadcasting system, it is often necessary to transmit a plurality of image signals at the same time, such as when a large incident occurs. Therefore, in a broadcasting system such as an FPU (Field Pick Up) device having a limited number of channels, a given transmission system of, for example, 15 Mbps is divided into 5 Mbps, and the above image signal encoding device is divided into 3 by the same number of channels. An image signal encoding / multiplexing device has been proposed which prepares a table and time-division-multiplexes and transmits code data generated from each image signal encoding device.

By the way, in the image signal coding and multiplexing apparatus, if the image signal of a complicated pattern is coded in the same quantization step as that of the image signal of a non-complex pattern, the code amount of the image signal of the uncomplicated pattern is increased. Since the encoding is performed in the quantization step, the generated code amount of the image signal having a complicated pattern increases. Therefore, when the transmission rate for transmitting the code data is fixed, it is necessary to increase the quantization step in a complicated pattern, reduce the image quality, and encode and transmit so that the generated code amount does not exceed the transmission rate. On the contrary, since the amount of generated code is insufficient with a simple picture, the quantization step is lowered more than necessary, the image quality is increased, and the code is transmitted. As described above, in the conventional image signal coding and multiplexing apparatus, since the transmission rate of each channel is fixed at a constant value, the image quality of the channel for sending a complicated pattern is poor and the image quality of the channel for a simple pattern is good. As a result, the image quality varies among the channels.

As a method for solving this problem, the following method can be considered. That is, when the number of channels is 3, the target code amount of each channel (individual target code amount) T
ch is the complexity of the image of each channel Xa, Xb, Xc
According to the following equation: Tch = (Xch / (Xa + Xb + Xc)) × Rt (1) where Xch: complexity of a certain channel ch: Rt representing channel number a, b, c: transmission system Allocate according to a fixed rate value. The transmission rate (individual rate) Rch of each channel is set to the individual target code amount Tch.
The individual rate Rch = Tch capable of transmitting the same code amount as is assigned.

FIG. 13 shows an image signal coding / multiplexing apparatus. A plurality of image signal coding apparatuses shown in FIG. 12 are provided with a target code amount allocation circuit 9 and a code data multiplexing circuit 10 for multiplexing. Is added. In FIG.
The target code amount allocation circuit 9 is a circuit for obtaining the individual rate Rch according to the equation (1). The output of the individual rate Rch obtained by this circuit is input to the transmission rate designation terminal 8 of each channel shown in FIG. 12, and the generated code amount is adjusted according to the complexity of the image of each channel. Further, the target code amount allocation circuit 9 simultaneously controls the buffer memories 3 of the respective channels, and reads the code data corresponding to the size of the individual rate Rch from the respective buffer memories 3. The code data read from each buffer memory 3 is output to the code data multiplexing circuit 10, the code (header) necessary for transmission is added in the code data multiplexing circuit 10, multiplexed and output, and transmitted. Transmitted to the system.

FIG. 14 schematically shows a change in the code amount in the buffer memory on the transmitting side and the receiving side when two-channel image signals are multiplexed and transmitted using the image signal coding and multiplexing apparatus shown in FIG. It is shown. In the above schematic diagram, an encoder (encoding circuit) and a buffer memory for two fields are provided on the transmission side, and a decoder and two fields for two fields are provided on the reception side (a general decodable device is not shown). This is the case assuming that there is a buffer memory. In FIG. 14, a double-line frame 11 on the transmitting side shows a code portion generated from an encoder (encoding circuit) in the current 1-field period, and a double-line frame 12 on the receiving side shows in the current 1-field period. The image code portion which is decoded by the decoder and output is output by the transmission system 13 which is an intermediate area.
The box inside indicates the code part to be transmitted in the current one field period. Further, for simplification, the code amount is shown in units of one block indicated by a square. Further, the transmission rate value after the individual rate change is shown in the parentheses in block units.

FIG. 14 (a) shows a stable state in which the a channel and the b channel are transmitting at the same transmission rate. That is, the fourth field is encoded during the current 1-field period on the transmitting side, the second field is transmitted during the current 1-field period of the transmission system, and the 0th field is decoded during the current 1-field period on the receiving side. It starts and ends each operation at the end of this one-field period. In FIG. 14B, the generated code amount of the fifth field is 1.5 in the channel a on the transmission side due to a scene change or the like.
The figure shows a case in which the generated code amount of the fifth field is doubled and the generated code amount of the fifth field is reduced to 1/2 in the b channel. If this state continues thereafter, the transmission rate of each channel of the next field is reset to the new individual rate obtained from the image complexity Xa of the a-channel fifth field.

That is, as shown in FIG. 14 (c),
The transmission rate of the channel a on the transmitting side is increased to 3 blocks in the sixth field like the fifth field, and code data for 1.5 fields is transmitted in one field period. Further, the transmission rate of the b channel is reduced to one block, and code data for 0.5 field is transmitted in one field period. In this way, the transmission rate of each channel is changed according to the complexity of the input image, and it is possible to realize the multiplex transmission in which the fixed rate Rt of the transmission system is effectively used and the variation in image quality is small.

By the way, in the third field portion on the transmission side in FIG. 14A, when the code amount of the second field is smaller than the target code amount, in order to prevent the transmission code amount from becoming insufficient and causing a malfunction, It corresponds to a margin field stored in the transmission side buffer memory. Also, the first on the receiving side
On the contrary, the field portion is stored in the buffer memory on the receiving side in order to prevent a malfunction in which the image cannot be output in the next field time when the transmission amount cannot be completed in one field period due to the excessive code amount of the second field. It corresponds to the surplus field. As described above, the margin field is always necessary to prevent malfunction of the image signal encoding device.

However, in the case of the image signal encoding / multiplexing apparatus shown in FIG. 13, after passing through the stable state shown in FIG. 14 (d) after changing the transmission rate allocation, as shown in FIGS. 14 (e) and 14 (f). As described above, the margin field is completely eliminated on the b channel side of the receiving side. Therefore, if the code amount of the fifth field of the b channel, for example, slightly increases from the target code amount, the code data cannot be sent in one field period at the stage of FIG. 14D, and the one field period of FIG. There is a lack of coded data to be input to the receiving side decoder. Therefore, it is necessary to increase the margin field on the receiving side by one field.

[0013]

In the above description, the case where the code amount ratio between channels is 1: 3 has been described.
In the conventional image signal coding and multiplexing apparatus, if the ratio of the code amount is further increased, it is necessary to further increase the margin field for several fields, and it is necessary to further increase the margin field on the receiving side. However, increasing the margin field not only requires a large-scale circuit to increase the storage capacity of the buffer memory, but also
There arises a problem such as a transmission delay of several field periods due to code data remaining in the buffer memory. In order to solve the above problems, in the present invention, individual rate allocation is performed using not the target code amount of each channel or the image complexity but the code amount actually generated in a predetermined past period, for example, one field period. It is an object of the present invention to provide an image signal coding / multiplexing device for performing.

The present invention, in order to achieve the above object, a plurality of image signal encoding circuit for encoding an image signal of a plurality of channels for each channel, the code data generated by the respective image signal encoding circuit each a plurality of buffer memories for temporarily storing for each channel, in the image signal encoding multiplexing apparatus having a code data multiplexing circuit for multiplexing the encoded data read from said each buffer memory at a predetermined rate, each image signal encoding The number of generated codes in a predetermined period in the digitizing circuit and the time of the predetermined period are counted in the vertical synchronization signal.
A plurality of generated code amount storage circuit having a memory for storing the time number, expressed by the number, from the stored time numbers to the respective generated code amount storage circuit, the channel of the oldest time number 1
If that is the case , select that channel and select the oldest time
If there is more than one channel with an issue, the oldest
Buffer within two or more channels with time numbers
A channel selection circuit total code amount of the memory to select the largest channel selection signal from the channel selection circuit
Corresponding channel selected by the relevant selection signal
Code amount g0 for a predetermined period of time and a predetermined constant code amount
Code amount to be read, calculated by comparison with gMAX
The code amount gt and the code data read control signal and is equivalent
Comprising a transfer code amount calculation circuit for output of the channel to the buffer memory, an image signal encoding multiplexing apparatus adapted to control the buffer memory for each channel by the said code quantity gt and the code data read control signal.

In order to achieve the above object, other
In addition, the image signals of multiple channels are encoded for each channel.
Image signal encoding circuits for encoding, and each image signal code
The coded data generated by the digitizing circuit is temporarily stored for each channel.
A plurality of buffer memories to be stored in the
Code data to be read at a predetermined rate from the memory
Image signal coding and multiplexing apparatus having code data multiplexing circuit
, The last code stored in each buffer memory
No. of data storage address and generated code data for a predetermined period
And the time number expressed by the number of vertical sync signals
A plurality of generated code amount storage circuits having a memory for storing,
From the time number stored in each generated code amount storage circuit, the oldest
If there is only one channel with a different time number, that channel
And select two channels with the oldest time number.
If there are more than two, the two or more with the oldest time number
The total code amount in the buffer memory of the channel is the largest
Channel selection circuit that selects the desired channel and the channel
The selection signal is received from the channel selection circuit and
Sign of the buffer memory of the corresponding channel selected from
Read address br which is the starting point of data storage and the last code
Memory address b0 storing the number data and a predetermined number
Code data to be read calculated from the constant code amount gMAX
The memory address bt storing the last code data of
Transfer code amount calculation circuit that outputs to the channel buffer memory
And the read address br and the storage address bt
To control the buffer memory of each channel by
The image signal encoding and multiplexing device according to the present invention.

[0016]

Further, each transfer code amount calculation circuit receives a selection signal from the channel selection circuit, and the code amount g0 from each generated code amount storage circuit and a predetermined constant code amount gMA.
The image signal encoding / multiplexing device has a circuit for calculating the code amount gt to be read from X and gMIN as follows: when g0 <gMAX is satisfied: gt = g0 g0? GMAX is satisfied: gt = gMAX-gMIN

Further, each transfer code amount calculation circuit receives a selection signal from the channel selection circuit, and a read address br which is a starting point of storing code data in the buffer memory of the selected channel with predetermined constant code amounts gMAX and gMIN.
And the storage address b0 storing the oldest last code data and the storage capacity B of the buffer memory, the code to be read
The memory address bt that stores the last coded data of the data is: b0 '= b0 if br <b0, b0' = b0 + B if br> b0, and bt if b0 '<b'MAX (= br + gMAX) '
= B0 'b0'>b'MAX, bt '= b'MAX -gMIN, and bt'<B, bt = bt 'bt'> B, bt = bt'-B. The image signal coding and multiplexing apparatus is a circuit that calculates a storage address bt in which code data is stored.

Further, the code data P signal obtained by encoding the difference signal obtained by correcting the movement of the images of two consecutive screens and the code data I signal obtained by encoding the image signals of all the images are repeated at a predetermined field period Fg. The image signal encoding / multiplexing apparatus is provided with an IP synchronization control circuit which enables output and controls so that the output timings of the coded data I signals of the respective channels are mutually shifted.

[0020]

The function of the present invention is as follows. In the encoding of the image signal, the generated code amount storage circuit stores at least one of the generated code amount of the predetermined period or the last code data storage address stored in the buffer memory and the time number indicating the relative time of the predetermined period, The channel selection circuit selects the channel having the oldest time number of each generated code amount storage circuit or the channel having the largest total code amount in the buffer memory of two or more channels having the oldest time numbers, and the transfer code amount is selected. The calculation circuit outputs the code amount gt calculated by the selection signal and the code data read control signal to generate the code amount gt or the memory address and the code data read control signal to control the buffer memory of each channel.

Further, in the memory of the generated code amount storage circuit, the generated code amount in a predetermined period in the image signal encoding circuit, a time number representing the relative time of the predetermined period, and the last code data storage address stored in the buffer memory. Is the memory for temporarily storing the oldest code amount g0, the time number t0, and the last code data storage address b0 stored in the memory. Further, the transfer code amount calculation circuit receiving the selection signal from the channel selection circuit calculates the code amount gt from the code amount g0 from the generated code amount storage circuit and the predetermined constant code amount gMAX or from the temporary storage memory. The memory address b0 and the code read control signal are output to the buffer memory of the channel.

Further, the transfer code amount calculation circuit receiving the selection signal from the channel selection circuit, the code amount g0 from the generated code amount storage circuit and the predetermined constant code amounts gMAX, g.
When computing and selecting MIN, when g0 <gMAX is satisfied gt = g0 When g0 ≧ gMAX is satisfied gt = gMAX-gMIN, the code amount gt is calculated.

Further, the transfer code amount calculation circuit receiving the selection signal from the channel selection circuit, the code amount g0 from the generated code amount storage circuit and the predetermined constant code amounts gMAX and g.
When MIN and the read address br, which is the starting point for storing the code data in the buffer memory of the selected channel, the storage address b0 storing the oldest last code data and the storage capacity B of the buffer memory are selected, br <b0 When b0 '= b0 br> b0, b0' = b0 + B, and b0 '<b'MAX (= br + gMAX) bt'
= B0 'When b0'>b'MAX, bt '
= B'MAX-gMIN, and when bt '<B, bt = bt' bt '> B, bt = bt'-B is used to calculate the memory address bt at which the last coded data is stored. Is.

Further, the IP sync control circuit repeats the code data P signal of the difference signal in which the movement of the images of two consecutive screens is corrected and the code data I signal of the image signals of all the images at a predetermined field cycle Fg. The output timing and the output timing of the code data I signal of each channel are controlled so as to be shifted from each other.

[0025]

【Example】

[Embodiment 1] FIG. 1 shows a first embodiment of the present invention. FIG. 1 shows a configuration of an image signal coding / multiplexing apparatus according to the present invention. In the image signal coding / multiplexing apparatus according to the prior art shown in FIG. The quantity calculation circuit 16 is provided, and the same components as those in FIG. 13 are designated by the same reference numerals. Also,
The read control of the code data output from the buffer memory 3 of each channel to the code data multiplexing circuit is performed by the control signal from the channel selection circuit 15 instead of the target code amount allocation circuit 9 in the prior art. different.

FIG. 2 shows a configuration example of the newly-generated code amount storage circuit 14. In FIG. 2, the memory 17 is a FIFO type memory configured to write three types of data as one set and to read in the order of writing. This memory 17 generates the generated code amount of the current field input from the code amount counter 6, the time number of the vertical synchronization signal input to the generated code amount storage circuit 14 by the counter 19, and the generated time number in the current field. The storage address in the buffer memory 3 storing the last code data of the code data is sequentially stored. In addition, the counter 18 has a memory 17
It is a counter that counts the number of data sets stored in the memory 17 by adding 1 when data is written to and subtracting 1 when read. Then, the temporary storage memory 20 reads out the oldest set of data (time number: t0, code amount: read from the FIFO type memory 17).
g0, end address: b0) is a memory for temporarily storing.

The operation of the image signal coding and multiplexing apparatus according to the present invention will be further described below with reference to FIGS. Note that, in FIG. 1, the encoding of a plurality of applied image signals and the allocation of the target code amount are performed in the same manner as in the device of FIG. In each newly-generated code amount storage circuit 14 of each channel, a set of data (t) for the oldest field stored in the temporary storage memory 20 is stored.
0, g0, b0) is output to the channel selection circuit 15. The channel selection circuit 15 compares the time number (t0) in each set of data obtained from the temporary storage memory 20 of the generated code amount storage circuit 14 of each channel, and selects the channel number having the oldest time number. To do. In this case, if there are multiple channels with the same time number,
Further, the total accumulated code amount of the buffer memory 3 is read from the corresponding code amount counter 6 of each channel and compared, and the channel number having the largest accumulated code amount is selected. Then, the selection signal is output to the transfer code amount calculation circuit 16 of the channel of the selected channel number. (FIG. 3 schematically shows an example of a flowchart of the processing steps of the channel selection circuit 15 described above.) The channel selection circuit 15 may be configured by using, for example, a microcomputer, or other various configurations. It is possible.

The transfer code amount calculation circuit 16 of the corresponding channel which receives the channel selection signal from the channel selection circuit 15 causes the code amount of the field stored in the temporary storage memory 20 of the generated code amount storage circuit 14 ( g
0) is compared with a predetermined constant code amount gMAX, and the smaller code amount is gt = MIN (g0 or gMA
Select as X). Then, the transfer code amount calculation circuit 16
Outputs the selected code amount gt and the code data read control signal to the buffer memory 3 of the channel. (FIG. 4 schematically shows an example of a flowchart of a process of selecting the code amount performed by the transfer code amount calculating circuit 16 described above.) The code read from the buffer memory 3 by the code amount gt and the code data read control signal. The code data of the amount gt is sequentially output after the code (header) necessary for transmission is added by the code data multiplexing circuit 10.

The transfer code amount calculation circuit 16 outputs the selected code amount gt to the buffer memory 3 and at the same time to the generated code amount storage circuit 14. The generated code amount storage circuit 14 subtracts the code amount gt from the code amount (g0) stored in the temporary storage memory 20 (g0-g).
t), and when (g0-gt)> 0, this value (g0
-Gt) is stored again in the temporary storage memory 20 instead of the code amount (g0) stored so far. On the other hand, when (g0-gt) = 0, the oldest field data is newly stored in the memory 17 and temporarily stored in the memory 20.
It is read inside and again the temporary storage memory 20 of each channel
The data in the above is output to the channel selection circuit 15, and the same operation as described above is repeated.

FIG. 5 shows how the code amounts in the buffer memories on the transmitting side and the receiving side are changed by the series of operations described above.
However, one square block represents the code amount gMAX. In the image signal code multiplexer according to the present embodiment,
Always transmit the code data of the oldest field number. Therefore, as shown in FIG. 5B, the effective transmission rate distribution is not directly affected by the increase or decrease of the code amount generated in the current field image signal coding. That is, as shown in FIG. 5C, the transmission rate of the a channel in one field period is shown in FIG.
Unlike the conventional example of (c), the code data of the fourth field of both channels a and b is transmitted first without raising immediately. As a result, the code before the scene change stored in the transmission side buffer memory is wiped out. Therefore, even in FIG. 5 (f) in which a sufficient time has elapsed and the steady state is reached, the imbalance in the number of margin fields does not occur as in FIG. 14 (f). Therefore, it is not necessary to increase the number of spare fields as in the conventional technique, and the transmission delay due to the storage capacity of the buffer memory and the spare field can be minimized.

As described above, in the image signal coding and multiplexing apparatus according to the present invention, distortion is not concentrated on only one channel, and the number of spare fields can be suppressed to the minimum number. Therefore, it is possible to obtain a good image signal coding and multiplexing apparatus in which the circuit scale of the buffer memory is small and there is no useless transmission delay. Further, in the image signal coding and multiplexing apparatus according to the present invention, the transmission rate is automatically assigned according to the actually generated code amount. Therefore, even if the code amount actually generated deviates from the target code amount, the transmission rate allocation is automatically changed and the error amount is distributed to multiple channels, so the storage capacity of the buffer memory can be further reduced. become.

[Embodiment 2] FIG. 6 shows a second embodiment of the present invention. FIG. 6 is a schematic diagram of a calculation flowchart in which the transfer code amount calculating circuit 16 of the image signal coding and multiplexing apparatus according to the present invention is used as another means. The other circuits of the image signal coding and multiplexing apparatus and their operations are the same as those in the first embodiment. The transfer code amount calculation circuit 16 in the present embodiment calculates the transfer code amount as follows. That is, the transfer code amount calculation circuit 16 receives the code amount (g0) of the field stored in the temporary storage memory 20 of the input generated code amount storage circuit 14 (see FIG. 2) and a predetermined constant code amount. Compare with gMAX, and when g0 <gMAX, gt = g0,
When g0 ≧ gMAX, a value obtained by subtracting a predetermined constant code amount gMIN from gMAX gt = gMAX-gMI
Output N to the buffer memory 3. Then, the code data of the code amount gt read out from the buffer memory 3 is sequentially output after a code (header) required for transmission is added by the code data multiplexing circuit 10.

In the flow chart of the transfer code amount calculating circuit in the first embodiment shown in FIG. 4, gt = gMAX when g0 ≧ gMAX. Therefore, in an extreme case, the remaining code amount of the field becomes 1 bit, and when the code data is transmitted next time, a transmission code (header) of several tens of bits is added for this 1 bit to transmit. Occurs. On the other hand, if gt = gMAX-gMIN is set as in the transfer code amount calculating circuit of the present embodiment shown in FIG. 6, the minimum code amount of gMIN can be secured when the code data is transmitted next time. As described above, when the transfer code amount calculating circuit 16 according to the present embodiment is used, it is unreasonable that a transmission code (header) of several tens of bits must be added to transmit an image code of several bits. It is possible to realize a good transmission rate allocation that does not occur.

[Embodiment 3] FIG. 7 shows a third embodiment of the present invention. FIG. 7 is a schematic diagram of a calculation flowchart in which the transfer code amount calculation circuit 16 of the image signal coding and multiplexing apparatus according to the present invention is used as another means. In the case of the present embodiment, it is assumed that the buffer memory 3 has a structure of cyclically storing. That is, as schematically shown in FIG. 8, the storage is sequentially started from the address 0 and the last address B-1 (the storage capacity is B
When it has reached (0), it has a structure to return to address 0 again and continue to store the data sequentially. Address br in FIG.
Is the starting point of the data stored in the buffer memory 3 and is the address representing the starting point of the next data reading. The address bw is an address representing the starting point of new data input. The other circuits of the image signal coding and multiplexing apparatus and their operations are the same as those in the first embodiment.

In the transfer code amount calculation circuit 16 of this embodiment,
The point that the code amount for reading the code data from the buffer memory 3 is selected by designating the storage address (end address) in the buffer memory 3 storing the last code data of the code data to be read is Different from the first and second embodiments. That is, the transfer code amount calculation circuit 16 uses the temporary code memory 20 of the generated code amount storage circuit 14.
From the end address of the code generated in the field (b
0) and the read address br which is the starting point of data accumulation from the buffer memory 3. When the following expression br <b0, b0 '= b0 (2) When br> b0, b0' = b0 + B The virtual address b0 ′ (see FIG. 8) above is obtained.

Then, this virtual number of addresses is compared with a numerical value b'MAX = br + gMAX separately obtained from the read address br, and when the following expression b0 '<b'MAX (= br + gMAX), bt' = b0 '. ... (3) When b0 '>b'MAX,bt' =
The address bt 'on the virtual memory of the storage address bt of the buffer memory 3 in which the last code of the series of codes to be transmitted is accumulated is obtained by b'MAX-gMIN. From this value bt ', when the following equation bt'<B, bt = bt '(4) When bt'> B, the actual address bt of the buffer memory is calculated by bt = bt'-B. The value is output to the buffer memory 3. In the buffer memory 3, the code data from the read start address br to the address bt is read, the code data multiplexing circuit 10 adds a code (header) required for transmission, and then sequentially outputs.
As described above, also in this embodiment, the other circuits and their operations are performed in the same manner as in the first embodiment, so that the same effect as in the first or second embodiment can be obtained.

[Embodiment 4] FIG. 9 shows a fourth embodiment of the present invention. FIG. 9 shows the configuration of an image signal coding and multiplexing apparatus according to the present invention. The image signal coding and multiplexing apparatus of the first embodiment shown in FIG. 1 is further provided with an IP synchronization control circuit 21. In general, two consecutive fields or two frames of images in a moving image are very similar images, and the difference signal (hereinafter referred to as P signal) obtained by correcting and subtracting the movement of the subject in the two images is almost zero. Become. Therefore, when this difference signal is used for encoding, the code amount can be significantly reduced. However, if only the difference signal is continuously transmitted, the image after that cannot be reproduced once the disturbance enters the transmission system. Therefore, in a normal image signal encoding device using a difference signal, a signal obtained by encoding the image signal of the entire image (hereinafter referred to as I signal) is transmitted at a constant field period Fg, and even if disturbance occurs. The image can be played back continuously.

The code data thus constructed is shown in FIG.
FIG. 10 schematically shows how the code amount in the buffer memory on the transmitting side and the receiving side changes when transmitting through the conventional image signal encoding and multiplexing apparatus shown in FIG. Third in FIG.
The field and the eighth field are I signals, and the other fields are P signals. In such a case, since the code amounts of the a and b2 channels increase at the same time, there arises a dangerous state in which there is no margin field or a margin code which is a part of the margin field on the receiving side (FIG. 10 (d)). Therefore, normally, the code amount of the P signal is adjusted to be slightly smaller than the transmission rate, and the signal is gradually returned. But,
In spite of the fact that the margin field temporarily disappears,
Furthermore, a margin for one field is required. In addition, it takes a long period of the constant field period Fg to return to the normal state.

In view of this, in this embodiment, an IP synchronization control circuit 21 is newly added to the configuration of the image signal encoding / multiplexing device shown in FIG. 1 so as to shift the timing of transmitting the I signal for each channel. FIG. 11 schematically shows how the code amounts in the buffer memories on the transmitting side and the receiving side change in this way. As shown in FIG. 11 (d),
Also in this embodiment, the margin field on the receiving side is reduced. However, the sign of the margin field does not completely disappear like the receiving side in FIG. Therefore, the code amount of the margin field to be increased can be small, and the increase of the circuit scale of the buffer memory and the transmission delay can be suppressed to a small level. In addition, it is possible to return to the normal state in a period of about 1/2 or less of that in the case of FIG.
(F) The margin field on the receiving side is shown in FIG.
(E) There is a margin field on the receiving side), and the risk of malfunction can be greatly reduced.

As a method of controlling the timing of transmitting the I signal in the IP synchronization control circuit 21, for example, the value of the constant field period Fg of one channel is temporarily (Fg
It may be set to a value larger than one field, such as +1), and gradually or all at once shifted to the target timing position.
At this time, the value of the constant field period Fg may be set to a small value, but the code amount is temporarily increased in the same manner. As described above, in the image signal coding and multiplexing apparatus according to the present embodiment, in addition to the same effects as the first embodiment, the shortage of the margin field on the receiving side due to the increase in the code amount due to the I signal is suppressed to a small level, and the buffer memory circuit It is possible to obtain a good image signal coding and multiplexing apparatus that is small in scale and has no useless transmission delay.

As the time number used in each of the above embodiments, a sufficiently large number F (field) may be prepared and used cyclically. That is, the field number is counted from 0, and the time number is added so as to return to 0 when the set F is exceeded. When the predetermined number is F0 and the two time numbers are f1 and f2, when | f1-f2 | ≦ F0, when the time number with the smallest number among f1 and f2 is | f1-f2 |> F0 , F1 and f2, the time number with the largest number ... (5) may be used to determine the age of the time number.
The number F can be arbitrarily set as long as it is (2F0 + 1) or more.
However, in the method according to the present invention, the difference between the field time numbers to be compared with each other is in principle not more than ± 1. Therefore, F0 can be set to an arbitrary number of 1 or more, and F can be set to count a number of 3 or more.

In the generated code amount storage circuit shown in FIG. 2, the field code amount (g0) and the last storage address (b0) of the field code are stored in the memory 17. However, only the last storage address (b0) is stored, and the field code amount (g0) may be obtained from the difference between the storage addresses of two consecutive fields. Also,
When selecting using only the code amount (g0) as in the second embodiment, it is obvious that only the code amount (g0) may be stored. Further, although the memory 17 stores the last storage address (b0) of the field code, it is obvious that the start address of the code may be stored.

Further, in the generated code amount storage circuit shown in FIG. 2, since the memory of the FIFO system in which the stored contents are erased once read is used as the memory 17, a temporary storage memory for temporarily storing the read data. 20 was also used. However, when a memory (for example, a RAM) of a type that does not lose the stored contents even if it is read and is used as the memory 17 is used, the temporary storage memory 20 is not used, and g0 and other data are directly stored in the memory 17. Obviously, it may be read. Further, in the transfer code amount calculation circuit 16 of each of the above-described embodiments, g0 and gMAX are compared and the code amount gt for transmitting the smaller value is selected, but gt = g0 (gMAX is a sufficiently large value). It is clear that it may be set as).

When reading a set of data of a new field stored in the memory 17 shown in FIG. 2,
When the number of the counter 18 is 0, that is, when the coding of the next field is not completed, and the value of the code amount counter 6 does not exceed a certain amount such as gMIN, gMAX,
A time number indicating that there is no code to be transmitted (for example, F +
By storing 1) in the temporary storage memory 20 or the like,
It is desirable to exclude it from the selection target in the channel selection circuit 15. As a result, it is possible to prevent an erroneous operation that starts reading the code data from the buffer memory 3 even though there is no code data to be transmitted.

In each of the above-mentioned embodiments, the case has been described in which the code amounts generated in the past predetermined period are put together in a general field unit, but the predetermined period is not limited to the frame unit, for example. Obviously, it may be set to an arbitrary predetermined period such as an integer fraction of the field, and this is within the scope of the present invention. In addition, as described above, when the predetermined period is, for example, an integer fraction of the field, it can be set to an arbitrary time different from the synchronization signal such as the vertical synchronization signal of each channel, so that it is not synchronized. It becomes possible to multiplex and transmit image signals of a plurality of channels. Further, the code amount in each of the above-mentioned embodiments does not necessarily have to be in bit units. For example, it is obvious that a byte, a word, or a value expressed in units of an arbitrary number of bits may be used. However, in this case, a shortage may occur in the last code unit of the field. Therefore, it goes without saying that it is necessary to fill the deficiency with a dummy code or fill this with a part of the code of the next field to form a complete code unit.

Further, in FIG. 1, the generated code amount storage circuit 14 and the transfer code amount calculation circuit 16 are provided for each channel.
However, it is obvious that at least one of these circuits may be combined into one and centralized control may be performed. Further, in each of the above-mentioned embodiments, the maximum code amount gMAX to be transmitted collectively is defined, but it is obvious that the transmission may be performed in a unit of one field without providing such a limitation.

[0047]

As described above, in the image signal coding and multiplexing apparatus according to the present invention, since the coded data of the oldest field is always transmitted in sequence, distortion is not concentrated on only one channel. Therefore, the number of spare fields can be suppressed to a minimum number, and a good image signal coding and multiplexing apparatus with a small circuit scale of the buffer memory and without unnecessary transmission delay can be obtained. Further, since the transmission rate is automatically assigned according to the actually generated code amount, even if the actually generated code amount deviates from the target code amount, the transmission rate allocation is automatically changed and the error is reduced. Since it is distributed over a plurality of channels, it becomes possible to further reduce the storage capacity of the buffer memory.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an image signal coding and multiplexing apparatus according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a generated code amount storage circuit according to the present invention.

FIG. 3 is a calculation flowchart of a channel selection circuit according to the present invention.

FIG. 4 is a calculation flowchart of a transfer code amount calculation circuit according to the present invention.

FIG. 5 is an explanatory diagram of changes in the storage code amount according to the first embodiment of the present invention.

FIG. 6 is a calculation flowchart of the transfer code amount calculation circuit according to the second embodiment of the present invention.

FIG. 7 is a calculation flowchart of the transfer code amount calculation circuit according to the third embodiment of the present invention.

FIG. 8 is a schematic diagram of a buffer memory structure for cyclically storing.

FIG. 9 is a configuration diagram of an image signal coding and multiplexing apparatus according to a fourth embodiment of the present invention.

FIG. 10 is an explanatory diagram of changes in the storage code amount in the conventional image signal encoding and multiplexing apparatus.

FIG. 11 is an explanatory diagram showing changes in the storage code amount in the image signal coding and multiplexing apparatus according to the fourth embodiment of the present invention.

FIG. 12 is a configuration diagram of a conventional image signal encoding device.

FIG. 13 is a block diagram of a conventional image signal coding and multiplexing apparatus.

FIG. 14 is an explanatory diagram of changes in the storage code amount in the conventional image signal encoding and multiplexing apparatus.

[Explanation of symbols]

2 ... Encoding circuit, 3 ... Buffer memory, 5 ... Complexity calculation circuit, 6 ... Code amount counter, 7 ... Quantization step calculation circuit, 9 ... Target code amount allocation circuit, 10 ... Code data multiplexing circuit, 14 ... Generated code amount storage circuit, 15 ... Channel selection circuit, 16 ... Transfer code amount calculation circuit, 17 ... Memory, 1
8 ... Counter, 19 ... Counter, 20 ... Temporary storage memory, 21 ... IP synchronization control circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiyuki Akiyama 32 Miyuki-cho, Kodaira-shi, Tokyo Hitachi Electronics Co., Ltd.Koganei factory (72) Inventor Yuichi Ohnami 32 Miyuki-cho, Kodaira-shi, Tokyo Hitachi Electronic Co., Ltd. Koganei Factory (56) Reference JP-A-52-38811 (JP, A) JP-A-58-145284 (JP, A) JP-A-3-163979 (JP, A) JP-A-4-160888 (JP, A) JP 5-64175 (JP, A) JP 5-111014 (JP, A) JP 5-227516 (JP, A) JP 6-62393 (JP, A) JP 6 -86261 (JP, A) JP-A-6-268985 (JP, A) JP-A-6-326986 (JP, A) JP-A-7-111649 (JP, A) US Patent 5159447 (US, A) T.S. KOGA, et al. , Statistical Performance Analysis of an Interframe Encoder for Broadcast Television Revision Signals, IEE Transactions on Communications, Ill. COM-29, No. 12, p. 1868-1876 (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N ^7/ 24-7/68 H04N ^7/ 00-7/088

Claims (5)

(57) [Claims] 1. A plurality of image signal encoding circuit for encoding an image signal of a plurality of channels for each channel, a plurality of temporarily storing code data generated by the respective image signal encoding circuit for each channel and a buffer memory, an image signal encoding multiplexing apparatus having a code data multiplexing circuit for multiplexing the encoded data read from said each buffer memory at a predetermined rate, the generated code quantity of a predetermined period in each of the picture signal encoding circuit And vertical synchronization of the predetermined period of time
A plurality of generated code amount storage circuit having a memory for storing the time number, expressed by the number of counting signals, from the stored time numbers to the respective generated code amount storage circuit, when the channel of the oldest time number is one Selects that channel ,
If there is more than one channel with the oldest time number
Of the two or more channels with the oldest time number
The channel with the largest total code amount in the buffer memory
A channel selection circuit for selecting a channel, a selection signal from the channel selection circuit, and a selection signal selected by the selection signal .
The code amount g0 of the corresponding channel for a predetermined period is determined in advance.
Reading calculated by comparison with the fixed code amount gMAX
A code amount gt and the code data read control signal is a code quantity to give to and a transfer code amount calculation circuit to be output to the buffer memory of the channel, the code quantity gt and marks <br/> No. data read control signal An image signal coding and multiplexing apparatus characterized in that a buffer memory of each channel is controlled by and. 2. A plurality of image signal encoding circuits for encoding image signals of a plurality of channels for each channel, and a plurality of temporarily storing code data generated by the image signal encoding circuits for each channel. In the image signal encoding / multiplexing device having the buffer memory and the code data multiplexing circuit for multiplexing the code data read from each buffer memory at a predetermined rate, the last code data storage address stored in each buffer memory. And a plurality of generated code amount storage circuits having a memory for storing the time of a predetermined period of the generated code data represented by the number of vertical synchronization signals counted, and the time stored in each generated code amount storage circuit. From the numbers, if there is one channel with the oldest time number, select that channel, and there are two or more channels with the oldest time number. In the case of two or more channels having the oldest time number, a channel selection circuit that selects the channel with the largest total code amount in the buffer memory, and a selection signal from the channel selection circuit, The read address br which is the start point of the code data storage of the buffer memory of the corresponding channel selected by
And a storage address b0 storing the last code data and a predetermined fixed code amount gMAX, the storage address bt storing the last code data of the code data to be read.
And a transfer code amount calculating circuit for outputting to the buffer memory of the channel, and controlling the buffer memory of each channel by the read address br and the storage address bt. 3. A code amount g0 from each of the generated code amount storage circuits according to claim 1, wherein each of the transfer code amount calculation circuits receives a selection signal from the channel selection circuit.
And a predetermined constant code amount gMAX, gMIN, the code amount gt to be read is calculated as gt <gMAX gt = g0 g0? GMAX is satisfied gt = gMAX-gMIN Image signal encoding and multiplexing device. 4. A ones according to claim 2, wherein each transfer bitrate calculating circuit receives a selection signal from the channel selection circuit, a predetermined constant code amount gmax, the code buffer memory of the selected channel and gMIN From the read address br, which is the starting point of data storage, the storage address b0 that stores the oldest last code data, and the storage capacity B of the buffer memory, the storage address bt that stores the last code data of the code data to be read, When br <b0, b0 '= b0 When br> b0, b0' = b0 + B, and when b0 '<b'MAX (= br + gMAX), bt'
= B0 'b0'>b'MAX, bt '= b'MAX -gMIN, and bt'<B, bt = bt 'bt'> B, bt = bt'-B. An image signal coding / multiplexing device, which is a circuit for calculating a storage address bt in which code data is stored. 5. The code data P according to claim 1 or 2, wherein the difference signal is generated by correcting the movement of images on two consecutive screens, and the code data obtained by encoding the image signals of all the images. I signal and I signal are repeatedly output at a predetermined field period Fg, and an IP synchronization control circuit is provided for controlling the timings of outputting the code data I signals of the respective channels to be shifted from each other. apparatus.