JPH05300486A - Variable length encoding and decoding circuit - Google Patents

Abstract

PURPOSE:To reduce the memory circuit required for a parallel processing by performing a parallel processing by a picture element unit in the variable length encoding and decoding circuit in the encoding of a TV signal. CONSTITUTION:Inputted picture data is distributed to variable length encoders 4 to 7 by a picture element unit in a separation circuit 3 and a variable length encoding processing is performed for the data by a parallel processing. After encoded data is written in memory circuits 8 to 11, each encoded data is multiplexed by a word unit in a multiplex circuit 12. At the time, the number of word of each encoded data to be outputted from the variable length encoders 4 to 7 is also multiplexed with the encoded data so as to normally separate the data at the time of decoding even if the data are multiplexed by a word unit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable length coding circuit and a variable length decoding circuit used in a high efficiency coding apparatus for television signals.

[0002]

2. Description of the Related Art In a variable-length coding circuit used in a high-efficiency coding apparatus for television signals, parallel processing is performed when the data speed of input data is high and the processing speed of variable-length coding is too late. There is. In that case, the variable-length code cannot simply perform parallel processing on a pixel-by-pixel basis because the data break cannot be recognized unless decoding is actually performed at the time of decoding.

At the time of encoding, for example, if the data of the first pixel and the second pixel are variable length coded by parallel processing and multiplexed, it is determined from where the encoded data of the second pixel starts. The first pixel and the second pixel cannot be simultaneously decoded by parallel processing, because it is not known without first decoding.

Therefore, conventionally, parallel processing has been performed for each image frame in which the delimiter of data can be easily recognized at the time of decoding.

FIG. 2 is a block diagram showing an example of a conventional variable length coding circuit. Here, consider a case where variable length coding is performed by four parallel processes in units of 8 lines. In FIG. 2, the image data input from the input terminal 1 is divided into 8 lines by the separation circuit 13 and is input to the memory circuits 14 to 17. For example, the data of the first line to the eighth line is input to the memory circuit 14, and the data of the ninth line to the sixteenth line is input to the memory circuit 15. After 32 lines of data are written in the memory circuits 14 to 17 by 8 lines, reading is performed at a speed of 1/4 of the writing speed, and the variable length encoders 18 to 21 perform 4 parallel processing of 8 lines by 8 lines. Variable length coding is performed. Variable length encoders 18-21
From each of them, the coded data of 8 lines are output and written in the memory circuits 22 to 25. The multiplexing circuit 26 multiplexes the coded data read from the memory circuits 22 to 25 in order of eight lines and outputs the multiplexed data from the output terminal 2.

On the other hand, in the variable length decoding circuit used in the high-efficiency coding apparatus for television signals, if the data speed of the input data is high and the processing speed of the variable length decoding cannot be met, parallel processing is performed. There is. In that case, the variable-length code cannot simply perform parallel processing on a pixel-by-pixel basis because the data break cannot be recognized unless decoding is actually performed at the time of decoding. Therefore, in the past, parallel processing was performed in image frame units in which data delimiters can be easily identified.

FIG. 6 is a block diagram showing an example of a conventional variable length decoding circuit. Here, it is assumed that the image frame is configured in units of 8 lines as in the case of the above encoding circuit, and the case where variable length decoding is performed by 4 parallel processing in units of 8 lines. In FIG. 6, the variable length coded data input from the input terminal 41 is divided into 8 line units by the separation circuit 57 based on the image frame, and the memory circuit 5
8 to 61 are input. For example, the data of the first line to the eighth line is input to the memory circuit 58, and the data of the ninth line to the sixteenth line is input to the memory circuit 59. After 32 lines of data are written in the memory circuits 58 to 61 by 8 lines, reading is performed at a speed of 1/4 of the writing speed, and the variable length decoders 62 to 65 read 8 lines by 8 lines.
Variable length decoding is performed by parallel processing. Variable length decoder 62-
Decoded data for 8 lines is output from each of 65 and written in the memory circuits 66 to 69. In the multiplexing circuit 70, the data read from the memory circuits 66 to 69 are sequentially multiplexed every eight lines and output from the output terminal 6.

[0008]

However, in the conventional variable-length coding circuit shown in FIG. 2, since the unit of data to be processed in parallel is large, a large memory capacity is required for the memory circuits 14 to 17, and the variable-length coding circuit is required. There are drawbacks that the delay between the input and output of the encoding circuit becomes large and the circuit scale becomes large.

On the other hand, even in the conventional variable length decoding circuit shown in FIG. 6, since the unit of data to be processed in parallel is large,
Since the memory circuits 66 to 69 require a large memory capacity, there is a drawback that the delay between the input and output of the variable length decoding circuit becomes large and the circuit scale becomes large.

The present invention has been made in view of the above-mentioned conventional circumstances. Therefore, the object of the present invention is to provide a novel variable-length coding capable of eliminating the above-mentioned drawbacks inherent in the prior art, It is to provide a decoding circuit.

[0011]

In order to achieve the above object, a variable length coding circuit according to the present invention includes a separation circuit for distributing input image data into n data strings in pixel units, and the separation circuit. N variable length encoders for variable length encoding each of n data strings output from the circuit to output encoded data and word number information thereof, and encoded data output from the variable length encoders. N memory circuits to be stored, and n data strings output from the memory circuits are alternately arranged in word units and multiplexed with the word number information output from the variable length encoder, and the n memory And a multiplexing circuit that outputs a read clock to the circuit.

The variable length decoding circuit according to the present invention is
The image signal is divided into n groups on a pixel-by-pixel basis, variable-length coded, and the word for each of the n coded data is multiplexed with the coded data alternately multiplexed for each word of the coded data. A separation circuit that separates into n coded data strings based on the number information and outputs together with a clock signal, and n coded data strings that are output from the separation circuit are written using the clock signal. A memory circuit and n variable-length decoders for variable-length decoding the n data strings read from the n memory circuits, respectively.
And a multiplexing circuit for multiplexing n pieces of decoded data output from the variable length decoder for each pixel and arranging them in the order of normal image data.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will now be described with reference to the drawings for each of its preferred embodiments.

FIG. 1 is a block diagram showing an embodiment of a variable length coding circuit when the present invention is applied to a coding circuit.

Referring to FIG. 1, the input terminal 1 is a terminal to which image data is input, and is connected to the separation circuit 3. The four outputs of the separation circuit 3 are variable length encoders 4 respectively.
Connected to ~ 7. The variable length encoders 4 to 7 each have two outputs, one of which is connected to the multiplexing circuit 12 through the memory circuits 8 to 11 and the other of which is directly connected to the multiplexing circuit 12. The clock output of the multiplexing circuit 12 is connected to the memory circuits 8 to 11, and the data output is connected to the output terminal 2.

Here, consider a case where the image data is subjected to variable length coding by four parallel processing in pixel units. The image data input from the input terminal 1 is distributed to the variable length encoders 4 to 7 in order by pixel in the separation circuit 3. For example, the data of the first pixel is stored in the variable length encoder 4, the data of the second pixel is stored in the variable length encoder 5, and the data of the third pixel is stored in the variable length encoder 6.
Then, the data of the fourth pixel is distributed to the variable length encoder 7. The variable length encoders 4 to 7 convert the input data into variable length codes having a word length of 1 to 16 bits and output them in 16-bit parallel.

In the multiplexing circuit 12, the coded data output from the variable length encoders 4 to 7 are alternately multiplexed in units of 16-bit words.
In the case of a variable-length code of 16 bits, 16 pieces of data are input and one piece of encoded data of 16-bit is output. In the case of a variable-length code of word length 16 bits, one input data is Since 16-bit coded data is output as one, the coded data is not output continuously,
After writing to the memory circuits 8 to 11, the data is read at the timing of multiplexing. The read clock is generated by the multiplexing circuit 12 and output to the memory circuits 8-11. The data read from the memory circuit 8 is A1, A2 ...
... Ak, data read from the memory circuit 9 is B1, B2
……… B1, data read from the memory circuit 10 is C
1, C2, ..., Cm, and the data read from the memory circuit 11 is D1, D2, ..., Dn, in the multiplexing circuit 12, as shown in f of FIG. 4, A1, B1, C1, D1, A2, B2. Output in the order of .... The values of k, l, m, n are generally not equal. For example, if m <k, m <l, m <n, the multiplexed data is ... Am, Bm, Cm, Dm, Am + 1, Cm + 1, D
m + 1 ... In this case, if the receiving side does not know the values of k, l, m, and n, this data is written as ... Am, Bm, Cm, Dm, Am + 1, Bm + 1, C
Since it is interpreted as m + 1, Dm + 1 ..., The values of k, 1, m, and n, which are the number of words of each encoded data, are also multiplexed together with the encoded data and transmitted.

FIG. 3 is a block diagram showing an example of the structure of the multiplexing circuit 12. In FIG. 3, input terminals 120 to 12
Reference numeral 3 is a terminal to which encoded data output from the memory circuits 8 to 11 is input, and is connected to a data input of the selection circuit 27. The input terminals 124 to 127 are terminals to which the number of words of the encoded data output from the variable length encoders 4 to 7 is input, and four of the five data inputs of the counting circuits 29 to 32 and the selection circuit 28 are input. Connected to one input. The other input of the selection circuit 28 is connected to the output of the selection circuit 27. Counting circuits 29 to 32
Output of the control signal generation circuit 33 and the clock generation circuit 34.
It is connected to the. The output of the control signal generation circuit 33 is the selection control input of the selection circuit 27, and the output of the clock generation circuit 34 is the clock input and output terminal 1 of the counting circuits 29 to 32.
28, and the output of the selection circuit 28 is connected to the output terminal 129.

In FIG. 3, the counting circuits 29 to 32 normally output the "L" level, but when the counted value exceeds the number of data words input from the input terminals 124 to 127, the "H" level is output. To be done. Counting circuits 29-3
According to the output pattern of 2, the selection control signal of the selection circuit 27 is output from the control signal generation circuit 33. The read clock output to the memory circuits 8 to 11 is generated by the clock generation circuit 34 and output from the output terminal 128. Since the variable-length encoders 4 to 7 are processed with the clock divided by 4 for the input / output data of the variable-length encoder, the clock generator 34 outputs the divided-by-4 clock at the start of multiplexing the encoded data. Is output. When one of the output signals from the counting circuits 29 to 32 becomes "H" level, the clock generation circuit 34 outputs a frequency-divided clock of 3, and when the number of two output signals becomes "H" level, a frequency-divided clock of 2 and three "H" level. When the level is reached, a clock without frequency division, 4 "H"
When the level is reached, the clock is stopped because the encoded data is completed.

FIG. 4 is a time chart showing the operation of the multiplexing circuit of FIG. a is a clock for input / output data of the variable length coding circuit, and b to e are counting circuits 29 to 29, respectively.
32, the output f of the selection circuit 28, and g the clock output from the clock generation circuit 34. In f, first, the selection circuit 28 inputs the input terminal 1
The numbers k, l, m, and n of the encoded data input from 24 to 127 are selected, and the selection circuit 27 starts from time t1.
The encoded data to be output is selected.

In FIG. 4, k = 5, l = 3, m = 1, n = 3
, The values of k, l, m and n are set in the counting circuits 29 to 32 at time t1. At this time, b to e are at “L” level, and f outputs A1, B1, C1, and D1. At t2, the counting circuits 29 to 32 are counted up, and only d becomes "H" level. The selection control signal of the selection circuit 27 is output from the control signal generation circuit 33 according to the patterns b to e, and A2, B2, and D2 are selected by the selection circuit 27 and output to f. Since only d of b to e is at the “H” level, the clock generation circuit 34 outputs the divided-by-3 clock at t3, which is three clocks after the clock from t2 to a as shown in g. Similarly, A3, B3,
D3, A4 and A5 are output.

Next, the decoding circuit according to the present invention will be described.

FIG. 5 is a block diagram showing an embodiment of a variable length decoding circuit when the present invention is applied to the decoding circuit.

Referring to FIG. 5, the input terminal 41 to which the variable length coded data is input and the input terminals 42 to 45 to which the respective word numbers of the four types of data included in the variable length coded data are input are separated. It is connected to the circuit 47. The four data outputs and the four clock outputs of the separation circuit 47 are connected to the memory circuits 48 to 51, respectively. The outputs of the memory circuits 48 to 51 are connected to the variable length decoders 52 to 55, respectively, and the outputs of the variable length decoders 52 to 55 are connected to the multiplexing circuit 56. The output of the multiplexing circuit 56 is connected to the output terminal 46.

Now, let us consider a case where the image data is subjected to variable length decoding by four parallel processes in pixel units, as in the above encoding circuit. In order to perform variable length decoding with the variable length decoding circuit in FIG. 5, it is necessary to perform four parallel processing in pixel units and multiplex in word units also at the time of encoding. FIG. 7 shows the format of the variable length coded data input to the input terminal 41. The variable length coded data is divided into four groups A, B, C and D which are processed in parallel, and the data of each group are alternately multiplexed for each word. The group is divided into pixel units, and the groove A has the first, fifth, and ninth groups.
...... Pixel, group B is the second, sixth, tenth …… pixel,
The groove C is the third, seventh, eleventh ... Pixel, groove D
Are data obtained by variable-length coding every 4th pixel such as the 4th, 8th, 12th ... Pixel.

The number of words of data in each group is input from the input terminals 42 to 45, respectively. As will be described later, the separation circuit 47 divides the variable-length decoded data input using this word number into each group, and outputs it to the memory circuits 48 to 51 together with the write clock.
The variable length decoders 52 to 55 decode the variable length coded data of each group read from the memory circuits 48 to 51 at a rate of 1/4 of the rate of the data input from the input terminal 41. If the word length of the variable-length code used here is 1 to 16 bits, the amount of data to be read for decoding the data of one pixel changes in the range of 1 to 16 bits.
The memory circuits 48 to 51 convert the data transfer rate.

The decoded data output from the variable length decoders 52 to 55 is multiplexed on a pixel-by-pixel basis by the multiplexing circuit 56 and output from the output terminal 46. That is, after the first pixel of group A decoded by the variable length decoder 52, the second pixel of group B decoded by the variable length decoder 53, and the second pixel of group C decoded by the variable length decoder 54. Three pixels are multiplexed in order of the fourth pixel of group D decoded by the variable length decoder 55. Since this is multiplexing on a pixel-by-pixel basis, a conventional memory circuit is not required.

FIG. 8 is a block diagram showing a configuration example of the separation circuit 47. In FIG. 8, an input terminal 701 is a terminal to which variable length encoded data is input, and is connected to the switch 71. The input terminals 702 to 705 are terminals to which the number of words of the encoded data of each group multiplexed with the variable length encoded data is input, and the counting circuits 72 to 7
Connected to 5. The outputs of the counting circuits 72 to 75 are connected to the control signal generating circuit 76 and the clock generating circuit 77. The output of the control signal generation circuit 76 is connected to the control signal input of the switch 71. Of the five outputs of the clock generation circuit 77, one is used as the clock input of the counting circuits 72 to 75, and the other four are output terminals 710 to 71, respectively.
Connected to 3.

In FIG. 8, the counting circuits 72 to 75 normally output the "L" level, but when the counting values exceed the number of words input from the input terminals 702 to 705, respectively, the counting circuits 72 to 75 become the "H" level. Depending on the output patterns of the counting circuits 72 to 75, the control signal generating circuit 76 switches the switch 71 to the switch 71.
Control signal is output. The write clock output to the memory circuits 48 to 51 is generated by the clock generation circuit 77 and output from the output terminals 710 to 713. The clock generation circuit 77 also generates clocks for the counting circuits 72 to 75.

FIG. 9 is a time chart showing the operation of the separation circuit of FIG. a is variable length encoded data to be input,
b is a clock for input variable-length coded data,
c to f are output signals of the counting circuits 72 to 75, g is an output signal of the control signal generating circuit 36, h to k are clocks output from the output terminals 710 to 713, and l is a clock generating circuit 77 to a counting circuit. It is a clock output to 72-75. Here, the number of words of each data of the groups A to D is 5, as in the above-described encoding circuit,
Set to 3, 1, and 3.

At time t1, the number of words of data in each group is set in the counting circuits 72 to 75. At this time, c ~
f becomes "L" level, and g is Sa, Sb, Sc, Sd.
Are output in order. Here, Sa is a control signal for connecting the switch 71 to the output terminal 706, and Sb is the switch 71.
Is a control signal for connecting the switch 71 to the output terminal 709, Sc is a control signal for connecting the switch 71 to the output terminal 708, and Sd is a control signal for connecting the switch 71 to the output terminal 709.
The control signal generation circuit 76 generates a clock divided by 4 with respect to the clock of b and outputs it to l, and at the same time, an output terminal 706.
Data output from the memory circuits 48 to 51
Output h to k at the timing that can be read by. At t2, the counting circuits 72 to 75 are counted up, and only e is “H”.
Become a level. The control signal g of the switch 71 is output from the control signal generation circuit 76 according to the patterns c to f, and the switches 71 output A2, B2, and D2, respectively.
6, 707 and 709 are connected so as to be output.
Since only e of c to f is at the “H” level, the clock generation circuit 77 generates a clock divided by three with respect to the clock of b and outputs it at the timings h to l. Similarly, A3, B3, D3, A4 and A5 are separated and output.

[0032]

As described above, according to the present invention,
When variable-length coding is performed in parallel to reduce processing speed, parallel processing in pixel units can reduce the memory capacity of peripheral memory circuits, reducing processing delay time and circuit scale. The effect that can be obtained is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a variable length coding circuit according to the present invention.

FIG. 2 is a block diagram showing an example of a conventional variable length coding circuit.

FIG. 3 is a block configuration diagram showing a specific example of a multiplexing circuit 12 shown in FIG.

FIG. 4 is a timing chart explaining the operation of the multiplexing circuit 12 shown in FIG.

FIG. 5 is a block diagram showing an embodiment of a variable length decoding circuit according to the present invention.

FIG. 6 is a block diagram showing an example of a conventional variable length decoding circuit.

7 is a diagram showing a format of variable-length coded data input to the variable-length decoding circuit shown in FIG.

8 is a block configuration diagram showing a specific example of the separation circuit 47 shown in FIG.

9 is a timing chart explaining the operation of the separation circuit 47 shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Input terminal 2 ... Output terminal 3, 13 ... Separation circuit 4-7, 18-21 ... Variable-length encoder 8-11, 14-17, 22-25 ... Memory circuit 12, 26 ... Multiplexing circuit 27, 28 ... selection circuit 29-32 ... counter circuit 33 ... control signal generation circuit 34 ... clock generation circuit 41-45 ... input terminal 46 ... output terminals 47, 57 ... separation circuit 48-51, 58-61, 66-69 ... memory circuit 52-55, 62-65 ... Variable length decoder 56, 70 ... Multiplexing circuit 71 ... Switch 72-75 ... Counting circuit 76 ... Control signal generating circuit 77 ... Clock generating circuit

Claims (3)

[Claims] 1. A separation circuit that distributes input image data into n data strings on a pixel-by-pixel basis, and n data strings output from the separation circuit are each variable-length coded to coded data and its words. N variable-length encoders that output numerical information, n memory circuits that store encoded data output from the variable-length encoders, and n data strings output from the memory circuits as words A variable length code which is alternately arranged in units and which is multiplexed with the word number information output from the variable length encoder and which outputs a read clock to the n memory circuits. Circuit. 2. The multiplexer circuit inputs a first selection circuit for selecting one from n input coded data, a word number of coded data and an output of the first selection circuit. Second selecting circuit, n counting circuits for inputting and counting the number of words, and outputs of the n counting circuits are input, and a selection control signal is output according to the output pattern. 2. The control signal generating circuit according to claim 1, further comprising: a control signal generating circuit which outputs the control signal generating circuit and a clock generating circuit which inputs the outputs of the n counting circuits and generates a read clock of the n memory circuits. Variable length coding circuit. 3. The image signal is divided into n groups on a pixel-by-pixel basis, variable-length coded, and n is multiplexed with coded data that is alternately multiplexed for each word of the coded data.
A separation circuit that separates into n coded data strings based on the word number information for each of the coded data and outputs together with a clock signal, and the n coded data strings output from the separation circuit are the clocks. N variable-length decoders for variable-length decoding n data circuits read from the n-memory circuits, and n variable-length decoders for variable-length decoding, respectively. A variable length decoding circuit, comprising: a multiplexing circuit that multiplexes n pieces of decoded data that are output for each pixel and arranges them in the order of normal image data.