JPH04257184A - Encoding device - Google Patents

Abstract

PURPOSE:To equalize the delay quantity of image data to that of audio data at the time of encoding. CONSTITUTION:Digital image data are encoded by a predictive encoding circuit 14 in encoding frame units with high efficiency and outputted as encoded image data. The encoded image data are stored temporarily in a buffer memory 15 with a write clock and read out as buffer image data at a specific read speed. A delay quantity calculating circuit 16 finds the delay quantity of the buffer image data as a mean delay quantity in units of N (N: integer larger than two) encoding frames predetermined according to the write clock. Then a delay control circuit 17 varies the delay quantity of a delay circuit 18 according to the input level of digital audio data on the basis of the mean delay quantity. Consequently, the audio data which is delayed corresponding to the delay quantity of the buffer image data are outputted as delayed audio data from the delay circuit 18. Those buffer image data and delayed audio data are multiplexed by a multiplexing circuit 19 and sent out as a multiplexed signal.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoding apparatus for highly efficient encoding of image data, and more particularly to an encoding apparatus used for video conferences and the like in which image data and audio data are simultaneously transmitted.

0002

[Prior Art] Conventionally, this type of encoding device includes an encoding circuit that highly efficiently encodes digital image data for each encoded frame and outputs it as encoded image data, and a writing clock that outputs the encoded image data as encoded image data. A buffer memory that temporarily stores the digital audio data based on the data and reads it out as buffered image data at a predetermined readout speed, a delay circuit that delays the digital audio data and outputs it as delayed audio data, and multiplexes the buffered image data and delayed audio data. A multiplexing circuit for sending out a multiplexed signal is provided. When image data is encoded, it is read out from the buffer memory as buffer image data at a predetermined speed.
When considering the amount of information in image data, the amount of delay is greater in image data than in audio data. For this reason, in this type of encoding device, audio data is fixedly delayed in accordance with a pre-calculated average delay time of image data.

0003

[Problem to be Solved by the Invention] When transmitting image data, the amount of information generated changes depending on the movement of the image to be transmitted, the size of the subject, the fineness of the image, etc. The amount of delay of image data changes accordingly. Therefore, as mentioned above, when audio data is fixedly delayed in accordance with the average delay time of image data as in conventional encoding devices, there is a problem that the delay times of image data and audio data cannot be made equal. There is a point. An object of the present invention is to provide an encoding device that can always equalize the delay times of image data and audio data.

0004

[Means for Solving the Problems] According to the present invention, there is provided an encoding circuit that receives digital image data, highly efficiently encodes the digital image data for each encoded frame, and outputs the encoded image data; a buffer memory that temporarily stores converted image data based on a write clock and reads it out as buffered image data at a predetermined readout speed; and a delay circuit that receives digital audio data, delays the digital audio data, and outputs the delayed audio data. and a multiplexing circuit that multiplexes the buffered image data and the delayed audio data and sends it out as a multiplexed signal, wherein the delay circuit is a variable delay circuit, and the delay circuit is a variable delay circuit, and a delay amount calculation circuit that calculates the delay amount of the buffer image data as an average delay amount for each predetermined N (N is an integer of 2 or more) encoded frame; and an input level of digital audio data based on the average delay amount. and a delay control circuit that changes the amount of delay of the delay circuit according to the encoding circuit. Here, the delay amount control circuit includes a determining means that determines the presence or absence of the digital audio data based on the input level and sends out a determination signal, and when the determination signal indicates that there is no audio, the average a first generating means that generates a delay control signal indicating the amount of audio delay based on the amount of delay; and a second generating means that generates a delay hold signal indicating that the amount of delay is maintained when the determination signal indicates that audio is present. and means for holding the delay amount when the delay circuit receives the delay holding signal.

[0005]

EXAMPLES The present invention will be explained below by way of examples. Referring to FIG. 1, the illustrated encoding device has an image data input terminal 11, an audio data input terminal 12, and an output terminal 13.
It is equipped with Digital image data a received at the image data input terminal 11 is given to a predictive encoding circuit 14,
Here, it is highly efficiently encoded and output as encoded image data b. This encoded image data b is temporarily stored in the buffer memory 15 by the write clock, and the buffer image data c is stored at a predetermined speed by the read clock.
It is read as . At this time, the write clock d and the encoded frame pulse e are given to the delay amount calculation circuit 16, and the buffer memory occupation amount f is given to the predictive encoding circuit 14.

[0006] Here, referring to FIG. 2, one encoded frame section is defined as one encoded frame to the frame immediately before being encoded (for example, as shown in FIG.
, frame A to frame E is one encoded frame section), and the delay amount i of image data per one encoded frame section is variable depending on the fixed delay time p in the predictive encoding circuit 14 and the buffer memory 15. It is obtained by adding the delay time q. The variable delay time q is expressed as the time from when one frame of coded image data is written into the buffer memory 15 until when the written data is read out. That is, the variable delay time q can be obtained by measuring the amount of information generated in one encoded frame section and dividing this measured amount of information by the transmission rate. Therefore, the delay amount i is calculated using the formula 1
Represented by In Equation 1, p is the fixed delay time of the predictive encoding circuit, R is the transmission rate, and S is the amount of information generated in one encoded frame.

[0007]

[Math 1]

Referring also to FIG. 3, the write clock d is first given to the first counter 16a, and the first counter 16a counts the number of pulses of the write clock d and sends it out as a first count signal. do. The first counter 16a is reset with an encoded frame pulse e. The first count signal is stored as a count number by the first register 16b, and when the encoded frame pulse e is received, it is given to the ROM 16c as the amount of information S generated in one encoded frame section. ROM16
The delay amount i for each generated information amount S is stored in advance in c based on Equation 1 (here, the fixed delay time p and transmission rate R of the predictive encoding circuit are predetermined). Therefore, when the generated information amount S is received, the delay amount i corresponding to the generated information amount S is sent out from the ROM 16c. This delay amount i is then given to the adder 16d.

The output of a second register 16e, which will be described later, is further added to the adder 16d and added to the delay amount i.
Output as an added delay amount. Second register 16e
Then, when receiving this added delay amount and receiving the encoded frame pulse e, this added delay amount is sent out as an integrated delay amount. This cumulative delay amount (cumulative delay amount up to one encoded frame before) is added to the delay amount i by an adder 16d. In other words,
The second register 16e outputs a delay amount (cumulative delay amount) obtained by sequentially adding up (accumulating) the delay amount in each encoded frame. This cumulative delay amount is then given to the divider 16f.

Further, the encoded frame pulse e is given to a second counter 16g, and when the second counter 16g counts the encoded frame pulse e N times, it outputs a pulse h of N encoded frame periods. Then, this pulse h is transmitted to the delay control circuit 17 and the second register 16e.
given to. The second register 16e is reset upon receiving the pulse h. Therefore, the second register 1
From 6e onwards, the cumulative delay amounts up to N encoded frames are sequentially output. The divider 16f sequentially receives the accumulated integrated values, divides the accumulated integrated values by N, and provides the divided integrated values to the delay control circuit 17 as an average delay value g.

Referring to FIGS. 4 and 5, delay control circuit 1
7 includes a third register 17a, an AND gate 17b, an audio presence/absence determination device 17c, and a ROM 17d. The audio presence/absence determiner 17c receives digital audio data j and sends out a determination signal k according to the input level of digital audio data j. For example, the audio presence/absence determiner 17c outputs a low level as the determination signal k when there is audio, and outputs a high level as the determination signal k when there is no audio.

This determination signal k is applied to an AND gate 17b. Furthermore, an N encoded frame period pulse h is applied to the AND gate 17b. and gate 17b
Then, the judgment signal k and the N encoded frame period pulse h are ANDed, and the AND pulse r is sent out. This AND pulse r is then given to the third register 17a as a calculation result acquisition pulse.

When the third register 17a receives a calculation result acquisition pulse, that is, when it is determined that there is no sound, the third register 17a acquires the average delay value g over that period. Then, when the calculation result acquisition pulse is interrupted, that is, when it is determined that there is audio, the average delay value g at this determination time is held and provided to the ROM 17d as the average delay amount s. This delay amount average value s is expressed by Equation 2. Note that in Equation 2, N is an integer of 2 or more, and ix is the amount of delay of image data in the x (x is 1 to N) encoded frame.

[0014]

[Math 2]

A conversion table is stored in the ROM 17d in advance, and when the average delay amount s is given to the ROM 17d, the average delay amount s is converted into a delay signal t according to the conversion table and output. Here, an example of the above conversion table is shown in FIG. Here, referring to FIGS. 5 and 6, the delay amount i is parallel 8-bit data, and the numerical value shown by the delay amount i in FIG. 5 specifically shows the delay amount in units of one encoded frame. Here, the average delay amount s is “
165", the ROM 17d outputs "2" as the delay control signal t.

Returning to FIG. 1, digital audio data j is received at the audio input terminal 12 and is applied to the delay control circuit 17 as described above. Furthermore, this digital audio data j is given to a delay circuit 18.

Referring to FIG. 7, the delay circuit 18 has n (n is an integer of 2 or more) bit shift registers 18a and m (
(m is an integer of 2 or more) is provided with an input-1 output selector 18b. The shift register 18a receives digital audio data j and outputs the digital audio data j as audio data j(1) to j(m) each having a different amount of delay. The selector 18b receives the audio data j(1) to j(m), selects one of the audio data j(1) to j(m) based on the delay control signal t, and outputs it as delayed audio data u. .

Referring also to FIG. 8, shift register 18a is assumed to be a 16-bit shift register, and selector 18b is assumed to be a 4-input-1-output selector. In this case, the shift register 18a outputs audio data j
(1) to j(4) are output, but the audio data j(1)
), j(2), j(3), and j(4) are 4 bits, 8 bits, and 12 bits, respectively, for digital audio data j.
bit, and data delayed by 16 bits. When the delay control signal t is "0", the selector 18b selects audio data j(1) and outputs it as delayed audio data u. Similarly, in the selector 18b, the delay control signal t
When is "2", audio data j(3) is selected and output as delayed audio data u.

Referring again to FIG. 1, the above-mentioned buffered image data c and delayed audio data u are applied to a multiplexing circuit 19, where they are multiplexed and sent out from an output terminal 13 as a multiplexed signal.

[0020]

Effects of the Invention As explained above, in the present invention, the amount of delay of audio data is controlled based on the amount of delay of image data. Even if the amount of information from the buffer memory changes, that is, even if the amount of delay of image data changes, there is an effect that the amount of delay between image data and audio data can always be made equal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an encoding device according to the present invention.

FIG. 2 is a timing diagram for explaining calculation of the amount of delay of image data.

FIG. 3 is a block diagram for explaining the delay amount calculation circuit shown in FIG. 1;

FIG. 4 is a block diagram for explaining the delay amount control circuit shown in FIG. 1;

FIG. 5 is a timing diagram for explaining the operation of the delay amount control circuit.

FIG. 6 is a diagram showing an example of a conversion table stored in the ROM shown in FIG. 4;

7 is a block diagram for explaining the delay circuit shown in FIG. 1. FIG.

FIG. 8 is a timing diagram for explaining the operation of the delay circuit.

[Explanation of symbols]

11 Image data input terminal 12 Audio data input terminal 13 Output terminal 14 Predictive coding circuit 15 Buffer memory 16 Delay amount calculation circuit 17 Delay control circuit 18 Delay circuit 19 Multiplexing circuit

Claims (2)

[Claims] 1. An encoding circuit that receives digital image data, highly efficiently encodes the digital image data for each encoded frame, and outputs the encoded image data as encoded image data; a buffer memory that stores and reads out buffered image data at a predetermined readout speed; a delay circuit that receives digital audio data, delays the digital audio data, and outputs the delayed audio data; and the buffered image data and the delayed audio. In the encoding device having a multiplexing circuit that multiplexes data and sends it out as a multiplexed signal, the delay circuit is a variable delay circuit, and the delay circuit is a variable delay circuit, and a predetermined value of N (N is 2 (integer greater than or equal to)) a delay amount calculation circuit that calculates the delay amount of the buffer image data as an average delay amount for each encoded frame, and a delay amount calculation circuit that calculates the delay amount of the delay circuit according to the input level of digital audio data based on the average delay amount. An encoding circuit comprising: a delay control circuit that changes the delay. 2. The encoding circuit according to claim 2, wherein the delay amount control circuit includes determining means for determining the presence or absence of the digital audio data based on the input level and transmitting a determination signal; a first generating means for generating a delay control signal indicating an amount of audio delay based on the average delay amount when the determination signal indicates that there is no audio; second generating means for generating a delayed hold signal indicating holding, wherein the delay circuit holds the amount of delay when receiving the delayed hold signal.