JP2000209584A - Fast motion shot control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a fast motion shot control circuit for an encoding device receiving a digital video signal by which excellent image quality is obtained and occurrence of dispersion in a frame rate is suppressed. SOLUTION: The fast motion shot control circuit 10 receives a video frame synchronizing signal (b) and a buffer memory occupied amount (g) and outputs a proper fast motion shot control signal (c) to an encoding circuit 20 on the basis of a relation among a plurality of preset thresholds Th1, Th2 and the buffer memory occupied amount (g). For example, the fast motion shot control circuit 10 selects 1/2 fast motion shot where encoding is conducted once per 2-frames when the buffer memory occupied amount (g) does not exceed the threshold Th1. When the buffer memory occupied amount (g) exceeds the threshold Th1 and there exists a danger of occurrence of buffer overflow, the control circuit 10 selects 1/4 fast motion shot where encoding is conducted once per 4-frames. It is preferred that a hysteresis is provided to the selection so that 1/4 fast motion shot continues until the generated code amount decreases and the buffer memory occupied amount (g) is less than the threshold Th2. When the buffer memory occupied amount (g) is lower than the Th2, the selection is restored to 1/2 fast motion shot.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image encoding and transmitting apparatus, and more particularly to an image encoding and transmitting apparatus used in the apparatus.

[0002]

2. Description of the Related Art In an image coding transmission apparatus for transmitting image information using a relatively low-speed transmission path, it is impossible to encode all input images and transmit all of them. . For this reason, it is common to employ a "frame dropping" technique for reducing the number of frames of an input image, and to transmit image information according to the capacity of the transmission path. In this specification, the number of image frames transmitted within a certain period of time will be referred to as "frame rate".

Heretofore, it has been general to use one of two methods for performing the "stripping". That is, one is an "unequal frame dropping method" in which it is determined whether or not "frame dropping" should be performed for each frame according to the amount of code generated as a result of encoding. The other is a "uniform frame dropping method" in which frames are dropped so as to have a predetermined frame rate before encoding. Less than,
Both of these methods will be described with reference to FIGS.

First, FIG. 10 shows a block diagram of the "uneven frame dropping method", and FIG. 11 shows a timing chart for explaining the operation. This method uses a frame dropping circuit 1-1, an encoding circuit 1-2, a buffer memory circuit 1-
3, a buffer memory occupancy calculation circuit 1-4, a frame removal control circuit 1-5, and a line interface 1-7. The frame dropping circuit 1-1 includes a frame dropping control circuit 1--1.
The digital video input signal 1-a input to the input terminal 1-6 is dropped under the control of the dropping control signal 1-h from 5.

[0005] The frame dropping circuit 1-1 is provided with a coded input data.
The frame 1-b and the frame valid signal 1-c indicating the dropped frame are input to the encoding circuit 1-2. Encoding circuit 1
2 encodes the coded input data 1-b based on the frame valid signal 1-c and the buffer memory occupancy 1-g from the buffer memory occupancy calculation circuit 1-4.

The encoding circuit 1-2 inputs the encoded data 1-d to the buffer memory circuit 1-3,
The clock 1-e is input to the buffer memory circuit 1-3 and the buffer memory occupancy calculation circuit 1-4. The buffer memory circuit 1-3 converts the encoded data 1-d into a clock 1-e.
And outputs smoothed data 1-i smoothed to the speed required by the line interface 1-7 to the line interface 1-7.

Next, a buffer memory occupancy calculation circuit 1-
4 counts the above-mentioned clock 1-e and the line clock 1-f from the line interface 1-7 to calculate the amount of encoded data stored in the buffer memory circuit 1-3. The indicated buffer memory occupancy 1-g is output to the encoding circuit 1-2 and the frame drop control circuit 1-5.
The buffer memory occupation amount 1-g is compared with a preset threshold value Th by a frame removal control circuit 1-5, and a frame removal control signal 1-h indicating whether or not to perform frame removal.
Is output to the frame dropping circuit 1-1.

In the case of the "unequal frame removal method", the encoding circuit 1-2 uses the buffer memory occupancy 1-g
The generated code amount is adjusted by controlling the image quality control parameters such as quantization based on the frame rate and controlling the frame rate by frame dropping. When the generated code amount is small, the frame rate is correspondingly improved, and when the generated code amount is large, the frame is dropped, so that there is an advantage that the image quality can be easily maintained at a constant quality.

In FIG. 11, (A) shows a digital video input signal 1-a, encoded input data 1-b, and a frame.
5 shows the system valid signal 1-c. FIG. 11B shows the time change of the buffer memory occupancy 1-g together with the frame drop threshold Th. FIG. 11 (C) shows a frame control signal 1-h which is a result of comparing the buffer memory occupancy 1-g of FIG. 11 (B) with the frame threshold Th.

Next, the "uniform frame dropping method" will be described with reference to the block diagrams and timing charts of FIGS. This method also has a configuration similar to the “uneven frame dropping method”. That is, the frame dropping circuit 2-1, the encoding circuit 2-2, the buffer memory circuit 2-3, the buffer memory occupancy calculating circuit 2-4, and the frame dropping control circuit 2-
5 and a line interface 2-7.

The frame dropping circuit 2-1 drops the digital video signal 2-a input to the input terminal 2-6 based on the frame dropping control signal 2-h output from the frame dropping control circuit 2-5. I do. This top dropping circuit 2-1
Outputs the framed encoded data 2-b and the frame valid signal 2-c indicating the frame dropped to the encoding circuit 2-2. The encoding circuit 2-2 converts the encoded data 2-b based on the frame valid signal 2-c and the buffer memory occupancy 2-g from the buffer memory occupancy calculation circuit 2-4. It encodes and outputs encoded data 2-d and clock 2-e.

The buffer memory circuit 2-3 stores the encoded data.
After storing the data 2-d by the clock 2-e and reading it out with the line clock 2-f from the line interface 2-7, the data is smoothed to the speed required by the line interface 2-7. The smoothed data 2-i is transferred to the line interface 2-
7 is output.

The buffer memory occupancy calculation circuit 2-4
By counting the clock 2-e and the line clock 2-f, the buffer memory occupation amount 2-g indicating the amount of encoded data stored in the buffer memory circuit 2-3 is calculated. Output to 2. Top removal control circuit 2-5
The frame-dropping control signal 2-h is output to the frame-dropping circuit 2-1 so that the frame rate becomes a predetermined frame rate.

In the case of the "equal dropping method",
The encoding circuit 2-2 adjusts the generated code amount by image quality control parameters such as quantization based on the buffer memory occupancy amount 2-g. FIG. 12 shows the digital video input signal 2-a, the encoded input data 2-b, and the frame valid signal 2
-C and the buffer memory occupancy 2-g.

[0015]

However, there are various problems in the above-mentioned prior art. First, in the case of the "equal dropping method", even if the generated code amount is small,
Images can only be transmitted at a fixed frame rate. The reason is that, in the case of uniform dropping, in order to determine the average frame rate that can be transmitted from the target transmission path speed and the required image quality in advance, and to drop the frame before inputting it to the encoding unit, In the case where the code amount generated as a result of encoding is average, it is possible to obtain an image having relatively good image movement and image quality. On the other hand, even when the code generation amount is small, the image can be transmitted only at the determined frame rate.

As another problem, if the amount of generated codes is large in equal frame dropping, the image quality is extremely deteriorated. The reason is that, when the generated code amount is large because the frame rate to be encoded is constant, the image quality is adjusted in a direction to suppress the generated code amount.

In the case of the "uneven frame dropping method", the frame rate varies, and the decoded image moves jerky. The reason for this is that if the amount of generated information increases when the image quality is to be kept constant, frame dropping occurs. However, since the amount of information does not increase or decrease in a fixed cycle, the cycle in which the frames are dropped becomes uneven.

[0018]

Means for Solving the Problems To solve the above-mentioned problems, the frame removing control circuit according to the present invention employs the following characteristic configuration.

(1) An input of a digital video signal is encoded by an encoding circuit, stored in a buffer memory circuit, read out by a line clock from a line interface, and smoothed data is output to the line interface. The frame drop control circuit includes a frame drop control unit that selects one of a plurality of frame drop numbers according to a buffer memory occupancy of the buffer memory circuit and performs a frame drop. Top control circuit.

(2) The frame drop control means compares the buffer memory occupancy with a plurality of thresholds and controls the frame drop with a hysteresis characteristic (1).
Saw removal control circuit.

(3) The frame drop control means compares a different threshold value with the buffer memory occupancy.
And the second comparator, and a flip-flop that receives the output of both comparators at a set and reset input terminal and outputs a threshold determination result.

(4) A pair of comparators for comparing the first and second threshold values with the buffer memory occupancy, a frame synchronization signal counting circuit for receiving a video frame synchronization signal and a frame drop control signal, respectively; A frame period selecting circuit for outputting a frame period in response to an output of the frame synchronization signal count and an output of the pair of comparators, and a code for encoding a digital video signal input by the frame control signal Control circuit that controls the conversion circuit.

(5) The above-mentioned frame drop cycle is either a half-frame drop or a quarter-frame drop.
Saw removal control circuit.

[0024]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a preferred embodiment of a frame removing control circuit according to the present invention; FIG.

The present invention improves the frame rate when the generated code amount is small, and improves the image quality when the generated code amount is large, by controlling the amount of uniform dropping before encoding according to the generated code amount. In addition, it is intended to improve the variation of the frame rate in non-uniform frame dropping.

Therefore, in the present invention, the intervals at which uniform dropping is performed are controlled according to the buffer memory occupancy. Specifically, there is provided an adaptive top-down circuit for selecting one from several top-down numbers according to the buffer memory occupancy and instructing the top-down.

FIG. 1 shows input / output signals to / from an adaptive frame-dropping circuit or a frame-dropping control circuit. FIG. 2 is a detailed block diagram of the frame-dropping control circuit shown in FIG.

First, a description will be given with reference to FIG. The first threshold value Th1 and the second threshold value Th2 are input to the frame drop control circuit 10 together with the buffer memory occupancy g and the video frame synchronization signal b. In addition, this frame removal control circuit 1
From 0, a frame drop control signal C is output.

As shown in the detailed block diagram of FIG. 2, the frame removal control circuit 10 controls the buffer memory occupancy g to 1/4.
A comparator 11 for comparing with the frame drop threshold Th1, a comparator 12 for comparing the buffer memory occupation amount g with the 1/2 frame drop threshold Th2, and comparison outputs k and l of these comparators 11 and 12 are represented by S ( Set), an S / R flip-flop 13 input to an R (reset) terminal, a frame synchronization signal counting circuit 14, a comparator 15, a frame drop cycle selection circuit 1
6 and a flip-flop 17.

CLK of the frame synchronization signal counting circuit 14
The (clock) terminal receives the video frame synchronization signal b, and the RST (reset) terminal receives the frame control signal c output from the comparator 15. The count value n of the frame synchronization signal counting circuit 14 is input to the comparator 15 and compared with the frame drop period p which is the output of the frame drop period selection circuit 16.

The threshold value determination result m from the S / R flip-flop 13 is input to the D terminal of the flip-flop 17 and its CLK terminal is supplied to the above-described frame drop control signal c.
Is entered. The Q output of the flip-flop 17,
The frame drop cycle selection signal 0 is input to the frame drop cycle selection circuit 16, and the above-mentioned frame drop cycle p is output from an output terminal thereof.

Next, the operation of each part of the frame removal control circuit 10 of FIG. 2 will be described with reference to the timing chart of FIG. The (video) frame synchronization signal b is input to the frame synchronization signal counting circuit 14 and counted, and outputs a frame synchronization signal count value n. The comparator 15 compares the frame synchronization signal count value n with the frame drop period p selected by the period selection circuit 16. When n = p, when the frame drop control signal c is at the H (high) level and the rising edge of the frame synchronization signal b is input,
The frame synchronization signal counting circuit 14 is reset.

The comparator 11 calculates the buffer memory occupancy g
And a quarter-threshold drop Th1. Th1
In the case of <g, the drop detection signal k is set to L (low) level. On the other hand, the comparator 12 compares the buffer memory occupancy g with the half-threshold threshold Th2. Th
When 2> g, the frame drop detection signal 1 is set to L level. The S / R flip-flop 13 is set when the frame drop detection signals l and k are at the L level, is reset when the frame drop detection signal l is at the L level, and outputs a threshold determination result m. This operation can prevent the frame rate from varying in a short cycle because the switching from the number of frame removal at a certain threshold to the number of frame removal at another threshold operates in a hysteretic manner.

The flip-flop 17 calculates the threshold value m
Is held at the rise of the frame drop control signal c, and the frame drop cycle switching signal o is output. The frame-dropping period selection circuit 16 selects 1/2 frame-dropping when the frame-dropping period selection signal o is at the L level, and performs the quarter-frame dropping when the frame-dropping period selection signal o is at the H level. select. The value selected as the frame drop period P is (cycle-
1) is selected.

In this embodiment, "1" is set in the case of half-frame coding in which encoding is performed once every two frames, and "3" is set in the case of quarter-frame coding in which coding is performed once every four frames. Select By selecting an appropriate value as the frame drop period, required image quality and frame rate can be realized. Since the amount of generated information is small, the frame rate can be increased if the buffer memory occupancy is small even if the image quality is increased to a certain level or more. In addition, when the buffer memory occupancy is large even if the image quality is increased to a certain level or more because the amount of generated information is large, the frame rate can be reduced to improve the image quality.

Next, with reference to FIG. 4, an application example of the frame removing control circuit 10 of the present invention will be described. The image encoding device in FIG. 4 includes an encoding circuit 20, a buffer memory circuit 30, a memory occupancy calculation circuit 40, and a line interface 50.
Used together with the frame drop control circuit 10.

The digital video signal a is input from the input terminal 21 to the encoding circuit 20. The video frame synchronization signal b is input from the input terminal 22 to the encoding circuit 20 and the frame drop control circuit 10. Further, a clock i is input from the terminal 23 to the encoding circuit 20. As described above, the frame drop control circuit 10 receives the video frame memory synchronization signal b, the buffer memory occupancy g, and the thresholds Th1 and Th2 as inputs, and outputs the frame drop control signal c to the encoding circuit 2.
Output to 0.

The buffer memory circuit 30 includes the encoding circuit 2
From 0, the encoded data d and the encoded data write signal e are received, and the data is read by the line clock f from the line interface 50 so as to output the smoothed data h to the line interface 50. The memory occupancy calculation circuit 40
Upon receiving the coded data storage clock e and the line clock f, the buffer memory occupancy g is output to the coding circuit 20 and the frame drop control circuit 10.

FIG. 5 shows the configuration of the buffer memory circuit 30. The buffer memory circuit 30, as shown in FIG.
Encoded data d is input to an I terminal, and a write clock e and a line (read) clock f are input to a WCLK (write clock) terminal and an RCLK (read clock) terminal, respectively. The semiconductor IC memory outputs the smoothed data h from the DO terminal.

FIG. 6 shows the memory occupancy calculating circuit 40 shown in FIG.
The detailed block diagram of FIG. This memory occupancy calculation circuit 4
0 is a flip-flop (hereinafter abbreviated as FF) 41, 4
2, 43, 44, AND gates 45, 46, comparator 47
And an up-down counter 48. The write clock e and the line clock f are input to the D terminals of the flip-flops FF41 and FF42, respectively, and the video data input clock i is input to the CLK (clock) terminal. The Q outputs of the flip-flops FF41 and FF42 are input to the D terminals of the flip-flops FF43 and FF44, respectively.
The same video data input clock i as the flip-flops FF41 and FF42 is input to the CLK terminal.

These four flip-flops FF41-FF41
44 Q or! A delay 1 write clock q, a delay 2 write clock r, a delay 1 read clock t, and a delay 2 read clock u are output from a Q (inverted Q) output terminal. The clocks q and r are input to the AND gate 45, and the clocks t and u are input to the AND gate 46. The differential write clock s and the differential read clock v are input to both input terminals of the comparator 47, respectively. The comparator 47 outputs the up-down counter control signal w to the UP-
Input to the / DOWN terminal. Up / down counter 48
Receives the video data input clock i at the CLK terminal,
The buffer memory occupancy g described above is output from the Q terminal.

Next, the operation of the circuits shown in FIGS. 4 to 6 will be described with reference to the timing charts of FIGS.
The encoding circuit 20 encodes the digital video signal a in accordance with the video frame synchronization signal b, the frame drop control signal c, and the buffer memory occupation amount g, and encodes the encoded data d and the encoded data write signal ( Clock) f is output.
In the buffer memory circuit 30, the encoded data d is stored by the encoded data write clock e. The buffer memory circuit 30 is a FIFO (first in, last out) memory.

The encoded data stored in the FIFO memory 30 is read by the line clock f output from the line interface 50, and is input to the line interface 50 as smoothed data h. The buffer memory occupancy calculation circuit 40 outputs the amount of coded data remaining in the FIFO memory 30 as the buffer memory occupancy g based on the coded data storage clock e and the line clock f. The operation of the buffer memory occupancy calculation circuit 40 is as follows.
Those skilled in the art can easily understand from the timing chart of FIG. Each signal i, e, f, q, r, t, u,
s, v, w and g correspond to input / output signals to and from each circuit element in FIG.

The input / output signals s, v and w of the comparator 47 of the buffer memory occupancy calculating circuit 40 shown in FIG. 6 and the operation of the up / down counter 48 are summarized as shown in FIG.

The encoding circuit 20 adjusts the generated code amount so that the buffer memory occupation amount g does not exceed the maximum capacity (buffer overflow) or zero (buffer underflow). If the generated code amount is large and there is a risk that the buffer memory occupation amount g may cause a buffer over simply by adjusting the generated code amount at the time of encoding, it is necessary to increase the number of frames to be dropped.

In the example shown in FIG.
If the buffer memory occupation amount g does not exceed the threshold value Th1, a value of 0 is selected to be a half-frame drop which performs encoding once every two frames. Buffer memory occupancy g is threshold value Th
In this case, when the number exceeds 1 and there is a risk of buffer overflow, encoding is performed once every four frames.
Select top drop. It is preferable to provide a hysteresis in the 1/4 frame dropping so that the generated code amount decreases and the buffer memory occupation amount g continues until the buffer memory amount g falls below the threshold Th2. When the buffer memory occupation amount g becomes smaller than Th2, the operation returns to the こ -step.

As described above, by selecting the cycle of frame removal in accordance with the buffer memory occupancy g, it is possible to increase or decrease the generated code amount which cannot be followed only by the code amount control by encoding. When the generated code amount is small, the frame rate increases accordingly, and when the generated code amount is large, there is an advantage that it is easy to keep the image quality constant because frame dropping occurs. Further, by giving hysteresis to the selection of the frame drop cycle, it is possible to suppress the variation of the frame.

Although the preferred embodiment of the frame removal control circuit of the present invention has been described above, this is merely an example,
It goes without saying that various modifications can be made according to the specific application.

[0049]

As can be understood from the above description, according to the frame drop control circuit of the present invention, the period for encoding, that is, the frame drop is appropriately selected based on the buffer memory occupancy of the buffer memory. An optimal image quality and frame can be selected according to the code amount. In addition, according to the frame drop control circuit of the present invention, when the frame rate is adaptively selected, the frame rate is given a hysteresis characteristic, so that a practically remarkable effect that variation in the frame rate hardly occurs is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing input / output signals to a frame removal control circuit according to the present invention.

FIG. 2 is a detailed block diagram of a preferred embodiment of a frame removal control circuit according to the present invention.

FIG. 3 is a timing chart for explaining the operation of the frame removal control circuit shown in FIG. 2;

FIG. 4 is a block diagram of an image encoding apparatus to which the frame removal control circuit shown in FIGS. 1 and 2 is applied;

FIG. 5 is a block diagram of the buffer memory circuit shown in FIG. 4;

FIG. 6 is a detailed block diagram of a buffer memory occupancy calculation circuit shown in FIG. 4;

7 is a timing chart for explaining the operation of the image encoding device shown in FIG. 4;

8 is a timing chart for explaining the operation of the image encoding device shown in FIG. 4;

9 is a timing chart for explaining the operation of the buffer memory occupancy calculation circuit shown in FIG. 6;

FIG. 10 is a block diagram of a conventional unequal frame dropping method.

11 is a timing chart for explaining the operation of each unit shown in FIG. 10;

FIG. 12 is a block diagram of a conventional uniform dropping method.

FIG. 13 is a timing chart for explaining the operation of each unit shown in FIG. 12;

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 frame drop control circuit 11, 12, 15 comparator 13, 17 flip-flop (FF) 14 frame synchronization signal counting circuit 16 frame drop cycle selection circuit 20 coding circuit 30 buffer memory circuit (FIFO) 40 memory occupancy calculation circuit 50 Line interface

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C059 KK34 SS06 TA07 TC15 TD12 UA10 UA32 UA34 UA38 5K034 CC02 HH01 HH02 HH23 HH50 PP01

Claims (5)

[Claims] A digital video signal input is encoded by an encoding circuit, stored in a buffer memory circuit, read out by a line clock from a line interface, and smoothed data is output to the line interface. In the drop control circuit, a frame drop control unit that selects one of a plurality of frame drop numbers according to the buffer memory occupancy of the buffer memory circuit and performs the frame drop at intervals for performing the same frame drop. The feature is a dropping control circuit. 2. The circuit according to claim 1, wherein said frame control means compares the buffer memory occupancy with a plurality of threshold values and controls the frame trimming with a hysteresis characteristic. . 3. The apparatus according to claim 1, wherein the first and second comparators compare different thresholds with the occupancy of the buffer memory, and outputs of the comparators are input to set and reset input terminals. The flip-flop control circuit according to claim 1, further comprising a flip-flop that outputs a threshold determination result. 4. A pair of comparators for comparing the first and second threshold values with the buffer memory occupancy, a frame synchronization signal counting circuit for receiving a video frame synchronization signal and a frame drop control signal, respectively, Output of the number of times the synchronization signal has been counted and 1
A frame drop cycle selection circuit that outputs a frame drop cycle by an output of the pair of comparators, and controls a coding circuit that codes a digital video signal input by the frame drop control signal. Control circuit. 5. The frame removal control circuit according to claim 4, wherein said frame removal period is one of 1/2 frame removal and 1/4 frame removal.