JPS61147690A - Highly efficient code decoding device - Google Patents

Abstract

PURPOSE:To reduce the effect of error transmission, by forming an expected addition code from, for example, the average value of addition codes of eight blocks placed up and down, and right and left of the block concerned, and by replacing this expected addition code with the error addition code when such error code is received. CONSTITUTION:The addition code, namely the minimum level MIN and dynamic range DR, is supplied to an error correction circuit 83 where transmission error is corrected. An error modification circuit 84 is connected to the error correction circuit 83. The error modification circuit 84 makes and adjustment to the addition code which has not been corrected according to the error flag issued from the correction circuit 83. The addition code outputted from the error modification circuit 84 and the encoded code DT which is time-adjusted by a delay circuit 87 are supplied to a decoder 85. The code DT is decoded by the decoder 85, and the original picture element data PD is outputted from an output terminal of the decoder 85.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a high-efficiency code decoding device based on in-field processing of digital television signals, and in particular, to a high-efficiency code decoding device for reducing the effects of transmission errors of additional codes. The present invention relates to a decoding device that corrects code errors.

[Conventional technology]

As methods for encoding television signals through intra-field processing, several methods are known in which the average number of bits per pixel or the sampling frequency is reduced in order to narrow the transmission band.

As an encoding method to lower the sampling frequency, image data is thinned out to 172 by subsampling, and the subsampling point and the position of the subsampling point used during interpolation are indicated (i.e., which subsampling point is above, below or to the left or right of the interpolation point? A method has been proposed that transmits a flag (indicating whether point data is used).

One of the encoding methods that reduces the average number of bits per pixel is D P CM (differenti
alPCM) is known. DPCM focuses on the fact that the pixels of a television signal have a high correlation (and the difference between adjacent pixels is small), and quantizes and transmits this difference signal.

Another encoding method that reduces the average number of bits per pixel is: ① The field screen is subdivided into small blocks, and the deviation of the level distribution of the pixel at the representative point and the data within the block is calculated for each block. There is something to transmit.

An encoding method that attempts to reduce the sampling frequency using subsampling reduces the sampling frequency to 1/2.
Therefore, there was a risk that aliasing distortion would occur.

DPCM has a problem in that coding errors propagate to subsequent coding.

The method of encoding in units of blocks has the disadvantage that block distortion occurs at the boundaries between blocks.

Therefore, the applicant of the present application has proposed a high-efficiency encoding device that does not suffer from the problems of the above-mentioned conventional techniques, such as occurrence of aliasing, error propagation, and occurrence of block distortion.

This high-efficiency encoding device calculates the dynamic range (difference between maximum level and minimum level) and minimum level for multiple pixels included in a predetermined block within one field, and calculates the compressed quantum according to the dynamic range. This method encodes pixels according to the number of bits.

Since television signals have a correlation in the horizontal and vertical directions, the level of pixel data included in the same block varies little in the stationary portion. Therefore, even if the dynamic range of data DTI after removing the minimum level shared by pixel data in a block is quantized with a smaller number of quantization bits than the original number of quantization bits, almost no quantization distortion occurs. By reducing the number of quantization bits, the data transmission bandwidth can be made narrower than the original one.

[Problem that the invention seeks to solve]

The above-described high-efficiency encoding device has a problem in that block distortion occurs when the additional code defined for each block becomes erroneous data due to a transmission error.

Therefore, in order to reduce the influence of transmission errors on the additional code, processing is performed to encode the error correction code. However, when an error exceeding the correction ability of the error correction code occurs, block distortion still occurs.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a highly efficient code decoding apparatus that can modify the additional code to a value close to the original code when a transmission error occurs in the additional code.

[Means for solving problems]

This invention provides at least two additional codes: a minimum value MIN of a plurality of pixel data, a maximum value MAX of a plurality of pixel data, and dynamic range information DR of a plurality of pixel data included in a predetermined block of a digital television signal. and an encoded code DT that is data obtained by subtracting the minimum value MIN from a plurality of pixel data and that is encoded to a predetermined number of quantization bits. A two-dimensional delay is applied to block B of interest.
Additional code MI in blocks B1 to B8 near O
N, a means for extracting DR and additional codes M I N of neighboring blocks B1 to B8.

A means for generating a predicted additional code for interpolation from DR, an additional code MIN for each block, and additional codes MIN and D received by a flag signal indicating the presence or absence of an error in DR.
If R is in error, the received additional code MIN;
A high-efficiency code decoding device characterized by comprising: means for selecting and outputting a predictive additional code in place of DR;

[Effect]

A predicted additional code is formed using, for example, the average value of the additional codes of eight blocks 81 to B8 located above, below, left and right of the block of interest BO. ° Television signals are correlated in a given area of the same field, so
The predicted additional code has a value close to the additional code of the block of interest. Therefore, if the received additional code is erroneous, the influence of the transmission error can be reduced by replacing the erroneous additional code with the predicted additional code.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 generally shows an example of a high-efficiency code encoder to which the present invention is applied.

For example, an NTSC digital television signal in which one sample is quantized to 8 bits is input to an input terminal indicated by 1. This digital television signal is supplied to a cascade of line delay circuits 2 and 3 and to a cascade of five sample delay circuits 11-15.

A cascade connection of five sample delay circuits 21 to 25 is connected to a connection point between line delay circuits 2 and 3.

A cascade connection of five sample delay circuits 31 to 35 is connected to the output terminal of the line delay circuit 3. Line delay circuits 2 and 3 having a delay amount of one line period, and sample delay circuits 11 to 15.21 to 25.3 having a delay amount equal to the sampling period of the input digital television signal.
1 to 35, one block of pixel data can be obtained simultaneously from the output terminal of each delay circuit.

In FIG. 2, 10 indicates one block, and the solid line indicates the nth consecutive block of the current field, (n+1).
The (n+2)th and (n+2)th lines are shown, and broken lines indicate lines of other fields.

Six pixels included in each of the three lines of the current field constitute one block of (3 lines x 6 pixels). When the pixel data of the (n+2)th line is supplied to the input terminal 1, the pixel data of the (n+1)th line is generated at the output of the line delay circuit 2, and the pixel data of the nth line is generated at the output of the line delay circuit 3. Pixel data is generated. The six pixel data of each line are taken out from the input terminal, the output terminal, and between each stage of the cascade connection of the sample delay circuit.

Six pixel data of the same line extracted by the cascade connection of sample delay circuits 11 to 15 are supplied two by two to selection circuits 16, 17 and 18.

Six pixel data of the same line extracted by the cascade connection of sample delay circuits 21 to 25 are supplied two by two to selection circuits 26, 27, and 28. Sample delay circuit 31
.about.35 pixel data of the same line taken out by cascade connection are supplied two by two to selection circuits 36, 37, and 38. These selection circuits compare the levels of two input pixel data, output pixel data with a higher level to one output terminal, and output pixel data with a lower level to the other output terminal. This is a digital level comparison circuit configured as follows.

One output terminal of the selection circuits 16 and 17 is the selection circuit 41
The other output terminals of the selection circuits 16 and 17 are connected to the input terminal of the selection circuit 51. One output terminal of selection circuits 18 and 26 is connected to an input terminal of selection circuit 42, and the other output terminal of selection circuits 18 and 26 is connected to an input terminal of selection circuit 52. One output terminal of the selection circuits 27 and 28 is connected to the input terminal of the selection circuit 43, and the other output terminal of the selection circuits 27 and 28 is connected to the input terminal of the selection circuit 53.

One output terminal of the selection circuits 36 and 37 is connected to the selection circuit 44.
The other output terminal of the selection circuits 36 and 37 is connected to the input terminal of the selection circuit 54.

The selection circuits 41 to 44 are digital level comparison circuits configured to compare the levels of two input pixel data and selectively output only the pixel data with the higher level. The selection circuits 51 to 54 select the input 2
This is a digital level comparison circuit configured to compare the levels of two pixel data and selectively output only the pixel data of the smaller level.

The outputs of the selection circuit 41 and the selection circuit 42 are supplied to the selection circuit 45. The outputs of the selection circuit 43 and the selection circuit 44 are supplied to the selection circuit 46. Selection circuit 45 and selection circuit 4
6 is supplied to the selection circuit 47. The output of the selection circuit 47 and the higher level output of the selection circuit 38 are supplied to the selection circuit 48. Selection circuit 45, 46.47.4
Similarly to the selection circuits 41 to 44, 8 selectively outputs pixel data of a higher level. Therefore,
At the output terminal of the selection circuit 48, pixel data of the maximum level MAX among the 18 pixel data in the block 10 is generated.

The outputs of the selection circuit 51 and the selection circuit 52 are supplied to the selection circuit 55. The outputs of the selection circuit 53 and the selection circuit 54 are supplied to the selection circuit 56. Selection circuit 55 and selection circuit 5
6 is supplied to the selection circuit 57. The output of the selection circuit 57 and the lower level output of the selection circuit 38 are supplied to the selection circuit 58. Selection circuit 55, 56.57.5
Similarly to the selection circuits 51 to 54, 8 selectively outputs pixel data of a smaller level. Therefore,
18 in the program 10 is connected to the output terminal of the selection circuit 58.
Among the pixel data, pixel data of the minimum level MIN is generated.

The output of the selection circuit 48 and the output of the selection circuit 58 are supplied to a subtraction circuit 49. By the subtraction circuit 49 (maximum level M
AX-minimum level MIN) is calculated and output terminal 6
An 8-bit dynamic range DR can be obtained. The minimum level MIN is taken out to the output terminal 7 and is also supplied to the subtraction circuit 50.

Pixel data PD generated at the output of the sample delay circuit 35 is supplied to the subtraction circuit 50 via the delay circuit 4. This delay circuit 4 has a maximum level MAX and a minimum level MI.
The amount of delay is equal to the delay caused to detect N as described above.

8-bit pixel data DTI from which the minimum level has been removed is obtained as the output of the subtraction circuit 50.

The dynamic range DR and the pixel data DTI after minimum level removal are supplied to the encoder block 5. The encoder block 5 converts the dynamic range DR into a quantization bit number smaller than the original quantization bit number (in this example,
4 bits), the pixel data DTI after the minimum level removal is determined in which of the divided regions the pixel data DTI is included, and a 4-bit encoded code DT specifying the region is outputted to the output terminal 8. It occurs in The specific configuration of the encoder block 5 will be described later.

As described above, the output terminals 6 and 7 of the encoder shown in FIG.
and the minimum level MIN are obtained, and an encoded code compressed to 4 bits is obtained at the output terminal 8.

One block of the original digital television signal is (3
x6 x 8 bits = 144 bits).

In this example, one block is (3X6X4 bits+1
6 bits = 88 pinto), and the number of bits to be transmitted can be reduced to approximately half. Although not shown, the encoded code DT and additional data DR.

The MIN is encoded with an error correction code and transmitted as serial data (or recorded on a recording medium).

Some examples of the format of transmission data are shown in FIG. Third
In FIG. A, each data portion consisting of the minimum level MIN, dynamic range DR, and encoded code is encoded with an independent error correction code, and the parity of each error correction code is added and transmitted. In FIG. 3B, the minimum level MIN and dynamic range DR are each encoded with independent error correction codes, and the parity of each error correction code is added. In FIG. 3C, a common error correction code is applied to both the minimum level MIN and the dynamic range DR, and parity thereof is added.

In this embodiment, as shown in FIG. 3A or FIG. 3B,
Error correction codes are applied to each of the dynamic range DR and the minimum level MIN.

The encoded code DT obtained at the output terminal 8 of the encoder is in the same order as the input television signal. Therefore,
Additional data MIN for each block.

DR occurs every 3 lines in terms of lines and every 6 samples in the sampling direction.

When the transmission data is divided into each predetermined amount of encoded code DT,
A section that does not include additional data occurs in the transmitted data. Therefore, by connecting a buffer memory to the encoder output,
1 block of additional data DR.

The MIN and encoded code DT may be used as the unit of transmission. In this case, the length of the data portion consisting of the encoded code DT in FIG. 3 is (4 bits x 16).

The smaller the number of quantization bits of the encoded code DT, the better, in order to suppress redundancy. However, in order to avoid increasing quantization distortion, the number of quantization bits must not be set too small. In television signals, each pixel within one block is
Since there is a correlation, the dynamic range DR does not become very large in the stationary part, and the maximum value is 1.
That's enough considering he ranks 28th.

As shown in Figure 4, when the number of quantization bits is 8 bits, the level of the television signal is 25 of (0 to 255).
There are 6 possibilities. However, in a stationary area excluding non-stationary areas such as the outline of an object, the level distribution of the pixels of the block (1) is concentrated in a fairly narrow level range, as shown in FIG. Therefore, if the number of bits of the encoded code is set to 4 bits as in this embodiment, it is possible to prevent quantization distortion from increasing.

That is, the dynamic range DR is 128 in the worst case.
becomes. Even in this case, when the number of quantization bits is 4 bits, the division level unit is 8, and the quantization distortion is 4. This degree of quantization distortion cannot be visually discerned.

On the other hand, in the unsteady part, the variation range becomes large, but in this invention, the dynamic range DR is determined adaptively, so
No drop in response occurs in the transient region.

FIG. 5 shows an example of the configuration of the encoder block 5 described above. However, in order to use Pi in the explanation, the number of quantization bits is set to 2 bits instead of 4 bits, and the dynamic range is divided into 4.

In FIG. 5, 61 indicates an input terminal to which the dynamic range DR is supplied, and 62 indicates an input terminal to which the data DTI after minimum level removal is supplied. The dynamic range DR is set to 1/4 level by a divider 63 (consisting of a bit shift circuit that shifts by 2 bits).

The output of this divider 63 is supplied to multipliers 64 and 65. The output tripled by the multiplier 64 is supplied to one input terminal of the level comparator 66. The output doubled by the multiplier 65 is supplied to one input terminal of the level comparator 67. The output of the divider 63 is supplied to one input terminal of a level comparator 68. These level comparators 6
The data DTI after minimum level removal is supplied to the other input terminal of each of 6, 67, and 68.

The outputs of the level comparators 6s and 67.68 are connected to C1 and C
2 and C3, these outputs CI, C2, and C3 change as follows depending on the level of data DTI.

(11 (3/4) When DR≦DTI≦DR, C1='l
', C2="1°, C3="l"(2) (2/4
)DR:5DTI<(3/4) When DR, C1='O'
, C2="1°, C3="l" (3) (1/4)
DR≦DT I<(2/4) When DR, C1="0"
, C2="O", C3="1" (4) 0≦DTI<(1
/4) At the time of DR, Ct=“0”, C2=’0’, C3
= “O” Output C of the above level comparator 66, 67, 68
1, C2, and C3 are supplied to the priority encoder 69. A 2-bit encoded code DT is obtained at the output terminal 8 by the priority encoder 69. In the case of (11) above, the priority encoder 69
11), in the case of (2) above, generate the coded code of (10), and in the case of (3) above, generate the coded code of (01), (4) above
In this case, an encoded code of (00) is generated.

The pixel data PD including the minimum level within one block varies from the minimum level MIN to the maximum level M, as shown in FIG.
It belongs to the dynamic range DR up to AX. The divider 63 divides this dynamic range DR into four.

Comparators 66, 67, and 68 determine which of the divided level ranges the data DTI after the minimum level has been removed belongs to, and is converted into a 2-bit encoded code corresponding to that level range.

FIG. 7 shows another example of the configuration of the encoder block 5.

The dynamic range DR from the input terminal 61 is determined by the divider 7.
1, the level is set to 1/4.

The output signal of this divider 71 is supplied to a digital divider 70 as a denominator input. Data DTI from input terminal 62 after the minimum level has been removed is supplied to divider 70 as a numerator input. A 2-bit encoded code is extracted from the output of this divider 70. The divider 70 generates a 2-bit output corresponding to a value obtained by cutting off fractions below the decimal point as an encoded code.

Furthermore, although not shown, the encoder block 5 converts the digital DTI and dynamic range D after minimum level removal.
It may also be constructed from a ROM to which a total of 16 bits of R are supplied as addresses.

In this example, as is clear from FIG. 6, the dynamic range is divided equally according to the number of quantization bits, and the median values of each area are Ll, L2, . L3 is used as a value during decoding.

This encoding method can reduce quantization distortion.

On the other hand, pixel data having the minimum level MIN and the maximum level MAX always exist within one block. Therefore, in order to create a large number of encoded codes with an error of O, the dynamic range DR should be changed (
21'-1) (where m is the number of quantization bits), the minimum level MIN may be set as the representative level LO, and the maximum level MAX may be set as the representative level L3.

FIG. 9 shows the configuration on the receiving (or reproducing) side.

The data received from the input terminal 81 is sent to the data separation circuit 82.
supplied to The data separation circuit 82 separates the encoded code and the additional code. The additional code, that is, the minimum level MIN and dynamic range DR, is supplied to an error correction circuit 83 for error correction code, and transmission errors are corrected. An error correction circuit 84 is connected to the error correction circuit 83 . The error correction circuit 84 corrects (interpolates) the additional code that could not be corrected based on the error flag from the error correction circuit 83, as will be described later.

The additional code output from the error correction circuit 84 and the encoded code DT whose timing is matched by the delay circuit 87
is supplied to the decoder 85.

The encoded code DT is decoded by the decoder 85,
The original pixel data PD is taken out to the output terminal 86 of the decoder 86. The decoder 86 decodes 8-bit pixel data PD from each 8-bit additional code DR, MIN and 4-bit encoded code DT.

The decoder 85 has the configuration shown in FIG.

In FIG. 10, the dynamic range DR from the input terminal indicated at 88 is stored in the buffer memory 92. 8
The minimum level MIN from the input terminal indicated by 9 is stored in a buffer memory 92. These buffer memories 91 and 92 are supplied with a block identification signal from a terminal 90 and store an additional code for each block.

Encoded code DT from terminal 87 and buffer memory 9
The dynamic range DR read from 1 is supplied to the decoder block 93. The decoder block 93 decodes the data DTI after the minimum level has been removed. This data DTI and the minimum level MIN read from the buffer memory 92 are added by an adder 94, and pixel data PD is taken out to an output terminal 86 of the adder 94.

The decoder block 93 is for restoring the representative value corresponding to the encoded code DT.

FIG. 11 shows the configuration of an example of the decoder block 93. However, in the decoder blocks shown in FIG. 11 and FIG. 12, which will be described later, the number of quantization bits of the encoded code is set to 1 and 2 bits for Ni2 in the explanation. The decoder block shown in FIG. 11 has a configuration corresponding to the encoder block shown in FIG.

The dynamic range DR from the input terminal 101 is divided by the divider 103 (consisting of a 2-bit bit shifter).
, and is supplied to multipliers 104 and 105. Multiplier 104 triples the output of divider 103, and multiplier 105 doubles the output of divider 103.

The outputs of these multipliers 104 and 105 and the divider 103
The output of the input terminal 10 and a code in which all 8 bits are "0" are supplied to the selector 107.
According to the encoded code DT from 2, one of the four inputs is selected and output.

When the encoded code DT is (00), the selector 107 selects the zero code. The encoding code DT is (01
), the selector 107 selects the output (1/4DR) of the divider 103. When the encoding code DT is (10),
The output (2/4 DR) of the multiplier 105 is selected by the selector 107
chooses. When the encoded code DT is (11), the selector 107 selects the output (3/4DR) of the multiplier 104. The output of this selector 107 is supplied to an adder 109. The adder 109 is supplied with data obtained by dividing the output of the divider 103 by half by the divider 108 . Therefore, the data DTI after minimum level removal is obtained at the output terminal 111 of the adder 109.

FIG. 12 shows another example of the decoder block 85. Another example shown in FIG. 12 has a configuration corresponding to the encoder block shown in FIG. 7.

In FIG. 12, 113 represents (1
/4DR) and the encoded code D from the input terminal 102
This is a digital multiplier that multiplies T. The multiplication output of this multiplier 113 and (1/2DR) from the divider 114
data is supplied to the adder 117. This adder 1
The data DT after minimum level removal is output to the output terminal 118 of 17.
I is taken out.

The encoder in this embodiment described above is configured to simultaneously generate all pixel data within one block.

However, pixel data within a block may be generated sequentially.

In the above explanation, three items are transmitted: the encoded code DT, the dynamic range DR, and the minimum level MIN. However, the minimum level MIN and maximum level MAX may be transmitted as additional codes (or the dynamic range DR and minimum level MIN may be transmitted).

The present invention is applied to the error correction circuit 84 provided on the receiving side described above. FIG. 13 shows the error correction circuit 8
An example of 4 is shown below.

In FIG. 13, 121 is an input terminal for an additional code whose error has been corrected by the error correction circuit 83. This data is supplied to gate circuit 123. Also, 122
An error flag indicating the presence or absence of an error in the dynamic range DR received from the error correction circuit 83 is supplied to the input terminal indicated by . The gate circuit 123 is supplied with a timing signal from the control circuit 124, and the gate circuit 123 is supplied with a timing signal from the control circuit 124.
Only the dynamic range DR is separated into the output of 23. The control circuit 124 is supplied with a line clock and a sampling clock from terminals 125 and 126, respectively, and forms a timing signal for separating the dynamic range DR.

The output signal of the gate circuit 123 is supplied to a cascade of line delay circuits 127 and 128 and to a cascade of block delay circuits 129 and 130. A cascade of block delay circuits 131 and 132 is connected between the stages of line delay circuits 127 and 128. A block delay circuit 133 is connected to the output terminal of the line delay circuit 128.
and 134 cascade connections are connected. Block delay circuits 129-134 each have a delay amount of one block.

The dynamic range DR generated at the output of the block delay circuit 131 is that of the lock BO (see FIG. 14). Block B1 diagonally lower right of the block of interest BO
A dynamic range of 0.01 to 1.0 is generated at the output of the block delay circuit 134. The dynamic range of the block B2 below the pressure block 7 is generated at the output of the block delay circuit 133. The dynamic range of the block B3 diagonally to the lower left of the block of interest BO is generated at the output of the line delay circuit 128.

Similarly, the dynamic range of the block B4 on the right side of the block of interest BO is generated at the output of the block delay circuit 132, and the dynamic range of the block B5 on the left side thereof is generated at the output of the line delay circuit 127. Featured block B
The dynamic range of the block B6 diagonally upper right of O is generated at the output of the block delay circuit 130, and the block B6 of interest
The dynamic range of the block B7 above the block B7 is generated at the output of the block delay circuit 129, and the dynamic range of the block B8 diagonally to the upper left of the block of interest is generated at the output of the gate circuit 123.

The dynamic range of the blocks B1 to B8 near the block of interest BO described above is determined by the adders 135, 136, 137,
138, 139, 140, 141 are totaled.

This total value is generated from the adder 141 and is generated from the divider 142.
(implemented by a bit shift circuit). Divider 142 generates a predicted dynamic range code with a total value of 178. This predicted dynamic range code is supplied to one input terminal of the selector 143. The other input terminal of the selector 143 is supplied with the dynamic range of the target block BO from the block delay circuit 131.

Selector 143 is controlled by an error flag signal from input terminal 122. For example, when the error flag signal is at a low level, it means that the dynamic range of the block of interest is correct.

On the other hand, when the error flag signal is high level, for example,
This means that the dynamic range of the block of interest is incorrect. When the error flag signal is at a low level, the selector 143 selects the dynamic range of the block of interest from the block delay circuit 131. On the other hand, when the error flag signal is at a high level, the selector 143 selects the predicted dynamic range code from the divider 142. The dynamic range information taken out to the output terminal 144 of the selector 143 is supplied to the aforementioned decoder.

Also error correction is made regarding the minimum level received. The configuration of the error correction regarding this minimum level is the same as the error correction regarding the dynamic range DR.

That is, the timing signal formed by the control circuit 154 from the line clock and sampling clock supplied to the terminals 155 and 156 is supplied to the gate circuit 153, so that the minimum level is separated into the output of the gate circuit 153. The minimum level subjected to the decoding process of this error correction code is supplied to line delay circuits 157 and 158 and block delay circuits 159 to 164. By these delay circuits, the first block BO and its neighboring block B
The minimum levels for each of 1 to B8 are taken out at the same time. Adders 165-171 and divider 172 form a predicted minimum level code. Input terminal 152
The selector 173 is controlled by an error flag signal from. The selector 173 replaces the erroneous minimum level with the predicted minimum level code. Selector 173
The minimum level extracted at the output terminal 174 of is supplied to the decoder.

This invention can also be applied when the block is one-dimensional. As shown in FIG. 16, one block may consist of, for example, 16 consecutive pixels on the same line. An encoder for a one-dimensional block will be described with reference to FIG.

In FIG. 15, 201 indicates an input terminal to which a digital television signal is input in 8-bit parallel.

The input digital television signal is supplied to a subtraction circuit 204 via a delay circuit 203.

202 indicates an input terminal to which a sampling clock synchronized with the input digital television signal is supplied. This sampling clock is supplied to counter 209 and registers 210 and 211 as clock pulses.

The counter 209 is a hexadecimal counter, and a block clock is generated at its output every 16 pixel data. This block clock is supplied to registers 210 and 211 as a pulse for initialization. It is also supplied to latches 215 and 216 as a latch pulse.

Registers 210 and 211 can input and output 8-bit parallel data. One register 2
10 output data is supplied to one input terminal of the selection circuit 212, and output data of the other register 211 is supplied to one input terminal of the selection circuit 213. The other input terminals of these selection circuits 212 and 213 are supplied with an input digital television signal.

The selection circuit 212 is configured as a digital level comparison circuit that selects and outputs the one with the higher level from two pieces of input data. The selection circuit 213 is configured as a digital level comparison circuit that selects and outputs the one with the smaller level of the two input data. The output data of the selection circuit 212 is supplied to one input terminal of the subtraction circuit 214 and also to the input terminal of the register 210. The output data of the selection circuit 213 is supplied to the other input terminal of the subtraction circuit 214 and also to the input terminal of the register 211.

In this embodiment, one block is composed of 16 consecutive pixel data on the same line, as shown in FIG. At the beginning of each block, a block clock from counter 209 is generated and registers 210 and 21
An initial setting of 1 is made. The register 210 is loaded with a code of all "0" bits as an initial value, and the register 211 is loaded with a code of all bits of 1° as an initial value.

The first pixel data of one block is selected by selection circuits 212 and 2.
13 and stored in registers 210 and 211. The next pixel data is compared with the pixel data stored in the registers 210 and 211, and the data with the higher level of both is output from the selection circuit 212, and the data with the lower level of both is output. Data is output from selection circuit 213. Thereafter, the levels are sequentially compared within one block, and the highest level among the 16 pixel data is taken out to the output terminal of the selection circuit 212, and the lowest level among the 16 pixel data is taken out to the output terminal of the selection circuit 212. It is taken out to the output terminal of the selection circuit 213.

The subtraction circuit 214 performs the calculation (maximum level - minimum level), and the dynamic range of the block is detected at the output terminal of the subtraction circuit 214. The dynamic range DR output from the subtraction circuit 214 is stored in the latch 215, and the minimum level M output from the selection circuit 213 is stored in the latch 215.
IN is stored in latch 216. The dynamic range DR stored in the latch 215 is taken out to the output terminal 206 and is also supplied to the encoder block 205. On the other hand, the minimum level MIN stored in latch 216
is taken out to the output terminal 207, and the subtraction circuit 20
4 to the other input terminal.

The subtraction circuit 204 is supplied with pixel data PD whose timing has been adjusted by the delay circuit 203 . Therefore, data DTI from which the minimum level MIN has been removed is generated at the output terminal of the subtraction circuit 204. This data DTI
is supplied to encoder block 205. As described above, the encoder block 205 divides the dynamic range DR into 16 equal level ranges by using a quantization bit number smaller than the original quantization bit number, for example, 4 bits, and determines which level the data DTI after minimum level removal is. Determine whether it belongs to the range. A 4-bit encoded code DT corresponding to the level range thus specified is output to the output terminal 208 of the encoder block 205.

The present invention can be applied to a simplified high-efficiency code decoding device that selects predetermined 4 bits of data DTI after minimum level removal according to the dynamic range of each block. Furthermore, the present invention can also be applied to decoding high-efficiency codes using variable length coding in which the number of quantization bits is varied according to the dynamic range of each block.

〔Effect of the invention〕

According to this invention, even if the dynamic range information is incorrect, the two-dimensional correlation of the television image is used to replace it with, for example, the average value of the dynamic range of the blocks surrounding the block of interest. It has the advantage that no deterioration occurs. Since the pattern information representing a detailed picture is sent as a quantization code for each pixel, problems such as image distortion do not occur due to interpolation. Furthermore, according to the present invention, even if the minimum level is incorrect, it can be replaced with, for example, the average value of the minimum levels of the blocks surrounding the block of interest, using the two-dimensional correlation of the television image.
Block distortion can be prevented from occurring. Since the replacement is performed using the average value, step-like distortion will not occur even if replacement is performed at a location where the brightness is increasing or decreasing.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a route diagram used to explain blocks that are units of encoding processing, and Fig. 3 is used to explain multiple examples of the structure of transmission data. Route map, Figure 4 is a route map used to explain the level distribution of pixel data within one block, Figure 5 is a block diagram of an example of an encoder block, Figure 6 is a route map used to explain the encoder block, and Figure 7 is a route map used to explain the level distribution of pixel data within one block. The figure is a block diagram of another example of the encoder block, Figure 8 is a route diagram for explaining another encoding method of the encoder block, Figure 9 is a block diagram showing the configuration of the receiving side, and Figure 10 is the decoder. Block diagram of
FIG. 11 is a block diagram of an example of a decoder block,
Figure 2 is a block diagram of another example of the decoder block, No. 13.
Fig. 14 is a block diagram of an embodiment of an error correction circuit to which the present invention is applied, Fig. 14 is a route diagram used to explain an embodiment of the invention, and Fig. 15 is a high-efficiency encoding device to which the invention can be applied. FIG. 16 is a block diagram of another example of the high-efficiency encoding device. 1: Digital television signal input terminal, 2゜3=
Ni line extension circuit, 5: Encoder block, 6: Dynamic range DR output terminal, 7: Minimum level MIN output terminal, 8: Encoding code DT output terminal, 10 Ni blocks, 11-15, 21-25, 31- 35: Sample delay circuit, 81: Received data input terminal, 83: Error correction circuit, 84: Error correction circuit, 85: Decoder,
93: Decoder block, 127, 128, 157, 1
58 line delay circuit, 129-134.159-16
4 Niblock delay circuit, 142.1?2: Divider, 14
3,173: Selector.

Claims (1)

[Claims] Addition of at least two pieces of minimum value of a plurality of pixel data included in a predetermined block of a digital television signal, a maximum value of the plurality of pixel data, and dynamic range information of the plurality of pixel data. A high-efficiency code decoding device that transmits a code, and an encoded code that is data obtained by subtracting the minimum value from the plurality of pixel data and that is encoded to a predetermined number of quantization bits. means for extracting the additional code in the block near the block of interest by applying a two-dimensional delay to the additional code; means for generating a predicted additional code for interpolation from the additional code of the block in the vicinity; means for selecting and outputting the predicted additional code in place of the received additional code when the received additional code is in error based on a flag signal indicating whether or not there is an error in the additional code for each block; A high-efficiency code decoding device comprising: