JPH02305281A - Picture information transmission system - Google Patents

Abstract

PURPOSE:To efficiently transmit picture information of high quality by using already transmitted data free from error to generate interpolation data which interpolates data where error occurs as the time of the occurrence of error of data on a transmission line. CONSTITUTION:Each of memories 207a, 207b, and 207c delays input data by one field period, and maximum value data Dmax. minimum value data Dmin, and a division code i,j of one field period before are supplied to respective terminals A of data selectors 208a, 208b, and 208c. If error occurs in transmission data, maximum value data Dmax, minimum value data Dmin, and the division code i,j are supplied from data selectors 208a, 208b, and 208c to a division value inverse converting circuit 211 instead of erroneous data. Consequently, picture data is transmitted without degradation though data having a high degree of redundancy like an error correction code is not added at the time of transmission of picture data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to an image information transmission system, and particularly to an image information transmission system that enables highly efficient encoding.

[Prior Art] Conventionally, as this type of image information transmission system, for example, a high efficiency encoding system for television signals has been known. In this television signal high-efficiency encoding system, a so-called MIN-MAX method is adopted in which the average number of pixels per pixel is reduced due to the need to narrow the transmission band. This MIN-MAX method will be explained below.

Television signals have strong spatiotemporal correlation. When an image is divided into small blocks, each block often has only a small dynamic range due to local correlation. Therefore, by determining the dynamic range of each blower and adaptively encoding it, very efficient compression can be achieved.

Therefore, with specific reference to the drawings regarding this encoding,
I'll explain.

FIG. 3 is a diagram showing a schematic configuration of an image information transmission system as an example of conventional technology. 301 in the figure is an input terminal, which samples raster-scanned analog image signals such as television signals at a predetermined frequency;
Digital image data, digitized into n bits of data per sample, is input. This 2+ gradation digital image data is supplied to the pixel block division circuit 302.

FIG. 4 is a diagram showing how all pixel data for one screen is divided into pixel blocks. Pixel block division circuit 302
, all pixel data for one screen is stored in a memory etc., and as shown in Fig.
Pixel data is read out in units of pixel blocks, each consisting of (l x m ) pixels, with text pixels in the vertical direction (hereinafter referred to as the ■ direction) and m pixels in the vertical direction (hereinafter referred to as the ■ direction). That is, output is performed for each data of each pixel block.

FIG. 5 shows the a configuration of each pixel block. In the figure, Dl,...
~D, , / indicates each pixel data.

The image data output from the pixel block division circuit 302 is sent to the maximum value detection circuit 303. The minimum value detection circuit 304 is input to the timing adjustment circuit 305. As a result, all pixel data in each pixel block (D, , ~D, ,
,? ), the one having the maximum value (D,, X) and the one having the minimum value (D, .) are detected by the detection circuits 303 and 304 and output.

On the other hand, in the timing adjustment circuit 305, the maximum value detection circuit 303 and the minimum value detection circuit 304
mi. All pixel data is delayed by the time necessary to detect the pixel data, and is sent to the pixel data division value conversion circuit 306 in a predetermined order for each pixel block iσ. For example, for each pixel η, Dl, I+D2. I+D
:1. I, "", D-, 1, Dl, 2. "-",
D m, 2+"" + Dl, (eI) + "-
+ Dm, (j'-1) lD+,,l! l"-'
l Dm, l, and so on.

In this way, all pixel data (D4
．． l to D□l), their maximum value (D,, a,) and minimum value (Di, □) are input to the division value conversion circuit 306, and for each pixel data, D□, and Dl,. A bit division code (△1..~△□, l) is obtained by comparing the quantization level with the quantization level divided into two. Here, k is an integer smaller than n, and the state of quantization is shown in FIG. 6(a).

As shown in Figure 6(a), △0,4 is 2 bits
Output as a value symbol. The bit division code obtained in this way is △11. and n-bit Dmay and Dmi
Parallel-to-serial (P-3) converter 30
7, 307', 307'', and the data selector 308 converts the data into serial data as shown in FIG. ni′
As shown in Figure 7 (1)), after a p-bit error correction code is added, first-in first-out (
FIFO) Memory 310 has a constant data transmission rate 1~
A time axis adjustment process is performed so that the signal is then added, and a synchronization signal is added by a synchronization adding circuit 31.1, and the signal is sent from an output terminal 312 to a transmission path (for example, a magnetic recording/reproducing system such as a VTR).

Here, regarding the addition of the synchronization signal, for each pixel block,
This may be performed for each of a plurality of pixel blocks. Note that the operation timing of each of the circuits described above is determined based on a timing signal output from the timing control section 313.

FIG. 8 is a block diagram showing a schematic configuration of a receiving side corresponding to the data transmitting side shown in FIG. 3. In FIG. 8, reference numeral 821 is a terminal to which the transmission data encoded with high efficiency on the transmission side described above is input, and the input transmission data is supplied to a synchronization signal separation circuit 822 and an error correction circuit 823.

The synchronization signal separation circuit 822 separates a synchronization signal from the input transmission data and supplies it to an error correction circuit 823 and a timing control circuit 831.

The error correction circuit 823 includes a synchronization signal separation circuit 8
The data selector 824 separates the error correction code in the transmission data in synchronization with the synchronization signal supplied from the data selector 824, detects data errors occurring on the transmission path according to the error correction code, and corrects the errors. supply to.

Further, the timing controller 1 to roll circuit 831 controls the operation timing of each circuit on the receiving side based on the synchronization signal supplied from the synchronization signal separation circuit 822.

On the other hand, in the data selector 824, n-bit data D lR11X+DIlli11 in the aforementioned transmission data
Then, each pixel data is divided into hit-quantized codes Δi, j, etc. between aX and D□1n. This is a serial-parallel (S-P) converter 825°82
5', it is converted into parallel data. SP converter 8
The maximum value data Dmax and the minimum value data Dmi in each pixel block are converted into parallel data in step 25. are latched by latch circuits 826 and 827, respectively, and the latched maximum value data D. ax and minimum value data D0,.

are output to the divided value inverse conversion circuit 828, respectively. On the other hand, the division code △1 for each pixel data in each pixel block
．． J is the S-P converter 825 in a predetermined order as described above.
' and is supplied to the divided value inverse conversion circuit 828.

FIG. 6 (1)) shows the division code △1. J andori, □, I)
, , representative value data D'i of the original pixel data from n,
, i. As shown in the figure, the representative values are, for example, D□ax;Dmi. is set to the middle of each quantization level divided into 25. The representative value data (D' +,
+~D', , , , ) are output for each pixel block in the above-mentioned order. The scan conversion circuit 829 converts the output data of the divided value inverse conversion circuit 828 into an order corresponding to raster scan, and outputs it to an output terminal 830 as decoded image data.

[Problems to be Solved by the Invention] However, in the above conventional example, in order to correct errors in data that occur on the transmission path, the transmitting side adds an error correction code to the transmitted data, and then The receiving side uses the error correction code to correct errors in the data that occur on the transmission path, and the redundancy of the transmitted data increases by the error correction code, improving transmission efficiency. However, there were some that were not very good.

SUMMARY OF THE INVENTION In view of the above-mentioned points, an object of the present invention is to provide an image information transmission system that can efficiently transmit high-quality image information.

[Means for Solving Problems] The image information signal transmission method of the present invention is a method for transmitting image information in which one screen is composed of a plurality of pixel data, and the image information signal transmission method of the present invention is a method for transmitting image information in which one screen is composed of a plurality of pixel data. is divided into a plurality of pixel blocks for each predetermined number of pixel data, and each block is divided into distribution data representing the distribution of pixel data values within the block, and pixel data representing each pixel data within the block or the distribution data. Position data indicating where the value is located in the distribution of values is sent onto a transmission path, and if an error occurs in the data on the transmission path, the data that has already been transmitted is used to replace the data with the error. It is characterized by forming interpolated data for interpolation.

[Operation] When transmitting image information using the method described above, the transmission path
- Even if the data is erroneous, the erroneous data can be interpolated using previously transmitted data without errors.

[Example] Hereinafter, the present invention will be explained using examples of the present invention.

FIG. 1(a) shows a schematic configuration of a transmission system in an image information transmission system as an embodiment of the present invention.

In FIG. 1(a), the same components as in FIG. 3 are given the same reference numerals, and detailed explanations will be omitted.

In the transmission system shown in FIG. 1(a), unlike the transmission system shown in FIG.
As shown in FIG. 1 ( ] ), it is configured to add q bits and r bits 1 to error detection codes and supply them to the FIFO memory 310 .

With the above-described configuration, the error detection code added in the error detection code addition circuit 10 may have an extremely smaller number of bits than the error correction code in order to detect whether or not an error has occurred in the data. , it is possible to reduce the redundancy of transmitted data.

Further, FIG. 2 shows a schematic configuration of a receiving system in an image information transmission system as an embodiment of the present invention.

In Fig. 2, 201 is a terminal to which the transmission data (see Fig. 1(b)) encoded with high efficiency in the transmission system shown in Fig. 1(a) is input, and the input transmission data is supplied to the data selector 202, error detection circuit 203, and synchronization signal separation circuit 204.

The synchronization signal separation circuit 204 separates a synchronization signal from the input transmission data and supplies it to the error detection circuit 203 and the timing control circuit 205.

The timing control circuit 205 controls the operation timing of each circuit on the receiving side based on the synchronization signal supplied from the synchronization signal separation circuit 204, and the data selector 202 selects n-bit data Dmax in the transmission data. Data D is on the A side of the figure. on the B side in the figure, and each pixel data as DI, , a X r DI
The bit quantized code △, J between I and I is denoted by C in the figure.
These data are distributed to serial-to-parallel (S→P) converters 206a, 206b, and 206c, respectively.
is converted to parallel data.

Maximum value data D□ in each pixel block converted into parallel data by the 1+P converter 206a. is the memory 207a,
The minimum value data Dmin in each pixel block, which is supplied to the B terminal of the data selector 208a and the arithmetic circuit 209a and converted into parallel data by the S+P converter 206b, is supplied to the memory 207b, the B terminal of the data selector 208b, and the arithmetic circuit 209b. The division code Δ1 . .

is the memory 207c, the B terminal of the data selector 208c,
i is supplied to the maximum value latch circuit 210.

By the way, the memories 207a, 207b, and 207c are each for delaying the input data by one field period, and the A terminals of the data selectors 208a, 208b, and 208c are each configured to delay the input data by one field period. Maximum value data D□RM+minimum value data D,. A two-part code ΔI+J is supplied.

Additionally, the maximum value latch circuit 210 is an S→P converter 206C.
This is a circuit that latches the divided data indicating the maximum value of the divided codes Δi and j related to each pixel data in each pixel block outputted from the maximum value latch circuit 210, and the divided data latched in the maximum value latch circuit 210 is transferred to the arithmetic circuit. 209a, 2D9b
supply to. Then, the arithmetic circuit 209a uses the maximum value data D max supplied from the S+P converter 206a and the divided data supplied from the maximum value latch circuit 210 to obtain interpolated minimum value data D5. . ' is calculated and supplied to the C terminal of the data selector 208b, and the arithmetic circuit 209b calculates the minimum value data D supplied from the sp converter 206b.
Interpolated maximum value data Dff1a is obtained using the divided data supplied from the maximum value latch circuit 210.
X' is calculated and supplied to the C terminal of the data selector 208a.

The switching operations of the data selectors 208a, 208b, and 208c are controlled according to the error detection result output from the error detection circuit 203. In other words, if the error detection circuit 203 detects that no data error has occurred in the transmitted data, the data selector 2088
~208c are all connected to the B terminal in the figure, and if only the maximum value data D□9 is incorrect, the data selector 208
a to the C terminal data selector 208b, 2'08c in the figure.
is connected to the B terminal in the figure, and the minimum value data D1. . If only the maximum value data D□ and the minimum value data Dmin are wrong, connect the data selector 208b to the C terminal in the figure, and the data selectors 208a and 208c to the B terminal in the figure. The selectors 208a and 208b are connected to the A terminal in the figure, and the data selector 208c is connected to the B terminal in the figure.If the division codes Δi and j are incorrect, all data selectors 208a to 208c are connected to the A terminal in the figure. Connect to A side.

Through the above operations, the data selector 208a.

If an error occurs in the transmission data, interpolated data will be output from the data selectors 208b and 208c in place of the incorrect data.
Maximum value data D□8° Minimum value data D output from c
□I n + division code △i, j is the division value inverse conversion circuit 21
1, and in the division value inverse conversion circuit 211, division codes Δi, j, and aX, D□, similar to the receiving system shown in FIG. The n-bit representative value data D i,j related to the original pixel data from is decoded and supplied to the scan conversion circuit 212 . Then, the scan conversion circuit 212 converts the output data of the divided value inverse conversion circuit 211 into an order corresponding to raster scan, and outputs it from the output terminal 2]3 as decoded image data.

As explained above, when transmitting image data, it is possible to transmit the image data without deteriorating it without adding highly redundant data such as an error correction code.

Further, as described above, in this embodiment, the maximum value data D m a X and the minimum value data D, . . . in the transmission data.

Alternatively, if the division code i or j is incorrect, the memory 207a, 2[17b, 2117
The transmission data one field period before, which is stored in c, is supplied as interpolation data to the divided value conversion circuit 211, or the transmission data stored in c is not limited to this, but one field period before the transmission data in which the error occurred. If the interpolation data is calculated using the transmission data corresponding to the transmission data of the previous field period and the transmission data corresponding to the pixel blocks surrounding the pixel block representing the transmission data of one field period before, the deterioration of the image data can be further reduced. It becomes like you can do something.

[Effects of the Invention] As explained above, according to the present invention, it is possible to provide an image information transmission system that efficiently transmits high-quality image information.

[Brief explanation of the drawing]

FIG. 1(a) is a schematic configuration diagram of a transmission system of an image information transmission system as an embodiment of the present invention, and FIG. 1(b) is a transmission output from the transmission system shown in FIG. 1(a). A diagram showing a data string; FIG. 2 is a schematic configuration diagram of a receiving system of an image information transmission system as an embodiment of the present invention; FIG. 3 is a schematic configuration diagram of a transmitting side of an image information transmission system according to the prior art; Figure 4 is a diagram showing how all image data is divided into pixel block groups, Figure 5 is a diagram showing the data arrangement of each pixel block, and Figure 6 (a) is the conversion of the division value conversion section in Figure 3. FIG. 6(b) is a diagram showing the conversion characteristics of the divided value inverse converter in FIG. 8. FIG. 7(a) is a diagram showing the data string output from the data selector 308 in FIG. Figure 7(b) is a diagram showing the transmission data string output from the transmission system shown in Figure 3, and Figure 8 corresponds to the transmission side of the image information transmission system shown in Figure 3. FIG. 2 is a diagram showing a schematic configuration of a receiving side. 101...Error detection code addition circuit 203--Error detection circuit 207a to 207C...Memory 208a to 208cm data selector 209a, 209b---Arithmetic circuit 2]0...Maximum value latch circuit 211... Division value conversion circuit

Claims (1)

[Scope of Claims] A method of transmitting image information in which one screen is composed of a plurality of pixel data, wherein the one screen of the plurality of pixel data is divided into a plurality of pixel blocks for each predetermined number of pixel data. distribution data representing the distribution of pixel data values within each block, and position data representing where each pixel data within the block is located in the distribution of pixel data values represented by the distribution data. is transmitted onto a transmission path, and if an error occurs in the data on the transmission path, the already transmitted data is used to form interpolation data for interpolating the data in which the error has occurred. Image information transmission method.