JP3040728B2 - Image processing apparatus and image processing method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and an image processing method, and more particularly to an image processing apparatus and an image processing method capable of high-efficiency encoding. [0002] Hitherto, for example, a high-efficiency encoding method for television signals has been known as a processing method in this type of image processing apparatus. In this television signal high-efficiency encoding method, a so-called MIN-MAX method for reducing the average number of bits per pixel is employed because of the necessity of narrowing the transmission band. Hereinafter, the MIN-MAX method will be described. [0003] Television signals have strong spatiotemporal correlations. When an image is divided into small blocks, each block often has only a small dynamic range due to local correlation. Therefore, very efficient compression can be performed by obtaining a dynamic range in each block and adaptively encoding. Therefore, this encoding will be described specifically with reference to the drawings. FIG. 3 is a diagram showing a schematic configuration of an image information transmission system as an example of the prior art. Reference numeral 301 in the figure denotes an input terminal, which inputs a raster-scanned analog image signal such as a television signal at a predetermined frequency, and inputs digital image data digitized to n bits per sample. . The ^2n- gradation digital image data is supplied to the pixel block dividing circuit 302.
Supplied to FIG. 4 is a diagram showing how all pixel data for one screen is divided into pixel blocks. In the pixel block dividing circuit 302, all pixel data for one screen is once stored in a memory or the like, and as shown in FIG. 4, r pixels are arranged in a horizontal direction (hereinafter, referred to as H direction), and a vertical direction (hereinafter, referred to as V (Referred to as a direction), pixel data is read out in pixel block units composed of (r × s) pixels of s pixels. That is, the output is performed for each data of each pixel block. FIG. 5 shows the configuration of each pixel block. In the figure, D _{1,1 to} D _{s, r} indicate each pixel data. The image data output from the pixel block dividing circuit 302 includes a maximum value detection unit 303, a minimum value detection unit 304, and a timing adjustment unit.
305 is entered. As a result, of all pixel data (D _{1,1 to} D _{s, r} ) in each pixel block, the one having the maximum value (D
_max ) and the minimum value (D _min ) are detected by the detection units 303 and 304 and output. On the other hand, in the timing adjustment unit 305, all pixel data is delayed by a time necessary for the maximum value detection unit 303 and the minimum value detection unit 304 to detect D _max and D _min , and for each pixel block. The pixel data is sent to the division value conversion unit 306 in a predetermined order. For example, D _1,1 , D _2,1 , D _3,1 ,…, D _{s, 1} , D _1,2 ,…,
Ds _{, 2} , ..., D1 _{, (r-1)} , ..., Ds _{, (r-1)} , D1 _{, r} ..., Ds _{, r} . In this way, all pixel data (D _{1,1 to} D _{s, r} ) in each pixel block and their maximum value (D _max )
And the minimum value (D _min ) are input to the division value conversion unit 306, and for each pixel data, a k-bit division code (Δ _{1, 1)} is compared with a quantization level ^{obtained by} dividing 2 ^k between D _max and D _{min . 1 to} Δ
_{s, r} ). Here, k is an integer smaller than n, and the state of quantization is shown in FIG. As shown in FIG. 6A, Δ _{i, j} is k
It is output as a binary code of bits. The k-bit division code Δi _{, j} and the n-bit D _max and D thus obtained are obtained.
_min is the parallel-serial (PS) converter 307, 30
The data is converted into serial data at 7 ′, 307 ″, and the data selector 3
At 08, the serial data is as shown in FIG. FIG. 7 shows transmission data for one pixel block. The data output from the data selector 308 is processed on a time axis in a first-in first-out memory (FIFO memory) 309 so as to have a constant data transmission rate, and a synchronization signal is added by a synchronization adding section 310. Then, the signal is transmitted from an output terminal 311 to a transmission path (for example, a magnetic recording and reproducing system such as a VTR). Here, the addition of the synchronization signal may be performed for each pixel block or for each of a plurality of pixel blocks. The operation timing of each unit described above is determined based on a timing signal output from the timing control unit 312. FIG. 8 is a block diagram showing a schematic configuration of a receiving side corresponding to the data transmitting side shown in FIG. In FIG. 8, reference numeral 821 denotes a terminal to which the above-described transmission data which has been encoded at high efficiency at the transmission side is input. The synchronization signal in the input transmission data is separated by the synchronization separation unit 822 and supplied to the timing control unit 823. The timing control unit determines the operation timing of each unit on the receiving side based on the synchronization signal. On the other hand, in the data selector 824, n-bit data D _max and D _min in the above-mentioned transmission data and a code Δ _{i, j} obtained by quantizing each pixel data by k bits between D _max and D _min
And sorted out. These are converted into parallel data by serial-parallel (SP) converters 825 and 825 ', respectively. The maximum value data D _max and the minimum value data D _{min in} each pixel block converted into parallel data by the SP converter 825.
Are latched by latch circuits 826 and 827, respectively, and the latched maximum value data D _max and minimum value data D _min are output to the divided value inverse conversion unit 828, respectively. On the other hand, the division code Δ _{i, j} relating to each pixel data in each pixel block is output by the SP converter 825 ′ in a predetermined order as described above, and is supplied to the division value inverse conversion section 828. FIG. 6B shows the division codes Δ _{i, j} and D _max , D
FIG. 6 is a diagram showing a state in which representative value data D ′ _{i, j} relating to original pixel data is decoded from _min, as shown in FIG.
_max and D _min are set in the middle of each of the ^2k- divided quantization levels. The n-bit representative value data (D ′ _{1,1 to} D ′ _{s, r} ) obtained by the division value inverse conversion unit 828 in this manner is output for each pixel block in the order described above. In the scan converter 829, the output data of the split value inverse converter 828 is converted into an order corresponding to the raster scan and output to the output terminal 830 as decoded image data. However, in the above-mentioned conventional example, the correlation of only the two-dimensional space of the image is used. Therefore, when transmitting a still image or an image with little motion, the transmission information has redundancy on the time axis, and the same information is repeatedly transmitted, which has a disadvantage of deteriorating the transmission efficiency. Accordingly, an object of the present invention is to provide
An object of the present invention is to provide an image processing apparatus and an image processing method capable of efficiently transmitting high-quality image information. In order to achieve the above object, an image processing apparatus according to the present invention comprises: input means for inputting an image signal; and detecting means for detecting a movement of the image signal. A first encoding mode in which an image signal input by the input unit is quantized and encoded in units of blocks constituted by a single-screen image signal, and a plurality of image signals input by the input unit are displayed on a plurality of screens. The second method is to quantize and encode in block units constituted by the image signals of
Encoding means for selecting the encoding mode in accordance with the output of the detection means and encoding the image signal, and serially converting the block data encoded by the encoding means. Conversion means for converting to data;
Control means for changing the conversion order of the conversion means according to the output of the detection means. In the image processing method according to the present invention, an image signal is input, motion of the image signal is detected, and the input image signal is quantized and encoded in a block unit constituted by a single-screen image signal. A first encoding mode for encoding, and a second encoding mode for quantizing and encoding the input image signal in units of blocks constituted by image signals of a plurality of screens. The encoding mode is selected to encode the image signal, the encoded block data is converted into serial data, and the conversion order is changed according to the detection result. Hereinafter, an example of an embodiment of the present invention will be described in detail. FIG. 1 and FIG. 2 are diagrams showing a schematic configuration of an image information transmission system according to an embodiment of the present invention. Here, FIG. 1 shows a configuration on the transmission side, and FIG. 2 shows a configuration on the reception side. In FIG. 1, reference numeral 101 denotes an input terminal, 102 denotes a pixel block dividing circuit, and 103 denotes a pixel block dividing circuit.
A frame memory for delaying the output of the pixel block by one frame;
Subtracter 105 for calculating the difference between the outputs of the pixels; 105, a motion detector for performing motion detection based on the result of the subtractor 104; , 107 is a switch for selecting the output of the average value calculation circuit 106 and the output of the frame memory 103, 108 is a maximum value detector for finding the maximum value of the input value from the switch 107, 109 is a minimum value detector, 110 Is a delay circuit for delaying the input of the switch 107, 111 is a divided value converter for converting a signal from the delay circuit 110 based on data from the maximum value detector 108 and the minimum value detector 109, and 100 is a motion detector A switch for selecting and outputting the output of the maximum value detector 108 and the output of the minimum value detector 109 based on the information of 105, a switch 112 for selecting an output signal, and a memory 113 for storing data from the motion detector 105 Frame memory, 11
4 is a timing controller that controls the timing of each circuit in this system, and 115 is a parallel-serial that converts parallel data from the switch 112 into serial data.
A (PS) converter, 116 is a first-in first-out memory (FIFO memory), 117 is a synchronization adding circuit that adds a synchronization signal to an input signal from the FIFO memory 116, and 118 is an output terminal. In the receiving side block diagram shown in FIG.
0 is a receiving system input terminal, 121 is a serial / parallel (SP) converter that performs serial / parallel conversion, 122 is a synchronization separation circuit that separates a synchronization signal from an input signal, and 123 is based on the input from the synchronization separation circuit 122. A timing controller for controlling the timing of each circuit; 124, a maximum / minimum position detector for detecting motion information from data from the SP converter 121; 125, a frame memory for storing output signals of the maximum / minimum position detector 124; 126 is the maximum value detector for finding the maximum value from the input from the SP converter 121, 127 is the minimum value detector, and 128 is based on the data from the above detectors 126 and 127.
A split value inverse converter for inversely converting the signal from the SP converter 121, an address generator 129 for generating an address of the frame memory 130 based on an output of the frame memory 125, and an output terminal 131. Hereinafter, the operation of each of the above blocks will be described step by step. In the transmitting side block shown in FIG. 1, an input terminal 101 samples a raster-scanned analog image signal such as a television signal at a predetermined frequency, and converts the digitized t-bit digital image data into t-bit digital image data. Is entered. The digital image data of ^2t gradation is supplied to the pixel block dividing circuit 102, and is divided into (r × s) pixel blocks of r pixels in the horizontal direction and s pixels in the vertical direction. . That is, output is performed for each data of each pixel block. The image data output from the pixel block division circuit 102 is input to a frame memory 103, a subtractor 104, and an average value calculation circuit 106. The frame memory 103 delays the data by one frame and outputs the data to the subtractor 104 and the average value calculation circuit 106. The subtractor 104 obtains the difference between the data of the previous frame and the data of the current frame to obtain the correlation in the time axis space, and the motion detector 105 outputs the motion information. The motion detector 105 compares the inter-frame difference value with a set threshold value and outputs 1-bit motion information. Based on the obtained motion information, it is determined which of the previously obtained average value between two frames (output of 106) and original data delayed by one frame (output of 103) is to be encoded and transmitted. This operation is performed by the switch 107. Based on this motion information, encoded transmission information as shown in FIG. 9 is output. For motion blocks,
The output of the frame memory is encoded by the MIN-MAX method, and the information of each frame is transmitted. For stationary blocks,
The difference between the original data and the data one frame before, that is, the frame memory output Is encoded by the MIN-MAX method, and information for one frame is transmitted every two frames. More specifically, a case where a motion block is determined will be described first. The output of the frame memory 103 is
The signals are input to a maximum value detector 108, a minimum value detector 109, and a delay circuit 110 via a switch 107. As a result, the maximum value among all pixel data (D _{1,1 to} D _{s, r} ) in each pixel block is obtained.
(D _max ) and the minimum value (D _min ) are detected by the maximum value detector 108 and the minimum value detector 109 and output to the switch 100. The switch 100 is a switch that selects and outputs the output of the maximum value detector 108 and the output of the minimum value detector 109 based on the information of the motion detector 105. When it is determined that the image is a "movement" image, the output _Dmax of the maximum value detector 108 is output to the terminal 2a of the switch 112, and the output of the minimum value detector 109 is output to the terminal 2b. When it is determined that the image is a “still” image,
D _max is switched to terminal 2b and D _min is switched to terminal 2a for output. On the other hand, in the delay circuit 110, all pixel data is delayed by the processing time of the maximum value detector 108 and the minimum value detector 109, and the pixel data is divided in a predetermined order for each pixel block. Send to 111. For example, for each pixel block, D _1,1 , D _2,1 , D _3,1 ,..., D _{s, 1} , D _1,2 ,.
_{1, (r-1)} , ..., Ds _{, (r-1)} , D1 _{, r} , ..., Ds _{, r} . In this way, all pixel data (D _{1,1 to} D _{s, r} ) in each pixel block and their maximum value (D _max ) and minimum value (D _min ) are input to the division value converter 111. and, D _max and D _min division code (Δ _1,1 ~Δ _{s, r)} of k bits by comparing the 2 ^k division quantization level and the pixel data between the obtained. Here, k is an integer smaller than t. The k-bit division code and the t-bit D _max and D _min thus obtained are supplied to the switch 112. The switch 112 is a switch for selecting data in accordance with the transmission order of transmission data. The operation of these switching devices 100 and 112, for the motion block _{D max, D min, Δ 1,1} , ..., the order of the delta _{s, r,} a still block _{D min, D max, Δ 1,1} , ..., The data transmission order can be set to the order of Δs _{, r} . That is, D _max , D _min
Are changed according to the motion information and output. The data sequentially switched and output by the switch 112 is output to the parallel / serial converter 115.
Is converted into serial data. The data output from the switch 112 is processed on a time axis in a first-in first-out memory (FIFO memory) 116 so as to have a constant data transmission rate, and a synchronization signal is added by a synchronization addition circuit 117. The output signal is sent from an output terminal 118 to a transmission line (for example, a magnetic recording / reproducing system such as a VTR). Here, the addition of the synchronization signal may be performed for each pixel block or for each of a plurality of pixel blocks. The operation timings of the above-described units are determined based on a timing signal output from the timing controller 114. Next, a case where the block is determined to be a still block will be described. In the frame A shown in FIG. 9, the output of the average value calculation circuit 106 is subjected to the same signal processing as described below via the switch 107 and output. At the same time, the motion information from the motion detector 105 is recorded in the frame memory 113. The frame memory 113 stores one pixel for each pixel block.
What is necessary is just to comprise by the data capacity of bits. That is, (r ×
A capacity of s × 1) bits is sufficient. In the frame B shown in FIG. 9, the image data is not transmitted, and the compression ratio is increased. Whether the image data is transmitted in the B frame is determined by the frame memory 113.
Since the motion information for each block determined in the previous frame (A frame) is stored, the control is performed based on this information. FIG. 2 is a schematic configuration diagram of the receiving side. In the figure, reference numeral 120 denotes an input terminal for inputting the above-mentioned signal from the transmission side, and the transmitted data is converted to a serial / parallel converter.
121, are input to the sync separation circuit 122. Sync separation circuit 122
Then, the synchronization signal in the input transmission data is detected and separated, and supplied to the timing controller 123. The timing controller 123 determines the operation timing of each unit on the receiving side based on the synchronization signal. On the other hand, the serial / parallel converter 121 converts the serial input data into parallel data, and converts the data into a maximum / minimum position detector 124, a maximum value detector 126, a minimum value detector 127, and a divided value inverse converter 128. Supply. The maximum / minimum position detector 124 determines the order of D _max and D _min for each block of the transmitted information and, based on the result, determines whether the block is a motion block or a still block. Get motion information. The motion information data for each pixel block obtained by the maximum / minimum position detector 124 is stored in a frame memory 125.
Is stored. Since the above data is sent from the transmitting side only when transmitting the A frame shown in FIG. 9, it is used when receiving and reproducing the B frame. The divided value inverse converter 128 obtains D _max , D
_min from D _max, between D _min and 2 ^k divided, pixel data delta _{1, 1} from the SP converter 121, ..., and converts the delta _{s, r} to the division value outputs. In the frame memory 130, the divided value inverse converter 12
8 is stored, converted into an order corresponding to the raster scan by the control signal of the address generator 129, and output to the output terminal 131 as decoded image data. At this time, in the frame memory 130, data is written for all pixels in the case of the A frame in FIG. 9, but only pixels of the motion block are written in the case of the B frame. The address generator 129 has a frame memory
A write address is generated based on the information of the 125 motion blocks, an address is generated at the time of reading so as to have a pixel order corresponding to the raster scan as described above, and the data stored in the frame memory 130 is decoded. The data is output from the output terminal 131 as data. In the above embodiment, the motion information is described as the additional information. However, the present invention is not limited to this, and it goes without saying that other information may be used. As described above, according to the present invention, there is provided an image processing apparatus and an image processing method capable of efficiently transmitting high-quality image information by removing the redundancy in the time direction of the image information. Obtainable.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic configuration diagram of a transmitting side according to an example of an embodiment of the present invention. FIG. 2 is a schematic configuration diagram of a receiving side according to an example of an embodiment of the present invention. FIG. 3 is a schematic configuration diagram of a transmission side of an image information transmission system according to the related art. FIG. 4 is a diagram showing how all image data is divided into pixel block groups. FIG. 5 is a diagram showing a data arrangement of each pixel block. 6 is a diagram illustrating conversion characteristics of a division value conversion unit in FIG. 3 and conversion characteristics of a division value inverse conversion unit in FIG. 8; FIG. 7 is a diagram for explaining data to be transmitted. 8 is a diagram illustrating a schematic configuration of a receiving side corresponding to a transmitting side of the image information transmission system illustrated in FIG. 3; FIG. 9 is a diagram for explaining the operation of FIGS. 1 and 2; [Description of Signs] 102 Pixel block dividing circuit 103 Frame memory 104 Subtractor 105 Motion detector 106 Average value calculating circuit 100, 112, 107 Switching unit 108, 126 Maximum value detector 109, 127 Minimum value detector 110 Delay circuit 111 Division value converter 114, 123 Timing controller 115 Parallel / serial converter 121 Serial / parallel converter, 124 Maximum / minimum position detector 128 Divided value inverse converter 129 Address generator 130 Frame memory

Claims (1)

(57) [Claims] Input means for inputting an image signal, detecting means for detecting the movement of the image signal, and quantizing and encoding the image signal input by the input means in units of blocks each composed of a single-screen image signal. A first encoding mode; and a second encoding mode in which the image signal input by the input unit is quantized and encoded in units of blocks composed of image signals of a plurality of screens, and the detection unit According to the output of the
Encoding means for selecting an encoding mode to encode the image signal; converting means for converting block data encoded by the encoding means into serial data; and performing the conversion in accordance with an output of the detecting means. Change the order of the means
An image processing apparatus comprising: control means for changing . 2. An image signal is input, the motion of the image signal is detected, and the input image signal is converted to a single-screen image signal.
A first method of quantizing and coding in units of the constructed block
Encoding mode, and the input image signal
Quantize in block units composed of image signals
And a second encoding mode for encoding, wherein the detection result
The encoding mode is selected according to the
And converts the encoded block data into serial data.
And changing the conversion order according to the detection result.
Image processing method