JPS63256080A - Decoder for block coding - Google Patents

Abstract

PURPOSE:To improve the picture quality of a decoded picture by using a decoded data with very strong correlation if an additional code is an error data so as to decode the additional code thereby decoding the additional information very close to a correct data. CONSTITUTION:A received data is fed to an input terminal 6 and a frame decomposition circuit 7 detects an error and decodes a correction code. An additional code and a code signal from the frame decomposition circuit 7 are fed to an ADRC (coding suitable for dynamic range) decoding circuit 8. In case of the desision that the additional code has an error not to be corrected by the error detection and the error correction code as the result of decoding, surrounding picture elements in a noticed block (a block to be decoded) and decoded data adjacent to the surrounding picture elements are used and the additional code is obtained by the method of least squares. That is, the additional code is identified by utilizing the relation that the surrounding picture element of the noticed block and the said decoded picture element having a minimum distance to the surrounding picture elements have a very strong correlation. The block code such as ADRC is decoded by using the obtained additional code.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a block encoding decoding device that can compress and transmit original image data by utilizing two-dimensional correlation of images.

[Summary of the invention]

In this invention, a digital image signal is converted into a signal having a block structure, a code signal is formed by encoding each block, and a parameter representing each block is transmitted as an additional code together with the code signal. If the additional code is incorrect in the decoding device,
By using the least squares method, an additional code with a value as close as possible to the correct data is calculated using pixels that are included in the decoded block located in the periphery and are adjacent to the block with an incorrect additional code, and surrounding pixels within the block. This additional code is used to obtain the restored data.

[Conventional technology]

One feature of image information is that it has two-dimensional correlation. As one type of encoding that utilizes this two-dimensional correlation, a block encoding method is known in which an image is divided into a large number of two-dimensional blocks and each block is encoded.

- As an example, the applicant of this application has filed Japanese Patent Application No. 59-266407.
A high-efficiency encoding device that obtains a dynamic range defined by the maximum and minimum values of a plurality of pixels included in a two-dimensional block and performs encoding adapted to this dynamic range, as described in the specification. is proposed. Furthermore, as described in Japanese Patent Application No. 60-232789, a high-efficiency encoding device performs encoding adapted to a dynamic range with respect to a three-dimensional block formed from pixels in areas included in each of a plurality of frames. is proposed.

Furthermore, as described in Japanese Patent Application No. 60-268817, there is a variable length encoding method in which the number of bits changes depending on the dynamic range so that the maximum distortion caused when quantization is constant. Proposed.

Encoding adapted to the dynamic range described above (A D
RC) is the dynamic range of each block,
Two data of the maximum value and the minimum value are used as an additional code, and a code signal whose number of bits per pixel is reduced compared to the original number of bits and the above-mentioned additional code are transmitted.

Further, as another example of a block encoding method, there is a method in which the average value Av and standard deviation σ are transmitted for each block. Each pixel in a block is encoded as a 1-bit "0" or "1'" depending on whether it is larger or smaller than the average value Av. For example, data with a level higher than the average value AV is
The average value Av and the standard deviation σ are parameters representing the block, and are transmitted as an additional code. On the receiving side, data of "1" is decoded to the level of (Av+σ), and data of '0' is decoded to the level of (Av-σ).

In block encoding, if the additional code, which is a parameter representing the block, is incorrect during the transmission process, the decoding side will
Since the additional code is an error, decoding is impossible.
0 where all pixel data of l block is error data
For example, as shown in Japanese Unexamined Patent Application Publication No. 147690/1982, the applicant of the present application has proposed that for a block whose additional code is error data, the average value of the additional codes of 8 blocks surrounding the block is used in place of the erroneous additional code. Suggests a repair method.

[Problem that the invention seeks to solve]

Even if concealment is performed as described above, the surrounding blocks used for correction and the block of interest are far apart, so there is little correlation (there was a problem that distortion in each block could not be sufficiently removed). .

Therefore, an object of the present invention is to obtain a block code that is very close to the correct additional code when the additional code, which is a parameter representing a block, is incorrect, and uses this data to enable decoding of each pixel data in the block. The purpose of the present invention is to provide a decoding device for decoding.

[Means for solving problems]

In this invention, a digital image signal is converted into a signal having a block structure, a code signal is formed by encoding each block, and a parameter representing each block is transmitted as an additional code together with the code signal. The decoding device attempts to decode using the least squares method using surrounding pixels in the block to be decoded whose additional code is incorrect and pixels included in the decoded block and adjacent to the block to be decoded. A circuit for obtaining an additional code of a block and a circuit for obtaining restored data from the additional code and the code signal are provided.

[Effect]

When an additional code such as a dynamic range in ADRC is determined to have an uncorrectable error by an error detection and error correction code, the surrounding pixels in the block of interest (the block to be restored) and the restored pixels adjacent to this surrounding pixel are Using the obtained data, the additional code is determined by the least squares method. That is, the additional code is identified by utilizing the fact that there is a very strong correlation between the pixels surrounding the block of interest and the restored pixel whose distance to the surrounding pixel is the minimum. The obtained additional code is used to decode a block code such as ADRC.

〔Example〕

An embodiment of the present invention will be described below.

In this embodiment, for example, one frame of the digital video signal is divided into n parts in the vertical direction and divided into plants in the horizontal direction, as shown in FIG.
(13...Bnm) blocks are formed.

As shown in FIG. 2, this one block includes 64 pixels (8 lines x 8 pixels). The number of quantization bits for one pixel is 8 pits. AD RC (Adaptive Dynaa+icr) is one of the high efficiency codes.
-ange Coding) is based on the maximum value MAX and minimum value MI of the levels of 64 pixels within one block.
N, respectively, find the dynamic range DR by (MAX'-M A 4-bit code signal is formed depending on whether the data is included in the data or not. The data to be transmitted is the maximum (tWMAX) per block.
, the minimum value MIN and two additional codes in the dynamic range DR, each being a 4-bit code signal for each pixel.

These additional codes and code signals are encoded with error detection and correction codes to detect and correct errors that occur during transmission. Error detection and correction codes are added separately to the additional code and code signal.

FIG. 5 shows a transmitting system using ADRC,
In FIG. 5, a digital video signal is supplied to an input terminal indicated by 1. This digital video signal is a signal in the scanning order, and is converted into the block order in the blocking circuit 2. In the example shown in FIG.
Bll-B12-B13-...-Bnm). The output signal of this blocking circuit 2 is supplied to the ADRC encoding circuit 3, and as mentioned above,
ADRC encoding is performed block by block.

Additional code (dynamic range DR and minimum value MIN) obtained by ADRC encoding circuit 3 and code signal D
T is supplied to the framing circuit 4. In this framing circuit 4, ADR is applied to data having a frame structure.
The output data of the C encoding circuit 3 is converted and also encoded with an error detection and correction code, and transmission data is obtained at the output terminal 5.

The receiving system corresponding to the transmitting system has the configuration shown in FIG. In FIG. 6, received data is supplied to an input terminal 6, and a frame decomposition circuit 7 performs error detection and correction code decoding. The additional code and code signal from the frame decomposition circuit 7 are ADR
The digital video signal is supplied to the ADRC decoding circuit 8, and a restored digital video signal is obtained from the ADRC decoding circuit 8. ADRC
The restored data from the decoding circuit 8 is supplied to a block decomposition circuit 9, which restores the order of the blocks to the television scanning order. The output data of block decomposition circuit 9 is supplied to error correction circuit IO. In the error correction circuit IO, erroneous pixel data that cannot be corrected in the frame decomposition circuit 7 is interpolated with surrounding correct pixel data. If the additional data is incorrect, the ADR
In the C decoding circuit 8, the additional data is modified. Restored data is obtained at the output terminal 11 of the error correction circuit 10.

FIG. 1 shows an embodiment of the present invention. In FIG. 1, a code signal DT is supplied to an input terminal indicated by 21;
The dynamic range DR is supplied to the input terminal indicated by 2, the minimum value MIN is supplied to the input terminal indicated by 23, and the minimum value MIN is supplied to the input terminal indicated by 24.
An error flag indicating the presence or absence of an error in the additional data DR, MIN is supplied to the input terminal indicated by . The dynamic range DR is supplied to the ROM 25 as an address signal, and the R
OM25 generates -Δ during minimum quantization. Code signal DT, minimum quantization width △ and minimum value MIN are in delay circuit 2
6. Code signal DT from delay circuit 26 is supplied to one input terminal of multiplier circuit 27 . The minimum quantization width from the delay circuit 26 is supplied to the selection circuit 28,
The output signal of the selection circuit 28 is supplied to the multiplication circuit 27.

The output of the multiplication circuit 27 is the product of the minimum quantization width and the code signal, that is, restored data after the minimum value has been removed.

The output signal of the multiplier circuit 27 is supplied to one input terminal of the adder circuit 30. The other input terminal of the adder circuit 30 has
The minimum value passed through the 0 selection circuit 29 to which the output signal of the selection circuit 29 is supplied is supplied to the addition circuit 30.
The restored data is taken out to the output terminal 31 of 0.

The selection circuit 28 selects the minimum quantization width Δ from the delay circuit 26 if the received dynamic range DR is correct, and if the received dynamic range DR is error data, it is shown surrounded by a broken line. Additional information restoration unit 41
The 0 selection circuit 29 that selects the minimum quantization width Δ′ from
If the received minimum (aMIN) is correct, select the minimum value MIN from the delay circuit 26 and set the received minimum value M
If IN is error data, the minimum value MIN' from the additional information restoring section 41, which is shown surrounded by a broken line, is selected. These selection circuits 28 and 29 are controlled by error flags from input terminals.

The additional information restoration unit 41 restores the restored data yl', y2', . . . y8' indicated by black dots in FIG.
and the code signal x1 of the block whose additional code is incorrect,
Using the known values of x2, . . . In this embodiment, the data on the bottom line in the upper decoded block is used as the data y1" to y8', and the code signal x l - x 3 is used as the data y1" to y8', and as the code signal x l -x 3, the additional code is included in the erroneous block. , data y1'~
The pixel adjacent to y8' is used. Restored data yl'
Since the distance between ~ya' and the code signals x1 to x8 is extremely close, there is a strong correlation between them, and therefore even if it is estimated that both have common additional information, the error is small. .

The additional code of the block to be decoded is (Δ=a)(
MIN-b), the following equation holds true.

yl = xl ・a+b+el y2'=x2・a+b+e2 )'8'=X8・a+b+e8 However, e　−e　F3 is an error.

According to the least squares method, the error (e1 to e8
) can be found to minimize the sum of squares of a and b. In the following equation, Σ means integration of eight pieces of data. For example, (Σy) is (yl'+y2'0...
・y8゛). Also, (x), (x2), (y
), (xy) mean the average values of x, x", y', xy, respectively (x" ) - (x)" Σxy ΣX Σy Σx! (Σx)! b" ()l) - (x ) a error-(Σy-ΣxXa)...■ The additional information restoration unit 41 is configured to execute these calculations. The restored data (y1' to y8') is
The additional information is provided from the memory 40 to the additional information restoring section 41 . The restored data obtained at the output terminal 31 is input to the memory 40 .

The memory 40 is supplied with an address signal and an R/W signal from a memory control circuit (not shown).

The memory 40 has a capacity that can store at least m547 worth of restored data, where m is the number of blocks in the horizontal direction.

The multiplication circuit 42 receives the code signal DT (
xl~x8) and the restored data (yl''~y8') x
form y. The integrating circuit 43 forms Σy, the integrating circuit 44 forms Σxy, and the integrating circuit 45 forms ΣX. The output signal of the integrating circuit 44 is supplied to the 8x circuit 46, the output signal of the 8x circuit 46 is supplied to the subtracting circuit 47, the output signals of the integrating circuits 43 and 45 are supplied to the 0 multiplying circuit 48, The output signal is supplied to the subtraction circuit 47. The numerator term of the equation (2) is obtained from the output of the subtraction circuit 47.

The term ΣX2 is calculated by the 2-east circuit 49 and the sum-of-products circuit 50, and the output signal of the sum-of-products circuit 50 is supplied to the subtraction circuit 52 via the 8x circuit 51.

The subtraction circuit 52 is supplied with (ΣX)2 from the 2-east circuit 53, and therefore, the denominator term of the equation (2) is obtained from the subtraction circuit 52. The respective output signals of the subtraction circuit 47 and the subtraction circuit 52 are supplied to the division circuit 53. This division circuit 53
From this, the value of a expressed by the formula (2), that is, the minimum quantization width Δ' restored by the least squares method is obtained.

The output signal of the division circuit 53 and the output signal of the integration circuit 45 are supplied to the multiplication circuit 54 , and the output signal of this multiplication circuit 54 is supplied to the subtraction circuit 55 .

The output signal of the integration circuit 43 is supplied to the subtraction circuit 55 , and the output signal of the subtraction circuit 55 is supplied to the (1/8) multiplication circuit 56 . The value of b expressed by the equation 0, that is, the minimum (aMIN') restored by the least squares method is obtained as the output of the (1/8) multiplication circuit 56. The minimum formed in the additional information restoration section 41 The quantization width Δ' and the minimum value MIN' are supplied to selection circuits 28 and 29, respectively.

FIG. 4 is a timing chart showing the operation of the additional information restoring unit 41, in which FIG. 4A shows the received code from the input terminal 21. code signals), the second line
...It is manually operated in the order of the 8th line. The first line contains data for eight pixels of code signals x1 to x8 used for restoring the additional code.

FIG. 4B shows the operation mode of the memory 40, in which reconstructed data of adjacent lines of the upper block is sent from the memory 40 in synchronization with data for 8 pixels of the first line of the received code signal. yl' to y8' are read 0 For example, if the Nth block is 822, block B
The restored data of the eighth line of twelve is read from the memory 40. Using these code signals x1 to x8 and restored data yl" to y8', the additional information restoring unit 41 calculates the minimum quantization width Δ' and the minimum value MIN', as described above.
(Figure 4C) is restored.

Time delay circuit 2 required for the additional information restoration unit 41 to perform the restoration operation
6, the received code is delayed and the minimum quantization width Δ' and the minimum value MIN' are restored before the timing when the code signal of the Nth block is supplied to the multiplication circuit 27, as shown in the fourth diagram. be done. In this restored data,
The eighth line of each block is written to memory 40 as shown in FIG. 4E. The restored data written in this memory 40 is used to restore the additional information of the block in the next row.

Note that the block Bll located at the top of one frame,
Regarding B12, --...Blm, the restored data of the 8th line of the block located at the bottom of the previous frame is used to restore the additional information. In addition, in order to restore the additional information, as described above, [the first
In addition to using the code signal of the 8th line of the upper block and the reconstructed data of the 8th line of the upper block, the decoding order
Depending on the memory capacity, etc., it is possible to use the following combinations of data.

[Code signal of the 8th line of the block of interest and restored data of the 1st line of the block below] [Code signal of the 1st sampling position of the block of interest and 8th sampling position of the left block ] [Restored data of the code signal at the 8th sampling position of the block of interest and the 1st sampling position of the block on the right] Furthermore, instead of using the above combinations alone, two, three, or all of the above combinations are used. You can do it like this.

The present invention is applicable not only to ADRC that converts pixel data into fixed length data for each two-dimensional block, but also to variable length ADRC that converts pixel data to variable length data. It can also be used for coding other than ADRC, such as block coding, in which the average value and standard deviation representing the block are used as additional codes, and each pixel in the block is coded into a 1-bit code signal. can.

〔Effect of the invention〕

In this invention, when an additional code, which is a parameter representing a block obtained by block encoding, and a code signal corresponding to a pixel are transmitted, if the additional code becomes error data, restored data with a very strong correlation is transmitted. Use to restore the attached code. Therefore, according to this invention,
Additional information that is very close to the correct data is restored, and the quality of the restored image can be made good.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of this invention, Figs. 2 and 3 are route diagrams used to explain blocks in an embodiment of this invention, and Fig. 4 is an explanation of operation of an embodiment of this invention. 5 is a block diagram of a transmitting system for block encoding to which this invention can be applied, and FIG. 6 is a block diagram of a receiving system for block encoding to which this invention can be applied. It is. Explanation of main symbols in the drawings 21: Input terminals for received code signals, 22 and 23
; Input terminal for received additional code (DR, MIN);
28.29: selection circuit, 27.30: multiplication circuit and addition circuit for decoding, 4o: memory, 41: additional information restoring unit. Agent Patent Attorney Masato Sugiura Figure 4

Claims (1)

[Claims] A digital image signal is converted into a signal having a block structure, a code signal is formed by encoding each block, and parameters representing each of the blocks are transmitted as an additional code together with the code signal. In a decoding device for block encoding, the additional code is used to calculate the minimum A decoding device for block encoding, comprising: means for obtaining the additional code of the block to be decoded by the method of squares; and means for obtaining restored data from the additional code and the code signal.