JP2861380B2 - Image signal encoding apparatus and method, image signal decoding apparatus and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[Industrial applications]

 The present invention relates to an image data encoding circuit.

Summary of the Invention

According to the present invention, in an image data encoding circuit, by transmitting, as an additional code, a median value of pixel data and data of a 1/2 dynamic range bit-compressed according to the median value, the data must be transmitted. This is to reduce the number of bits of the additional code that is not required.

[Prior art]

As a highly efficient encoding method for video signals, the present inventors have
Adaptive dynamic range coding (hereinafter referred to as "ADRC method")
(December 11, 1986 IEICE presentation)
MR86-43). The ADRC method is an encoding method that utilizes a strong temporal and spatial correlation of a video signal. That is, when an image is divided into blocks, each block often has only a small dynamic range due to local correlation. Therefore, in the ADRC method, for example, as shown in FIG. 5, an image is divided into blocks, and a minimum value MIN and a dynamic range DR for each block are obtained.
Then, for each block, a difference ΔD between each pixel data and the minimum value MIN is obtained, and this difference ΔD is adaptively re-encoded to compress each pixel data into a smaller number of bits than the original number of bits. Then, the minimum value MIN and the dynamic range DR of each block are transmitted in units of blocks, and the re-encoded pixel data is transmitted in units of pixels. In this case, as a method of dividing the image into blocks, a method of dividing the image only in the horizontal direction (one-dimensional ADRC method), a method of dividing the image into horizontal and vertical rectangular regions (two-dimensional ADRC method), a spatial region covering a plurality of frames (3D ADRC method) has been proposed.
JP-A-61-144990, JP-A-62-92620, etc.). And in the three-dimensional ADRC method, 2
A motion between frames is detected, and pixel data of, for example, a subsequent block is not sent in a still block. In this method, 1-bit motion information data is required for each block. However, for a still block, 1/2 data compression can be performed. When a new number of bits is allocated for re-encoding, the number of bits is fixed in each block and the quantization step width is changed for each block according to the dynamic range (fixed-length ADRC method). Method to change the number of bits corresponding to the dynamic range for each and to keep the quantization step width constant (variable length ADRC
(Japanese Patent Application Laid-Open No. 61-147689, etc.). FIG. 6 shows an example of an encoding circuit using the fixed-length ADRC method. That is, the video signal is supplied to the A / D converter 12 through the input terminal 11 and A / D-converted into pixel data with a quantization bit number of, for example, 8 bits. This pixel data is supplied to the block division circuit 13 and It is divided into blocks for each two-dimensional area of 4 pixels × 4 lines. Then, the pixel data of each block is supplied to the maximum / minimum value detection circuit 14, and the maximum value MAX and the minimum value MIN of the pixel data of each block are detected. Then, the maximum value MAX and the minimum value MIN are supplied to the subtraction circuit 15 to calculate the dynamic range DR. The dynamic range DR and the minimum value MIN from the detection circuit 14 are supplied to the framing circuit 16. Further, the pixel data from the dividing circuit 13 is
Is supplied to a subtraction circuit 22 through a delay circuit 21 for compensating a time delay of the data, and the minimum value MIN from the detection circuit 14 is supplied to a subtraction circuit 22 to calculate difference data ΔD. DR is supplied to the adaptive encoder 23 and, for example, 4-bit pixel data DT
Are re-encoded (re-quantized), and the re-encoded pixel data DT is supplied to the framing circuit 16. Then, in the framing circuit 16, the minimum value MIN and the dynamic range DR for each block, and the re-encoded pixel data DT are combined into a signal of a predetermined format, and this signal is output to the image output terminal 17. The data is supplied to a transmission path (not shown) such as a file device. In the case of the variable length ADRC method, the dynamic range
The number of bits of the pixel data DT is changed in accordance with DR, and data indicating the number of bits is transmitted in block units. FIG. 7 shows an example of a decoding circuit based on the fixed-length ADRC method. That is, a signal from the transmission path is supplied to the frame resolving circuit 32 through the input terminal 31 and decomposed into pixel data DT, a minimum value MIN, and a dynamic range DR, and the pixel data DT and the dynamic range DR are adaptive. decoder
33, the difference data ΔD is decoded, and this data ΔD is supplied to the addition circuit 34,
The minimum value MIN from 32 is supplied to the adding circuit 34 and
The bit pixel data is reproduced. Then, the pixel data is rearranged into pixel data in the order of the original time axis when supplied to the block decomposition circuit 35, and the rearranged pixel data is converted into a D / A converter 36.
The video signal is then D / A converted to the original video signal, and the video signal is taken out to the output terminal 37.

[Problems to be solved by the invention]

As described above, in the ADRC method, the minimum value MIN and the dynamic range DR are transmitted as an additional code for each block, but in the above case, when the original video signal is A / D converted to pixel data, Since quantization is performed with 8 bits, the minimum value MIN and the dynamic range DR are also each 8-bit data. Therefore, the minimum value MIN and the dynamic range DR
Therefore, it is necessary to transmit a total of 16 bits of data for each block. However, as described above, if the block size is 4 pixels × 4 lines and the number of bits of the re-encoded pixel data DT is 4 bits, the ratio of the additional code in one block is 16 bits / ( (4 pixels × 4 lines × 4 bits) = 25%, which is very large. The smaller the block size or the smaller the number of bits of the re-encoded pixel data DT, the greater the proportion of the additional code occupied and the lower the compression ratio. An object of the present invention is to reduce the number of bits of an additional code in the ADRC method.

[Means for Solving the Problems]

Now, assuming that A = (MAX + MIN) / 2 B = (MAX-MIN) / 2 as the values A and B as shown in FIG. That is, the value A is a median of the maximum value MAX and the minimum value MIN, and the value B is a half value of the dynamic range DR. When the maximum value MAX and the minimum value MIN are 8 bits, the sum (MAX + MIN) of these bits is 9 bits, but since the half thereof is the value A, the value A can be represented by 8 bits. it can. Also, since 0 ≦ (MAX−MIN) ≦ 255, a relationship as shown in FIG. 4 is established between the value A and the value B. In FIG. 4, (1) when 0 ≦ A ≦ 63, the value B is in the range of 0 to 63, and the value B can be represented by 6 bits. (2) When 64 ≦ A ≦ 128 The value B is in the range of 64 to 127. However, the complement (127−
When B) is obtained, it is in the range of 63 to 0 and can be represented by 6 bits. (3) 128 <A ≦ 191 The value B is in the range of 127 to 64. However, the complement (127−
When B) is obtained, it is in the range of 0 to 63 and can be represented by 6 bits. (4) When 192 ≦ A ≦ 255 The value B is in the range of 63 to 0, and the value B can be represented by 6 bits. It is. The present invention reduces the number of bits when transmitting an additional code by focusing on the above points. That is, in the encoding circuit according to the present invention, when the maximum value MAX and the minimum value MIN are 8 bits, the value A is transmitted as 8 bits as an additional code, and the value B is transmitted as the value A.
The data is converted into 6 bits as shown in the items (1) to (4) in accordance with the size of the data, and the effective 6 bits are transmitted. In the decoding circuit, the value B is inversely transformed by the value A to obtain the original value B, and by doubling the value, the dynamic range DR can be obtained, and the difference (A) between the values A and B is obtained. −
Taking B), the minimum value MIN can be obtained.

[Action]

According to the value A, the value B is subjected to data conversion as shown in the items (1) to (4) to reduce the number of bits of the additional code. Therefore, the number of bits transmitted is, for example, 2 per block. Bits are reduced.

【Example】

FIG. 1 shows an example of an encoding circuit according to the present invention. The maximum value MAX and the minimum value MIN from the detection circuit 14 are supplied to an addition circuit 41 to extract a sum (MAX + MIN). The data A having the value A is supplied and taken out, and the data A is supplied to the framing circuit 16 as an additional code. Further, the maximum value MAX and the minimum value MIN from the detection circuit 14 are supplied to the subtraction circuit 43, and the dynamic range DR (= MAX−M
IN) is taken out, and the dynamic range DR is supplied to the dividing circuit 44 to take out the data B of the value B. The lower 6 bits of the data B correspond to the switch circuit.
In addition to the data B, all the bits of the data B are supplied to the conversion circuit 46, where they are converted into the complement data B in the above items (2) and (3), and the lower 6 bits of the data B are switched. It is supplied to a circuit 45. Further, the data A from the dividing circuit 42 is supplied to a discriminating circuit 47 to discriminate which of the items (1) to (4) is included in the value A. And the signal S47 is given by the terms (1) and (4)
In the case of the term, the switch circuit 45 is switched to the state of FIG. 1, and the signal S47 is changed to the terms (2) and (3).
In the case of the item (1), the switch circuit 45
The state is switched to the opposite state as shown. Then, the output signal of the switch circuit 45 is supplied to the framing circuit 16. Therefore, when the value A is the term (1) or (4), the switch circuit 45 has been switched to the state shown in FIG.
Is supplied to the framing circuit 16 as it is. Also, the re-encoded pixel data from the encoder 23
DT is also supplied to the framing circuit 16. Then, in the framing circuit 16, the data A and B for each block and the re-encoded pixel data DT for each pixel are synthesized into a signal of a predetermined format, and this signal is transmitted through an output terminal 17 to a transmission path. Supplied to On the other hand, when the value A is the terms (2) and (3), the switch circuit 45 has been switched to the state opposite to that shown in FIG. Is converted as shown in (2) or (3), and the lower 6 significant bits are supplied to the framing circuit 16 through the switch circuit 45. Therefore, in the framing circuit 16, the data A and B for each block and the re-encoded pixel data DT for each pixel are combined into a signal of a predetermined format, and supplied to the transmission path via the terminal 17. FIG. 2 shows an example of a decoding circuit paired with the above-mentioned encoding circuit. That is, in FIG. 2, data A, data B, and pixel data DT are separated and taken out from the frame decomposition circuit 32, and at this time, data B is added with 2 bits at an upper position and becomes 8 bits. It is said. The data B is supplied to the switch circuit 51 and supplied to the conversion circuit 52, where the data B is inversely converted to the original data B corresponding to the above items (2) and (3). B
Is supplied to the switch circuit 51. Further, the data A from the decomposing circuit 32 is supplied to the discriminating circuit 55 to determine which of the items (1) to (4) is included in the value A. And the signal S55 is provided as (1) and (4)
Term, the switch circuit 51 is connected to the second
When the state is switched to the state shown in the figure and the signal S55 indicates the case of the items (2) and (3), the switch circuit 51
Is switched to the state opposite to that in FIG. Then, the output signal of the switch circuit 51 is multiplied by the multiplication circuit 53.
And supplied to the subtraction circuit 54. Therefore, when the value A is the term (1) or (4), the switch circuit 51 is switched to the state shown in FIG. 2, so that the data B from the framing circuit 32 is passed through the switch circuit 51 as it is. It is supplied to the multiplication circuit 53 and the subtraction circuit 54. When the value A is in the terms (2) and (3), the switch circuit 51 has been switched to the state opposite to that in FIG. 2, so that the data B from the framing circuit 32 becomes (2). ) And (3) are converted back to the original data B, and this data B is passed through the switch circuit 51 to the multiplication circuit 53.
And supplied to the subtraction circuit 54. In the multiplication circuit 53, the data B supplied thereto is doubled to form a dynamic range DR. The dynamic range DR is supplied to the decoder 33, and the pixel data DT from the frame decomposition circuit 32 is supplied to the encoder 33. The difference data ΔD is supplied to 33 and decoded, and the data ΔD is supplied to the addition circuit 34. Further, the data A from the frame decomposition circuit 32 is subtracted from the subtraction circuit.
The minimum value MIN is taken out by being supplied to 54 and subtracted from the data B, and this minimum value MIN is supplied to the addition circuit 34. Therefore, the original pixel data is extracted from the adding circuit 34, and this pixel data is
The video signal is sequentially supplied to the D / A converter 36 and the original video signal is taken out at a terminal 37.

【The invention's effect】

Thus, according to the present invention, the maximum value MAX and the minimum value M
According to the magnitude of the median value A of IN, the value B of the half of the dynamic range DR is bit-compressed, and the bit-compressed value B and value A are transmitted as additional codes. Even if the dynamic range DR is 8 bits each, the number of bits of the additional code is 14 bits, and the ratio of the additional code to the transmitted data can be reduced. For example, in the above case, the ratio occupied by the additional code in one block is 14 bits / (4 pixels × 4 lines × 4 bits) = 21.9%. Moreover, in this case, there is almost no deterioration in image quality due to compression of the number of bits of the additional code. Actually, the divisions of the division circuits 42 and 44 are performed by adding circuits.
It is only necessary to shift the data A and DR from the 41 and the subtraction circuit 43 rightward by one bit and supply them to the next stage, and no specific parts or circuits are required. Further, the multiplication of the multiplication circuit 53 is performed by dividing the input data B by one.
It is only necessary to shift the bit left and supply it to the next stage, and no specific parts or circuits are required.

[Brief description of the drawings]

1 is a system diagram showing an example of the present invention, FIG. 2 is a system diagram showing an example of a decoding circuit, FIG. 3 is a characteristic diagram for explaining the present invention, and FIG. 4 is a diagram for explaining the present invention. FIG. 5 is a diagram for explaining the ADRC method, and FIGS. 6 and 7 are system diagrams of a conventional example. 12; A / D converter 13; block division circuit 14; maximum / minimum value detection circuit 16; framing circuit 23; adaptive encoder 41; addition circuits 42, 44; division circuit 43; subtraction circuit 46; conversion circuit 47; discrimination circuit

Claims (4)

(57) [Claims] An image signal encoding apparatus for dividing a digital image signal into blocks each having a predetermined number of pixel data and encoding each of the blocks detects a maximum value and a minimum value of the pixel data in the block. Means for calculating difference data between the detected maximum value or minimum value and each pixel data; and each difference data corresponding to the dynamic range defined from the maximum value and the minimum value. Means for encoding to a smaller number of bits than the number of bits to generate encoded data; means for calculating a median of the maximum value and the minimum value; and means for calculating a half value of the dynamic range. Means for converting a half value of the dynamic range to a complement corresponding to the median value; data corresponding to the median value and valid lower bits of the complement Means for transmitting, together with the encoded data, data corresponding to the image signal. 2. An image signal encoding method for dividing a digital image signal into blocks each consisting of a predetermined number of pixel data, and encoding each of the blocks, wherein a maximum value and a minimum value of the pixel data in the block are detected. Calculating difference data between the detected maximum value or minimum value and each pixel data, and calculating each difference data according to the dynamic range defined from the maximum value and the minimum value by the number of bits of the pixel data. Generate encoded data by encoding to a small number of bits, calculate the median of the maximum value and the minimum value, and the value of 1/2 of the dynamic range, and calculate the value of 1/2 of the dynamic range as The data is converted to a complement corresponding to the median value, and data corresponding to the median value and data corresponding to valid lower bits of the complement are transmitted together with the encoded data. Image signal encoding method. 3. An image signal decoding apparatus for decoding coded data obtained by coding a digital image signal for each block of a predetermined number of pixel data, comprising: The data corresponding to the median of the maximum and minimum values, and the validity of the complement obtained by converting half the value of the dynamic range defined from the maximum and minimum values according to the median Data corresponding to the lower bits, and the difference data between the maximum value or the minimum value and each pixel data are encoded into a smaller number of bits than the number of bits of the pixel data corresponding to the dynamic range. Means for receiving the encoded data, decoding the dynamic range from the data corresponding to the effective lower bits of the complement, and Decoding means for decoding the coded data corresponding to the range to generate difference data; and data obtained from data corresponding to the median value and data corresponding to valid lower bits of the complement, and Means for restoring each pixel data from the obtained difference data. 4. An image signal decoding method for decoding encoded data obtained by encoding a digital image signal for each block composed of a predetermined number of pixel data, comprising the steps of: The data corresponding to the median of the maximum and minimum values, and the validity of the complement obtained by converting half the value of the dynamic range defined from the maximum and minimum values according to the median Data corresponding to the lower bits, and the difference data between the maximum value or the minimum value and each pixel data are encoded into a smaller number of bits than the number of bits of the pixel data corresponding to the dynamic range. Receiving the encoded data, decoding the dynamic range from the data corresponding to the valid lower bits of the complement, and Correspondingly, the encoded data is decoded to generate differential data, and data obtained from data corresponding to the median and data corresponding to valid lower bits of the complement and the decoded differential data are used. An image signal decoding method for restoring each pixel data.