JP2861381B2 - Image signal encoding apparatus and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

 The present invention relates to an image data encoding circuit.

Summary of the Invention

The present invention provides an image data encoding circuit that includes, for example, a combination of a minimum value and a dynamic range.
Transmission is performed by replacing a combination that requires all bits with a minimum value and does not require all bits with a combination that requires a dynamic range with all bits without requiring a minimum value with all bits. The number of bits to be performed is reduced.

[Prior art]

As a highly efficient encoding method for video signals, the present inventors have
Adaptive dynamic range coding (hereinafter referred to as "ADRC method")
(December 11, 1986 IEICE presentation)
MR86-43). The ADRC method is an encoding method that utilizes a strong temporal and spatial correlation of a video signal. That is, when an image is divided into blocks, each block often has only a small dynamic range due to local correlation. Therefore, in the ADRC method, for example, as shown in FIG. 4, an image is divided into blocks, and a minimum value MIN and a dynamic range DR for each block are obtained.
Then, for each block, a difference ΔD between each pixel data and the minimum value MIN is obtained, and this difference ΔD is adaptively re-encoded to compress each pixel data into a smaller number of bits than the original number of bits. Then, the minimum value MIN and the dynamic range DR of each block are transmitted in units of blocks, and the re-encoded pixel data is transmitted in units of pixels. In this case, as a method of dividing the image into blocks, a method of dividing the image only in the horizontal direction (one-dimensional ADRC method), a method of dividing the image into horizontal and vertical rectangular regions (two-dimensional ADRC method), a spatial region covering a plurality of frames (3D ADRC method) has been proposed.
JP-A-61-144990, JP-A-62-92620, etc.). And in the three-dimensional ADRC method, 2
A motion between frames is detected, and pixel data of, for example, a subsequent block is not sent in a still block. In this method, 1-bit motion information data is required for each block. However, for a still block, 1/2 data compression can be performed. When a new number of bits is allocated for re-encoding, the number of bits is fixed in each block and the quantization step width is changed for each block according to the dynamic range (fixed-length ADRC method). Method to change the number of bits corresponding to the dynamic range for each and to keep the quantization step width constant (variable length ADRC
(Japanese Patent Application Laid-Open No. 61-147689, etc.). FIG. 5 shows an example of an encoding circuit using the fixed-length ADRC method. That is, the video signal is supplied to the A / D converter 12 through the input terminal 11 and A / D-converted into pixel data with a quantization bit number of, for example, 8 bits. This pixel data is supplied to the block division circuit 13 and It is divided into blocks for each two-dimensional area of 4 pixels × 4 lines. Then, the pixel data of each block is supplied to the maximum / minimum value detection circuit 14, and the maximum value MAX and the minimum value MIN of the pixel data of each block are detected. Then, the maximum value MAX and the minimum value MIN are supplied to the subtraction circuit 15 to calculate the dynamic range DR. The dynamic range DR and the minimum value MIN from the detection circuit 14 are supplied to the framing circuit 16. Further, the pixel data from the dividing circuit 13 is
Is supplied to a subtraction circuit 22 through a delay circuit 21 for compensating a time delay of the data, and the minimum value MIN from the detection circuit 14 is supplied to a subtraction circuit 22 to calculate difference data ΔD. DR is supplied to the adaptive encoder 23 and, for example, 4-bit pixel data DT
Are re-encoded (re-quantized), and the re-encoded pixel data DT is supplied to the framing circuit 16. Then, in the framing circuit 16, the minimum value MIN and the dynamic range DR for each block, and the re-encoded pixel data DT are combined into a signal of a predetermined format, and this signal is output to the image output terminal 17. The data is supplied to a transmission path (not shown) such as a file device. In the case of the variable length ADRC method, the dynamic range
The number of bits of the pixel data DT is changed in accordance with DR, and data indicating the number of bits is transmitted in block units. FIG. 6 shows an example of a decoding circuit based on the fixed-length ADRC method. That is, a signal from the transmission path is supplied to the frame resolving circuit 32 through the input terminal 31 and decomposed into pixel data DT, a minimum value MIN, and a dynamic range DR, and the pixel data DT and the dynamic range DR are adaptive. decoder
33, the difference data ΔD is decoded, and this data ΔD is supplied to the addition circuit 34,
The minimum value MIN from 32 is supplied to the adding circuit 34 and
The bit pixel data is reproduced. Then, the pixel data is rearranged into pixel data in the order of the original time axis when supplied to the block decomposition circuit 35, and the rearranged pixel data is converted into a D / A converter 36.
The video signal is then D / A converted to the original video signal, and the video signal is taken out to the output terminal 37.

[Problems to be solved by the invention]

As described above, in the ADRC method, the minimum value MIN and the dynamic range DR must be transmitted for each block. However, when the original video signal is A / D-converted into pixel data, for example, 8-bit quantization is performed. Therefore, the minimum value MIN and the dynamic range DR are also 8-bit data. Therefore, the minimum value MIN and the dynamic range DR
Therefore, it is necessary to transmit 16-bit data in total. The present invention seeks to reduce the number of bits to be transmitted.

[Means for Solving the Problems]

Now, assuming that the minimum value MIN and the dynamic range DR are 8 bits, since DR = MAX−MIN, the relational expression of DR + MIN ≦ 255 holds, and the combination of data DR and MIN (DR, MIN)
MIN) is the existence range of the hatched area A in FIG. That is, the minimum value MIN and the dynamic range DR are
Even if each bit is 8 bits, the sum (DR + MI
N) does not exceed the maximum value of 255 represented by 8 bits. Further, the minimum value MIN and the dynamic range DR do not require 8 bits at the same time. If the data DR and MIN of the triangular area of DR ≧ 128 in the area A are moved to the triangular area B on the right side, the data DR and MIN can be expressed by 15 bits in total. However, when MIN ≧ 128 and DR + MIN = 255, that is, the area of the line C overlaps with the destination area. However, since the existence probability of this line C is small,
It can be replaced with the area of line D, that is, the area of DR + MIN = 254. The present invention, based on the above considerations, data DR,
This is to reduce the number of bits when transmitting MIN by one bit. That is, assuming that the original data DR and MIN are, for example, 8 bits, in the encoding circuit: (1) When MIN <128, the data DR is transmitted by 8 bits The data MIN is transmitted by 7 bits (2) When MIN ≧ 128, (255−DR) is transmitted as data DR. (255−MIN) is transmitted as data MIN. However, when DR + MIN = 255, the data MIN is reduced by one. ……… (3) Therefore, in the decoding circuit, (4) When DR + MIN ≦ 255, the data DR and MIN are used as is. (5) When DR + MIN> 255, (255−DR) is used as the data DR. Will be used.

[Action]

The combination of the minimum value MIN and the dynamic range DR is transmitted in such a manner as to be replaced by a combination that does not exist originally in correspondence with the combination, and the number of transmitted bits is reduced by one bit for each block.

【Example】

In FIG. 1, reference numerals 41 to 44 denote conversion circuits, 45 and 47 denote comparison circuits, and the conversion circuits 41 to 44 store data DR and MIN in (2),
The conversion is performed in accordance with the item (3). Then, the minimum value MIN from the detection circuit 14 is supplied to the comparison circuit 45 and compared with the reference value “128”, and the comparison output S45
Is supplied to the switch circuits 51 and 52 as a control signal thereof. When MIN <128, that is, in the case of the item (1), the switch circuits 51 and 52 are switched to the states shown in the drawing. Therefore, the dynamic range DR from the subtraction circuit 15
However, through the switch circuit 51, the framing circuit 16
Supplied to Further, the minimum value MIN from the detection circuit 14 is supplied to the conversion circuit 42, where the upper one bit (MSB) is deleted and converted into the data MIN of the item (1).
Is supplied to the framing circuit 16. Therefore, in the case of the term (1), the dynamic range DR is transmitted by 8 bits, the minimum value MIN is transmitted by 7 bits, and both of them are transmitted by 15 bits. On the other hand, in the case of MIN ≧ 128, that is, in the case of the items (2) and (3), the switch circuits 51 and 52 are switched to the opposite states by the signal S45. Further, the minimum value MIN from the detection circuit 14 and the subtraction circuit 15
Is supplied to an addition circuit 46 to obtain data (DR + MIN). This data is compared with a reference value "255" in a comparison circuit 47, and its comparison output S
47 is supplied to the switch circuit 53 as a control signal. When DR + MIN ≠ 255, the switch circuit 53 is switched to the state shown in FIG. Therefore, when MIN ≧ 128 and DR + MIN ≠ 255, that is, when the term (3) is excluded from the term (2), the dynamic range DR from the subtraction circuit 15 is supplied to the conversion circuit 41 ( The data is converted to the data (255-DR) in the item 2), and this data is supplied to the framing circuit 16 through the switch circuit 51. The minimum value MIN from the detection circuit 14 is
The data (2) is supplied to the conversion circuit 43 through (3).
55-MIN), and this data is supplied to the framing circuit 16 through the switch circuit 52. Therefore, when the term (3) is excluded from the term (2), the dynamic range DR is transmitted by 8 bits, the minimum value MIN is transmitted by 7 bits, and the dynamic range DR is transmitted by 15 bits in total. Further, when DR + MIN = 255, the signal S47 switches the switch circuit 53 to a state opposite to that shown in the figure. Therefore, when MIN ≧ 128 and DR + MIN = 255, that is, in the case of item (3) of item (2), the subtraction circuit
The dynamic range DR from 15 is supplied to the conversion circuit 41 and converted into the data (255-DR) in the item (2), and this data is supplied to the framing circuit 16 through the switch circuit 51. Further, the minimum value MIN from the detection circuit 14 is supplied to the conversion circuit 44 and converted into the data (MIN-1) of the item (3).
This data is supplied to the conversion circuit 43 through the switch circuit 53, and is converted into the data (255-MIN) in the item (2). The data is supplied to the framing circuit 16 through the switch circuit 52. Therefore, in the case of item (3) of item (2),
The dynamic range DR is transmitted in 8 bits and the minimum value MI
N is transmitted in 7 bits, and both are transmitted in 15 bits. FIG. 2 shows an example of a decoding circuit paired with the above-mentioned encoding circuit. That is, in FIG. 2, reference numerals 61 and 62 denote conversion circuits, and reference numeral 64 denotes a comparison circuit. The conversion circuits 61 and 62 convert the data DR and MIN according to the item (5). Then, the minimum value MIN and the dynamic range DR from the frame decomposition circuit 32 are supplied to the addition circuit 63 to obtain data (DR + MIN). This data is compared with the reference value “255” in the comparison circuit 64, and the comparison output is obtained. S64 is supplied to the switch circuits 71 and 72 as a control signal thereof. Then, when DR + MIN ≦ 255, that is, in the case of the item (4), the switch circuits 71 and 72 are switched to the states shown in the figure. Therefore, in this case, the minimum value MIN and the dynamic range DR from the frame decomposition circuit 32 are supplied to the addition circuit 34 and the decoder 33 through the switch circuits 71 and 72, and the original 8-bit pixel data is supplied from the addition circuit 33. Is taken out. In the case of DR + MIN> 255, that is, in the case of the item (5), the switch circuits 71 and 72 are switched by the signal S64 to a state opposite to the state shown in the figure. Therefore, in this case, the minimum value MIN and the dynamic range DR from the frame decomposition circuit 32 are
The data (255-MIN) of (5) supplied to 1, 62, (2
55−DR), that is, the original data MIN, DR
These data are supplied to the adder circuit 34 and the decoder 33 through the switch circuits 71 and 72, and the original 8-bit pixel data is extracted from the adder circuit 33. Thus, according to the present invention, even when the minimum value MIN and the dynamic range DR are each 8 bits, the minimum value
When transmitting MIN and dynamic range DR, the minimum value M
Of the combinations of IN and dynamic range DR, the minimum value MIN requires 8 bits and the combination of data that dynamic range DR does not require 8 bits is the minimum value.
MIN does not require 8 bits, dynamic range D
Since R is transmitted by replacing it with a combination of data requiring 8 bits, the number of transmitted bits can be reduced by 1 bit. Alternatively, when the three-dimensional ADRC method is performed, 1-bit motion information data for each block can be transmitted instead of the reduced 1-bit. In the above description, the minimum value MIN and the dynamic range DR can be reversed. Furthermore, (2),
(DR-128) and (MIN-127) can be used instead of (255-DR) and (255-MIN) in the item (5). Also, any two of the minimum value MIN, the maximum value MAX, and the dynamic range DR can be encoded and transmitted in the same manner.

【The invention's effect】

According to the present invention, even if the minimum value MIN and the dynamic range DR are each 8 bits, for example, the minimum value MIN
Minimum value MIN when transmitting dynamic range DR
And the minimum value of the combinations of dynamic range DR
MIN requires 8 bits and dynamic range DR is 8
The combination of data that does not require bits is
N does not require 8 bits, dynamic range DR
Is replaced with a combination of data requiring 8 bits, and the number of bits to be transmitted can be reduced by 1 bit. Alternatively, when the three-dimensional ADRC method is performed, 1-bit motion information data for each block can be transmitted instead of the reduced 1-bit.

[Brief description of the drawings]

FIG. 1 is a system diagram showing an example of the present invention, FIG. 2 is a system diagram showing an example of a decoding circuit, FIG. 3 is a characteristic diagram for explaining the present invention, and FIG. 4 is a diagram for explaining the ADRC method. 5 and FIG. 6 are system diagrams of a conventional example. 12; A / D converter 13; block division circuit 14; maximum / minimum value detection circuit 16; framing circuit 23; adaptive encoder 41 to 44; conversion circuits 45 and 47; comparison circuit

Claims (2)

(57) [Claims] An image signal encoding apparatus for dividing a digital image signal into blocks each including a predetermined number of n-bit pixel data, and encoding each of the blocks. Means for detecting a dynamic range defined from the minimum value, the maximum value and the minimum value, means for calculating difference data between the detected maximum value or minimum value and each pixel data, and the maximum value and the minimum value Means for encoding each difference data into a smaller number of bits than the number of bits of the pixel data in accordance with a dynamic range defined from the value, and generating encoded data; Means for transmitting at least two data of the range together with the encoded data; two transmitted together with the encoded data While the n-bit data of the data and the other (n-m) the picture signal encoding apparatus comprising a means for converting to become bits of data. 2. An image signal encoding method for dividing a digital image signal into blocks each including a predetermined number of n-bit pixel data, and encoding each block. Detect a minimum value, a dynamic range defined from the maximum value and the minimum value, calculate difference data between the detected maximum value or the minimum value and each pixel data, and define a difference data from the maximum value and the minimum value. The difference data is encoded into a smaller number of bits than the number of bits of the pixel data in accordance with the dynamic range to generate encoded data, and the maximum value, the minimum value, and the minimum value transmitted together with the encoded data are generated. One of the two data in the dynamic range is converted into n-bit data and the other is converted into (nm) -bit data. Picture signal encoding method.