JPH0216887A - Picture encodor - Google Patents

Abstract

PURPOSE:To improve encoding efficiency by generating a motion differential picture signal by motion-compensation between two picture signals continuous in point of time, and variable-length-encoding it after orthogonal-transforming and quantizing it. CONSTITUTION:The picture signal at present is predicted from two reduced picture signals of a low frequency component picture signal which is processed by an LPF 2, a sampling circuit 3, a frame memory 6, etc., and is continuous in the point of time, and a motion difference is generated by a motion compensation circuit 7, and is orthogonal-transformed by a discrete cosine transducer 4, and a low frequency component is encoded by a quantizer 5 and 8 variable code length encoder 8. The output of this quantizer 5 is supplied through an expansion circuit 9, and a high frequency component difference is generated, and a high frequency component is encoded similarly. Through the use of constitution to use correlation on a time base by performing the motion compensation on the reduced picture, the encoding efficiency can be extremely enhanced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an image encoding device that is effective for efficiently transmitting images, and in particular, when encoding an image, the encoding is performed with a reduced image size. By using a multi-stage configuration with the original size, an image encoding device that can reproduce low-resolution images by aborting decoding at an intermediate stage, and can reproduce high-resolution images by proceeding with decoding to the final stage. Regarding.

[Conventional technology]

As conventionally known image encoding techniques, those disclosed in the following documents are known.

(1) “Transmj, ss] on of HD T
V signal Sunder140 MbG/s
usjng a 5ub-band Dcconlp.

sN, j, on and r) 1screte
Co5jne TransformCodj ng”
(2nd Internatj, onal Works
hopon Signa] Processj, ng
of F (D TV, vol, ]) (2) "A Study of Orthogonal Transform Coding with a Hierarchical Structure" (Preliminary Papers for the 1985 IEICE Information and Systems Division National Conference 201) As shown in the above document (1) The technology used is horizontal to both signals,
A vertical filter is applied to convert the image signal into four components: 1) Low frequency components in both the horizontal and vertical directions 2) Low frequency components only in the horizontal direction 3) Low frequency components only in the vertical direction 4) Low frequency components in both the horizontal and vertical directions The low-frequency components in both the horizontal and vertical directions are DCT encoded, and the other three components are
It is used for childization and run-length encoding. here,
rl C'r is a discrete cosine transform (Djscret
CCosjr+eTransform).

In addition, the technique shown in the document 2) orthogonally transforms an image in blocks of nXn pixels, and inversely transforms mXm coefficients corresponding to the low frequency components of the orthogonal transform coefficients to create a reduced image. Then, the reduced image is orthogonally transformed again using a block of nXn pixels, the inverse transformation of the mXm coefficients of the low frequency component is repeated a predetermined number of times, and finally, the orthogonal transform coefficients and the orthogonal transform coefficients of the intermediate image are Coefficients corresponding to high frequency components other than Ir1×m are quantized and encoded.

[Problem to be solved by the invention]

However, the above-mentioned conventional technology has the following problems.1゜In other words, the technology shown in Document (1)
Because it does not utilize the correlation between the time axis for motion compensation, etc.
There is a problem that the encoding efficiency and quality are not sufficient.
In addition, since high frequency components are also run-length encoded,
The problem is that the encoding efficiency is sufficient.

On the other hand, with the technique shown in the "Fukui Reference (2)," the reduced image at an intermediate stage is obtained by inversely transforming the low frequency part of the orthogonal transform coefficient, so block noise is likely to occur. Similar to the technique shown in the above-mentioned document (1), since motion compensation is not used, there is a problem that sufficient encoding efficiency cannot be obtained.

The present invention has been made in view of the two-pronged situation, and its purpose is to solve the problems of the conventional technology, such as the two-pronged problem, and to compensate for the time axis by performing motion compensation on a reduced image. An object of the present invention is to provide an image encoding device that improves encoding efficiency by utilizing the second correlation. Another object of the present invention is to provide an image encoding device that improves encoding efficiency by performing orthogonal transform encoding also on high frequency components.

[Means to solve the problem]

The above-mentioned object of the present invention is to generate a low frequency component image signal from an input image signal, subsample the low frequency component image signal in a predetermined method to generate a reduced image signal, and generate a reduced image signal. In an image encoding device that encodes an image signal by performing discrete orthogonal transform on a signal and quantizing the orthogonal transform coefficients, it is possible to perform a discrete orthogonal transform on a signal and quantize the orthogonal transform coefficients. A motion compensation circuit is provided which predicts both current signals from both signals to generate a prediction side belief, and generates a motion difference from the current reduced picture signal, and a motion difference picture signal generated by the motion compensation circuit. After performing discrete orthogonal transformation, first, only the reduced image signal part is encoded by a variable length encoding circuit, and then the enlarged decoded image signal obtained by decoding the bifurcated reduced image signal and performing interpolation enlargement processing and the original image. An image encoding device characterized in that it is configured to generate a high-frequency component image signal based on a signal difference, perform discrete orthogonal transform on the high-frequency component image signal, and encode it using a two-prong variable-length encoding circuit. , or, in addition to the two-pronged means, motion compensation that predicts the current two signals from the temporally previous two signals to generate the predicted two signals, and generates a motion difference with the current high frequency component two signals. This is achieved by an image encoding apparatus characterized in that a circuit is provided to perform motion compensation between two consecutive image signals even for high-frequency component image signals.

[Effect]

In the image encoding device according to the present invention, the low frequency component image signal or the low frequency component image signal and the high frequency component image signal are subjected to motion compensation between two temporally continuous image signals to obtain a motion difference image signal. By orthogonally transforming, quantizing, and variable-length encoding the motion difference side, we can greatly improve the code encoding efficiency, and also create low-resolution images corresponding to the degree of decoding. This makes it possible to obtain multi-stage images ranging from high-resolution images to high-resolution images.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an image encoding device showing an embodiment of the present invention. In the figure, 1- is an image signal input terminal, 2
3 is a low-pass filter (LPF), and 3 is a sub-sampling circuit (SSS) that extracts one pixel every two pixels vertically and horizontally.
), 4 and 1o are the aforementioned DCT circuits (DCT), 5 and 11 are quantizers (Q), and 6 is a frame memory (FM
), 7 is a motion compensation circuit (MC) whose details will be described later, 8 and ]2 are variable length encoding circuits (vr=c), and 9 is an interpolation expansion circuit (TI) whose details will be described later.

Motion compensation, for example, divides both signals into blocks consisting of a predetermined number of pixels, and calculates a predetermined value between some of the pixels included in the block and a block of the previously encoded image. Block matching is performed within the range, and a motion vector indicating the direction in which the block moved is determined from between the blocks where the error between the blocks is the smallest. A predicted image of the current image can be constructed from blocks with smaller errors, and a moving image can be efficiently encoded by encoding the difference image between this predicted image and the current image and the above-mentioned motion vector. I can do it.

FIG. 2 is a diagram showing a specific example of the configuration of the two-pronged motion compensation circuit 7, and shows a motion compensation circuit having a detection range of 2×2 blocks and ±1. In the figure, 33 to 46 are Schiff 1
~Registers (SR), 47-64 are absolute value difference circuits (DF) that calculate the absolute value of the difference, 65-73 and 83-
The old one is an adder circuit (AD), and the ones from 74 to 82 are delay circuits (+)L.
) is shown. The operation of this circuit will be explained below.

31, both encoded past signals are input three lines at a time, and are input to shift registers 33-44. Further, from 32, the current lines of both signals are inputted, and inputted to shift registers 45 and 46. The absolute value difference circuit 47 calculates the absolute value of the difference between the contents of the shift register 33 and the shift register 45, and the absolute value difference circuit 48 calculates the absolute value of the difference between the contents of the shift register 34 and the shift register 46. It will be done.

The same applies to the absolute value difference circuits 49 to 64.

In the adder circuit 65, the outputs of the absolute value difference circuit 47 and the absolute value difference circuit 48 are added. Even in the adder circuits 66 to 73,
The same is true. The M delay circuit 74 delays the output of the adder circuit 65 by one line. The same applies to delay circuits 75 to 82. The adder circuit 83 adds the output of the adder circuit 65 and the output of the delay circuit 74 which is delayed by one line, and calculates the sum of absolute value differences for blocks shifted horizontally and vertically by -1. In the adder circuit 84, the adder circuit 6
The output of 6 and the output of delay circuit 75 are added, and horizontally ○
, the sum of absolute value differences for blocks vertically shifted by -1 is calculated.

Similarly, the adder circuits 85 to 91 also calculate the sum of absolute differences for each block. Based on this result, the motion vector detection unit 92 detects the block with the smallest sum of absolute differences among the 3×3=9 blocks, and determines the direction of the motion vector as 93.

” The direction of the motion back 1 hell determined by the two-pronged motion compensation circuit 7 is sent to the frame memory 6;
Now, based on this, the images previously stored in the frame memory 6 are rearranged to be similar to the current image. That is, in FIG. 1, if a is a current image and b is an encoded image, then C is the image obtained by transforming b so that it becomes closer to a.

FIG. 3 is a diagram showing an example of the operation of the two-pronged interpolation and expansion circuit 9. In the figure, if mouth to mouth are subsampled and encoded pixels, ■=(mouth to mouth)/2 It has a function to perform interpolation and expansion, as shown in the following formula: (1) = (10 mouths) / 2 (2) = (10 m) / 4.

The operation of the image encoding apparatus of this embodiment configured as described above is as follows.

Both signals input from the image signal input terminal 1 are sequentially sent to a low-pass filter 2 to generate a low-frequency image. After that, sub-sampling circuit 3.

For example, as described above, sub-sampling is performed in which one pixel is extracted every two pixels vertically and horizontally. At this time, since high frequency components have already been removed from the image signal, deterioration such as moiré does not occur.

For example, if we consider HD TV and ordinary Go
TV has 1125 lines. The number of samples is 2200, and the number of lines on a regular TV is 525. Number of samples: 85
It will be about 8. This sub-sampling circuit 3 converts 1125 → 525 in the vertical direction and 2200 → 8 in the horizontal direction.
If F.58 conversion is performed, a normal TVirlii image can be reproduced by decoding up to the middle of the bit sequence obtained by encoding the I-I D TV image signal.

1125→525 conversion like this, 2200→858
The conversion may be performed by direct subsampling, or
In addition, as described above, a 525 x 858 part in the center of the 525 x 858 image obtained by subsampling vertically and horizontally is cut out to generate a reduced image, and the remaining part is used as a high-frequency component. It may also be realized by encoding the image before encoding it.

The reduced image generated by the two-pronged subsampling circuit 3 is subtracted from the motion prediction result stored in the frame 11 memory 6, and is sent to the DCT circuit 4. , DCT circuit 4 divides the image signal into blocks each consisting of a plurality of pixels and performs discrete orthogonal transformation, and the transform coefficients are quantized by quantizer 5. The quantized value is encoded by a variable length encoding/encoding circuit 8. The output of the quantizer 5 is summed with the motion prediction value to generate a decoded image that is the same as the image to be decoded on the decoder side, and is sent to the frame memory 6 and the interpolation expansion circuit 9.

As described above, the motion compensation circuit 7 generates a predicted image from the previous image and the current image stored in the frame memory 6, and stores it in the frame memory 6.

The first stage decoded image sent to the interpolation enlargement circuit 9 is interpolated and enlarged to the original image size. The difference signal between the enlarged first-stage decoded signal and the original image is sent to the DCT circuit 10.
Copy orthogonal transformation is performed in , and the transform coefficients are quantized in quantizer 11 . The quantized value is encoded by the variable length encoding circuit 12, and second-stage encoding is performed. The motion compensation circuit 7 divides both signals into blocks, calculates the difference error between the two images, and in blocks in the vicinity of the two images.
Effective motion compensation can be performed by performing matching that selects the one with the minimum error.

If the motion compensation, quantization, variable length encoding, etc. of the reduced image are the same as those for encoding ordinary TV signals, compatibility with ordinary TV encoding is ensured. Furthermore, since motion compensation is performed on the reduced image, the amount of motion compensation processing can be reduced compared to performing it on the original size, and the effects of noise are also reduced.
There is also.

Various orthogonal transforms other than the above-mentioned DCT can be considered as the orthogonal transform, but DCT is common and has excellent characteristics. In this way, by using a two-stage encoding configuration, if the first stage is decoded, normally 1゛■,
If the second stage is decoded, an HD TV image can be decoded.

As described above, by using motion compensation, the amount of code can be significantly reduced and highly efficient encoding becomes possible. for example,
In the case of conventional TI D TVs, in order to detect the same amount of movement as normal TVs, it is necessary to expand the area in which block matching is performed, and the number of pixels is large, so it is necessary to However, according to the second embodiment, it is possible to obtain the same characteristics as using motion compensation directly for HD TV images. be able to.

In addition, in the two-prong embodiment, only two-stage processing is shown, but multi-stage processing of three or more stages can be implemented in the same way.

FIG. 4 is a block configuration diagram of an image encoding device showing another embodiment of the present invention, and corresponds to claim 2.

In the embodiment shown above, only the J:9 orthogonal transform was used in the second stage encoding, but since some frame 11 correlation remains even in the high frequency component, the motion difference is also
Perform motion compensation.

In this embodiment, symbols 1 to 9 indicate the same components as shown in FIG. 1 earlier, and the operations are also the same. The feature of the operation of this embodiment is that the difference between the output of the interpolation expansion circuit 9 and the original image is obtained, the difference is taken from the motion prediction result stored in the frame memory port, and the difference is taken from the result of the motion prediction stored in the frame memory port. , at the point where it is subjected to DCT transformation processing. On the DCT circuit, both signals are divided into blocks each consisting of a plurality of pixels, subjected to discrete orthogonal transform, and the transform coefficients are quantized by a quantizer]1.

The quantized value is encoded by a variable length encoding circuit 12.

According to the present embodiment, high-frequency components may also be processed with some complexity, but they can be encoded efficiently for transmission.

FIG. 5 is a block configuration diagram of an image encoding device showing still another embodiment of the present invention, which, like the embodiment shown in FIG. 4, corresponds to claim 2. be.

In this embodiment as well, the symbols "-9" indicate the same components as shown in FIG. 1, and the operations are also the same. The feature of this embodiment is that the subsampling circuit 3
For example, 1125→288.2200→360 conversion circuit, subsampling circuit 16 is ]125→525°2200
-+858 conversion circuit, 384Kbi, t/s
ee CT format used in VTDEOC0DEC (video encoding device) 1 ~ → Normal TV format → I-T D TV format images will be included, and only the output from the variable length encoding circuit 8 will be included. When decoding, the output from the variable length encoding circuits 8 and 12 is normal TV. When the output from the variable length encoding circuits 8 and 12 is decoding, it is I(1) T.
V images can be decoded.

According to this embodiment, not only compatibility between HD TV and regular TV but also compatibility between various format images can be realized.

[5] Note that the two-pronged embodiment is shown as an example of the present invention, and the present invention is not limited thereto.

〔Effect of the invention〕

As described above, according to the present invention, a low frequency component image signal is generated from an input image signal, and the low frequency component image signal is subsampled by a predetermined method to generate a reduced image signal. In an image encoding device that encodes an image signal by performing discrete orthogonal transform on the reduced signals and quantizing the orthogonal transform coefficients, the , predict the current two signals from the temporally previous two signals? A motion compensation circuit that generates a l1l1 picture signal and a motion difference with the current reduced picture signal is provided, and the motion difference picture signal generated by the motion compensation circuit is subjected to discrete orthogonal transformation. Then, a high-frequency component image signal is generated based on the difference between the enlarged decoded image signal and the original image signal obtained by decoding the reduced image signal and performing interpolation enlargement processing. Since the high frequency component image signal is configured to undergo discrete orthogonal transformation and is encoded by the variable length encoding circuit, it is possible to achieve a remarkable effect of realizing an image encoding apparatus with improved encoding efficiency.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an image encoding device showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of the structure of a motion compensation circuit which is the main part thereof, and FIG. 3 is an operation of an interpolation expansion circuit. Illustration showing an example, 4th
5 are configuration diagrams showing other embodiments of the present invention. image signal input terminal, 2: low-pass filter, 3: subsampling circuit, 4. ,．． 10.18: DCT
Circuit, 5, II, I9: Quantizer, 6, 13, 2]:
frame 11 memory, 7, I/1, 22: motion compensation circuit, R, 12, 20: variable length encoding circuit, 9. ．． 1.7
: Interpolation expansion circuit. Patent applicant Nippon Telegraph and Telephone Corporation

Claims (2)

[Claims] (1) Generate a low-frequency component image signal from the input image signal, subsample the low-frequency component image signal using a predetermined method to generate a reduced image signal, and perform discrete orthogonal transform on the reduced image signal. By quantizing the orthogonal transform coefficients,
In an image encoding device that encodes both signals, a predicted image signal is generated by predicting a current image signal from a temporally previous image signal between two temporally consecutive images of the reduced image signal,
A motion compensation circuit that generates a motion difference with the current reduced image signal is provided, and the motion difference image signal generated by the motion compensation circuit is subjected to discrete orthogonal transformation. and then generate a high frequency component image signal based on the difference between the enlarged decoded image signal and the original image signal obtained by decoding the reduced image signal and performing interpolation enlargement processing,
An image encoding device characterized in that the high frequency component image signal is configured to undergo discrete orthogonal transformation and is encoded by the variable length encoding circuit. (2) In addition to the above-mentioned means, a motion compensation circuit that predicts the current image signal from the temporally previous image signal to generate a predicted image signal and generates a motion difference with the current high-frequency component image signal is provided. 2. The image encoding apparatus according to claim 1, wherein motion compensation is performed between two consecutive image signals also for high frequency component image signals.