JPH02272972A - Still picture transmitter - Google Patents

Abstract

PURPOSE:To execute an optimum block encoding responding to the difference between signals being the objects of the block encoding at two block encoding means by making encoding code tables for the block encoding in two encoding means to be mutually different. CONSTITUTION:The outputs of a first encoding means 24 to block-encode the block signal composed of the prescribed number of picture element signals obtained from multistage thinning out processing circuits 21 and 23 and a second encoding means 30 to block-encode the block signal composed of the prescribed number of difference picture element signals obtained from a difference detecting means 29 are successively transmitted. Here, the encoding code tables for the block encoding at the first and second encoding means 24 and 30 are made mutually different. Thus, for the block encoding at the first and second encoding means 24 and 30, the optimum block encoding responding to the difference between the signals being the objects of the encoding can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a still image transmission device that hierarchically encodes still image signals and transmits the same.

[Summary of the invention]

The present invention supplies an input still image signal to a multi-stage thinning processing circuit connected in series and performs multi-stage thinning processing to obtain a block signal consisting of a predetermined number of pixel signals, and the block signal is processed by a first encoding means. Block encoding is performed, the block encoded signal is decoded by a decoding means, the block signal obtained by decoding is interpolated by an interpolation means, and the difference detection means outputs the output of the interpolation means and the output of the multistage thinning processing circuit. A block signal consisting of a predetermined number of differential pixel signals obtained from the difference detection means is
In the still image transmission device in which block encoding is performed by the second encoding means, the encoding code tables for block encoding in the first and second encoding means are made to be different from each other. It is possible to perform optimal block encoding according to the difference in signals to be block encoded by the first and second block encoding means.

(Prior Art) A conventional still image transmission device will be explained below with reference to Fig. 6. (1) is a microcomputer,
U (central processing unit) (2), ROM (3) and R
It is composed of A M (4). (5) is CPU
(2) bus (consisting of data bus, address bus, control bus, etc.). This microcomputer (1) controls each part of this still image transmission device. (13) is a transmission line, which can be wireless or wired, but in the case of a wired transmission line, it is an I5DN (Integrated Services Digital Network), high-speed digital line, analog telephone line, DDX (Digital Data - Exchange networks (there are two types: DDXC and DDXP), dedicated lines, etc. are possible.

(12) is a communication processing circuit that is connected between the transmission line (13) and the bus (5) and performs signal processing according to the protocol and transmission speed of the still image signal of the transmission line (13); In the interface, the communication processing means transmission processing and reception processing such as encoding, modulation, etc. for transmission, and decoding, demodulation, etc. for reception, respectively.

(6) is a frame memory (video memory) whose digital video signal input/output terminal and control signal input terminal are connected to the bus (5), and whose digital video signal input terminal is A
/D converter (10), its digital video signal output terminal is connected to the input terminal of the D/A converter (7), and its other control signal input terminal is connected to the display timing control circuit. (11) is connected to the output terminal. The writing and reading of this video memory (6) is controlled by the microcomputer (1).

Note that this video memory (6) includes horizontal and vertical address counters, a memory controller, etc.

(9) is an analog video signal input terminal, and the video signal from this input terminal (9) (video signal from a video camera, VTR, etc.) is supplied to the A/D converter (10) and converted into a digital video signal. After being converted, it is supplied to the video memory (6) and written.

(14) is a communication memory, that is, a buffer memory for transmission and reception. The writing and reading of this communication memory (14) is also controlled by the microcomputer (1). Note that this communication memory (14) includes horizontal and vertical address counters, a memory controller, and the like.

(15) is a digital signal processing circuit (DSP) capable of high-speed signal processing, and is equipped with an external RAM (16) and an internal RAM (17), which is also controlled by the microcomputer (1). Ru.

The analog video signal supplied to the input terminal (9) is
After being supplied to a D converter (10) and converted into a digital video signal, it is supplied to a video memory (6) and stored as a digital still image signal. Then, the still image signal stored in the video memory (6) is block-coded by the microcomputer (1) and the digital signal processing circuit (15) for each block signal, that is, orthogonal processing such as discrete cosine transform is performed. Transformation and subsequent compression encoding using variable length encoding such as Huffman encoding are performed,
After being written into and read from the communication memory (14), the data is supplied to the communication processing circuit and interface (12) for transmission processing, and then transmitted to another still image transmission device through the transmission line (13).

In addition, transmission signals supplied from other still image transmission devices to the communication processing circuit and interface (12) through the transmission line (13) are received and processed here, and the resulting orthogonal transformation and compression coding are performed. The digital video signal is written to a communication memory (14), where it is block decoded by a microcomputer (1) and a digital signal processing circuit (15), that is, it undergoes orthogonal inverse transformation and subsequent decompression decoding. After that, each block signal obtained is written into the video memory (6) to form a still image signal. The digital video signal read out from the video memory (6) is supplied to a D/A converter (7) and converted into an analog video signal, and then sent to a monitor receiver (8) equipped with a cathode ray tube. and projected as a still image on the surface of the cathode ray tube.

Next, referring to FIG. 7, IEEE TRANSACT
IONSON COMMUNICATION
E.E.E. Transactions on Comunication).

VOL, C0M-32, NO, 3, MARCI (198
A case will be described in which the adaptive discrete cosine transform (ADCT) encoding disclosed in No. 4 P, 225 to P, 232, etc. is applied to the above-mentioned still image transmission device of FIG. 5.

As shown in Figure 7A, video memory (frame memory)
The digital video signal for one frame (here, for ease of explanation, the video signal is assumed to be a monochrome video signal) stored in (6), that is, the 768×480 signal that constitutes a matrix of 480 rows and 768 columns. The microcomputer (1) outputs the 8-bit pixel signals as shown in FIG. The digital signal processing circuit (15) external RAM (
16).

Each block signal written in this external RAM (16) is subjected to two-dimensional discrete cosine transform (two-dimensional DCT) by this digital signal processing circuit (15). The -northernmost of these is shown below by the formula.

j, k (however, for j, j, k = 0.1, 2, 3
．． ..., N-1)'s sea fence f(j, k) is expressed as the following equation.

However, ulV = 0+1+2+ ・” +N-1 However, 8 rows 8 stored in external RAM (16)
The 8×8 pixel signals constituting the column matrix are obtained by two-dimensional discrete cosine transformation, and the 8×8 coefficient signals (each ,for example,
(rounded to 12 bits) (indicated by a small rectangle), the direct current coefficient (DC) (average value of 8/8 pixel signals) signal comes in the upper left corner, and as it moves away from it in the horizontal and vertical directions, it becomes lower. This results in a distribution of coefficient signals with high frequencies.

Then, by the microcomputer (1), the external R
The coefficients of the 8×8 coefficient signals constituting the 8-by-8 matrix stored in A M Quantization is performed by dividing by the corresponding number and rounding so that the quotient is represented by 8 bits. Figure 7 shows the 8 x 8 quantized coefficient signals (indicated by small rectangles) constituting the 8 rows and 8 columns matrix obtained by this method, and the quantized DC coefficient signal in the upper left corner. As the distance from (DC) increases, coefficient signals with a coefficient of O appear more frequently, and in some cases reach 2/3 of all quantized coefficient signals.

Then, the 8×8 quantized coefficient signals (indicated by small rectangles) shown in the seventh diagram are processed by the microcomputer (1), excluding (or including) the DC coefficient signal in the upper left corner.
After zigzag scanning as shown in Figure 7, compression encoding (Huffman encoding) is performed, and the communication memory (14
). Also, the DC coefficient signal of the quantized coefficient signal is
After compression encoding (Huffman encoding), the data is written into the communication memory (14).

Note that the I of the digital video signal encoded by ADCT
A detailed explanation of ADCT (reverse adaptive/i!iti losing cosinocosine transformation) will be omitted, but to briefly explain, the ADCT stored in the communication memory (14)
The digital video signal encoded by the microcomputer (1) decompresses and decodes (inverse Huffman encoding), scans it in an inverse zigzag manner, dequantizes it, and dequantizes it by the digital signal processing circuit (15). , is subjected to two-dimensional inverse cosine transformation to obtain block signals, and each block signal is loaded into the video memory (6) by the microcomputer (1), and by repeating this process, a still image signal is formed. Ru.

In the conventional still image transmission device described above, a still image signal of a coarse still image is created from the original still image signal to be transmitted, is transmitted to the still image transmission device of the other party, and the transmitted still image signal is interpolated. In addition, a corrected difference signal is created for the interpolated still image signal, and transmitted once or in multiple times to the still image transmission device of the other party, and the still image transmission device of the other party If you add a corrected difference signal to the still image signal of the coarse still image to correct it, the still image will be coarser, but it will be viewed more quickly than when the still image signal is compressed and encoded as it is and transmitted. At the same time, the coarse still image is then gradually corrected to become a fine still image.

Therefore, next, a conventional still image transmission apparatus will be described in which layered encoding and layered decoding are added to compression encoding and expansion decoding, respectively, in the conventional still image transmission apparatus. still,
The overall configuration of the still image transmission device is almost the same as the still image transmission device shown in FIG. 6 described above, so layered compression encoding and layered expansion decoding are applied to the still image transmission device shown in FIG. The case will be explained with reference to FIGS. 8 and 9. In the following explanation, the case of the luminance signal will be explained, and the explanation of the case of the red difference signal and the blue difference signal will be omitted.

FIG. 8 is an explanatory diagram of this conventional layered encoding and layered decoding, and FIG. 9 is an explanatory diagram to assist the explanation.

Each memory in FIG. 8 is one of a plurality of storage areas of a buffer memory provided separately from each memory shown in FIG. 6, and this buffer memory is connected to the bus (5) in FIG. 6. shall be taken as a thing.

In the coding system (layered compression coding system) shown in FIG. 8, 1 is stored in the video memory (frame memory) (6) shown in FIG.
Digital luminance signal (still image signal) for one frame (this is a 480-by-768-column matrix with 7 bits each, each with 8 bits)
It is composed of 68×480 pixel signals, and correspondingly, 16×1 which constitutes a matrix of 12 rows and 16 columns as shown in FIG. 9A.
It is illustrated as a set of rectangles representing two pixels, and based on this, the explanations of layered compression encoding and layered expansion decoding in FIG. 8 will be made easier to understand from FIG. ) and input them to the input terminal of the encoding system (
20) for low-pass filtering and 1/2 thinning processing [
This refers to two-dimensional low-pass filtering and subsequent large-scale 1/2 thinning processing (subsampling) in the horizontal and vertical directions (the same shall apply hereinafter) (21), and then reduction processing and storage in memory (22). Write. The digital luminance signal for one frame (consisting of 384 x 240 pixel signals constituting a matrix of 240 rows and 384 columns of 8 bits each) written in this memory (22) and thinned out to 1/2 is read out. hand,
After performing low-pass filtering and 1/2 thinning processing (23),
Perform an adaptive discrete cosine transform (ADCT) (24).

The above-mentioned low-pass filtering/1/2 thinning process (21), writing and reading in the memory (22), and low-pass filtering/1/2 thinning process (23) are, in short, the sixth
Digital luminance signal (still image signal) for one frame stored in the video memory (frame memory) (6) shown in the figure
(This consists of 768 x 480 pixel signals constituting a matrix of 480 rows and 768 columns, each of which has 8 bits.) (Figure 9A) is read out, and as shown in Figure 9B, it is low-pass filtered and /4 thinning processing (means two-dimensional low-pass filtering processing and large-scale 1/4 thinning processing in horizontal and vertical directions,
The same applies hereafter) (Figure 9B), and if this is reduced and written to memory, 12 bits of 8 bits each
192 x 120 pixel signals in row 0 and column 192 (Figure 9C
), a digital luminance signal (still image signal) corresponding to one frame thinned out to 1/4 is obtained. Then, the digital luminance signal (still image signal) for l frames thinned out to 1/4 is subjected to adaptive discrete cosine transform (ADCT) (24).

This A D CT (24) has 120 bits of 8 bits each.
1/ consisting of 192×120 pixel signals in rows and 192 columns
After writing the digital luminance signal (still image signal) for one frame thinned out into the buffer memory mentioned above, it is written to the microcomputer (1 frame) in the same way as explained in FIG. ), the digital signal processing circuit (15) performs a two-dimensional discrete cosine transform on each block signal, and the microcomputer (1) performs a two-dimensional discrete cosine transform on each block signal.
This means quantization, zigzag scanning, and variable length encoding (Huffman encoding).

In this way, the adaptive discrete cosine transform (ADCT) (24) is output to the output terminal (25).
Digital luminance signal for one frame thinned out to 1/4 (
The still image signal) is transmitted to the other party's still image transmission device, and is decompressed, decoded, and interpolated in a decoding system. This will be explained below. The digital luminance signal (still image signal) for one frame thinned out to 1/4 that has been subjected to adaptive discrete cosine transform (ADCT) from the input terminal (39) is subjected to inverse adaptive discrete cosine transform (IADCT). (40)
be done. This I A D CT (40) is subjected to decompression decoding (Huffman decoding), inverse zigzag scanning, inverse quantization, and two-dimensional inverse cosine transformation by the microcomputer (1) in the same way as described above. The signals are returned to block signals, and from these block signals, the original 192×120 pixel signals (9th
A digital luminance signal (still image signal) for one frame thinned out to 1/4 consisting of FIG. D) is obtained and written to the buffer memory.

Each 8-bit 1 stored in this buffer memory
The digital luminance signal (still image signal) for one frame thinned out to 1/4 consisting of 20 192Xi pixel signals (FIG. 9D) in 20 rows and 192 columns is processed by a microcomputer (
1) 2/1 interpolation processing (means 2/1 interpolation processing in the horizontal and vertical directions, the same shall apply hereinafter)
After (41), it is enlarged and written into the memory (42). One frame's worth of digital luminance signals (consisting of 384 x 240 pixel signals constituting a matrix of 240 rows and 384 columns of 8 bits each) written in this memory (42) and interpolated to 2/1 (9th pixel signal) Read Figure E) and read 2/1
Interpolation processing (43) is performed.

The above-mentioned 2/1 interpolation processing (4I), writing and reading in the memory (42), and 2/1 interpolation processing (43)
In short, each 8 stored in the buffer memory
A 192X1 matrix of bits with 120 rows and 192 columns
The digital luminance signal (still image signal) for one frame thinned out to 1/4 consisting of 20 pixel signals (Fig. 9D) is read out and subjected to 4/1 interpolation processing (horizontal and vertical direction large scale). This means the 2/1 interpolation processing process for each of the 2/1 interpolations (the same shall apply hereinafter), and this is enlarged and stored in the video memory (6
), 768 x 480 pixel signals constituting a matrix of 480 rows and 768 columns of 8 bits each (Figure 9F)
An interpolated digital luminance signal (still image signal) for one frame is obtained.

This interpolated digital luminance signal for one frame (
If the still image signal) is reproduced on the monitor receiver (8) shown in FIG. 6, the still image can be quickly viewed, although it is a rough still image.

Next, the creation, encoding, and decoding of a first modified difference signal for modifying the still picture signal of such a coarse still picture will be explained.

First, in the coding system, an adaptive discrete cosine transform (ADCT) (24) is output to an output terminal (25).
The digital luminance signal (still image signal) for one frame thinned out to 1/4 is processed by inverse adaptive discrete cosine transform (IADCT) (26) (inverse adaptive discrete cosine transform (IADCT) in the decoding system). AD CT) (40)], which makes the original 120 rows of 8 bits each 1
A digital luminance signal (still image signal) for one frame thinned out to 1/4 consisting of 192 x 120 pixel signals constituting a matrix of 92 columns (Fig. 9D) is obtained and written to the buffer memory. It will be done.

Each 8-bit 1 stored in this buffer memory
A digital luminance signal for one frame thinned out to 1/4 consisting of 192 x 120 pixel signals arranged in 20 rows and 192 columns (
The still image signal) (Fig. 9D) is processed by the microcomputer (
Under the control of 1), after performing 2/1 interpolation processing (27) [same as 2/1 interpolation processing (41) in the decoding system], it is enlarged and written to the memory (28). This memory (28)
The digital luminance signal for one frame interpolated to 2/1 (composed of 384 x 240 pixel signals constituting a matrix of 240 rows and 384 columns of 8 bits each) written in (Fig. 9E) is as follows: This is the same as the one stored in the memory (42) of the decoding system, and this is the digital luminance signal for one frame (8 bits each) read out from the memory (22) and thinned out to 1/2. 3 constitutes a matrix of 240 rows and 384 columns of
(consisting of 84x240 pixel signals), subtractive filtering (
29) and the 2/1 interpolation process (41
) is interpolated by the digital luminance signal for one frame (
The 38
A first modified differential signal (consisting of 384×240 differential pixel signals constituting a matrix of 240 rows and 384 columns of 8 bits each) (FIG. 9G) is obtained.

This first modified difference signal is subjected to adaptive discrete cosine transform (ADCT) (30) for each block signal, and the modified difference signal subjected to adaptive discrete cosine transform output from the output terminal (31) is The still image is transmitted to the still image transmission device.

In the decoding system, the modified difference signal that has been subjected to the adaptive discrete cosine transform (ADCT) from the input terminal (45) is subjected to the inverse adaptive discrete cosine transform (IADCT) (46).
As a result, a first modified difference signal (FIG. 9G) is obtained, which is then read out from the memory (42) as a digital luminance signal for l frames (8 bits each) and interpolated to 2/1.
(consisting of 384 x 240 pixel signals constituting a matrix of 40 rows and 384 columns) (Fig. 9E), is added and filtered (47), and then subjected to 2/1 interpolation processing (48) and sent to an output terminal (49).
If the output is enlarged and written to the video memory (6) in Figure 6, 480 rows and 76 of 8 bits each
A corrected digital luminance signal (still image signal) for one frame (FIG. 9H) consisting of 8 columns of 768×480 pixel signals (FIG. 9H) is obtained.

This interpolated digital luminance signal for one frame (
If the still image signal) is reproduced on the monitor receiver (8) of FIG. 6, the above-mentioned rough still image will be somewhat finely corrected. Note that, according to this correction, not only the roughness of a still image due to interpolation, but also the roughness due to ADCT and IADCT can be corrected.

Next, the creation, encoding, and decoding of a second modified difference signal for modifying such a coarse still image signal will be explained.

First, in the encoding system, an adaptive discrete cosine transform (ADCT) (30) is output to an output terminal (31).
The resulting first modified difference signal is subjected to an inverse adaptive discrete cosine transform (IADCT) (32) (same as the inverse adaptive discrete cosine transform (IADCT) (46) in the decoding system), which transforms the original first It is returned to the corrected difference signal, and this and the memory (28
) read out from the 2/1 interpolated digital luminance signal for one frame (consisting of 384 x 240 pixel signals constituting a matrix of 240 rows and 384 columns of 8 bits each) (Fig. 9E) ) are subjected to additive filtering (33).

This addition filtering (33) is processed by 2/1 interpolation (
34), it is enlarged and stored in the memory (35), read out and stored in the video memory (frame memory) (6) in Figure 6 from the input terminal (20). The digital luminance signal (still image signal) for one frame (FIG. 9A) is subjected to subtraction filtering (36) and interpolated by 2/1 interpolation processing (48) in the decoding system. digital luminance signal (48 bits each)
The second modified difference signal (consisting of 768 x 480 pixel signals forming a matrix of 0 rows and 768 columns) (consisting of a matrix of 480 x 764 columns of 8 bits each)
(FIG. 9I) consisting of 0 differential pixel signals is obtained.

Then, this second modified difference signal is subjected to adaptive discrete cosine transform (ADCT) (37) for each block signal, and the modified difference signal that has been subjected to adaptive discrete cosine transform and outputted from the output terminal (38) is The still image is transmitted to the still image transmission device on the side.

In the decoding system, the modified difference signal that has been subjected to the adaptive discrete cosine transform (ADCT) from the input terminal (50) is subjected to the inverse adaptive discrete cosine transform (I AD CT) (
51), a corrected difference signal (FIG. 9 I) is obtained, which is a digital luminance signal for one frame from the output terminal (49) (768x480 which constitutes a matrix of 480 rows and 768 columns of 8 bits each). consists of pixel signals) (Fig. 9H
) and is subjected to addition filtering (52), output to the output terminal (53), and the output is enlarged and sent to the video memory (6) in Figure 6.
If you write to
Digital luminance signal (still image signal) for one corrected frame consisting of 8 x 480 pixel signals (Fig. 9 J)
will be obtained.

The digital luminance signal (still image signal) for one frame from this output terminal (53) is sent to the monitor receiver (8) shown in Fig. 6.
If the still image is played back, the above-mentioned modified still image will be modified in detail in the still image transmission device of the other party. Note that according to this correction, as described above, not only the roughness of a still image due to interpolation but also the roughness due to ADCT and IADCT can be corrected.

In addition, the external RAM of the digital signal processing circuit (15) in AD CT (24), (30), and (37)
The same quantization matrix, DC Huffman code table, and AC Huffman code table stored in (16) are used.

[Problem to be solved by the invention]

In a still image transmission device that performs such conventional layered compression encoding and layered expansion encoding, during layered compression encoding,
The digital still image signal for one frame is low-pass filtered and
After the thinning process, each block signal is divided into block signals, and each block signal is block coded (first coding), that is, discrete cosine transform (orthogonal transform), and Huffman coding (variable length coding) is performed. Compression encoding) to obtain a digital still image signal of a coarse still image that has been compressed and encoded, and transmit it, as well as a digital still image for one frame that has been subjected to low-pass filtering and thinning processing. A corrected difference signal is obtained by subtractive filtering between the digital still image signals obtained by interpolation processing of the signal, and is subjected to or without low-pass filtering/thinning processing.The corrected difference signal is block encoded (second block coding). ), that is, performs discrete cosine transformation (orthogonal transformation) and Huffman encoding (compression encoding using variable length encoding) to obtain a compression-encoded modified difference signal, which is then transmitted.

In addition, during hierarchical decompression decoding, the digital still image signal of a coarse still image that has been compressed and encoded is decompressed and decoded block by block, and then interpolated to obtain a digital still image signal of a coarse still image. After the encoded modified difference signal is decompressed and decoded for each block signal, the digital still image signal of the coarse still image is modified with or without interpolation processing.

For this reason, such conventional still image transmission has the disadvantage that both the time required for layered compression encoding and layered expansion encoding and the time required for transmission are longer.

In addition, in the block encoding used for the first and second encoding, the same encoding code table (block encoding code table) was conventionally used, so the block encoding used for the first and second encoding It was not possible to optimize block coding for each signal.

In particular, in the case of variable length encoding in the first and second encoding, if the same variable length encoding code table is used, the statistical properties of the signals targeted for the first and second variable length encoding will be affected. Because of the difference, the compression ratio will decrease.

In view of this point, the present invention provides a still image transmission device that hierarchically encodes and transmits still image signals, in which block encoding in the first and second encoding means is performed as a target of the encoding. The purpose is to propose a method that can perform optimal block encoding according to differences in signals.

This is how it was done.

[Means to solve the problem]

The present invention blocks a block signal consisting of a series-connected multi-stage thinning processing circuit (21, 23) to which an input still image signal is supplied, and a predetermined number of pixel signals obtained from the multi-stage thinning processing circuit (2L23). A first encoding means (24) for encoding, a decoding means (26) for block decoding the output of the first encoding means (24), and an interpolation for the output of the decoding means (26). an interpolation means (27) for detecting a signal, a difference detection means (29) for detecting the difference between the output of the interpolation means (27) and the output of the multi-stage thinning processing circuit (21, 23), and It has a multi-stage circuit consisting of a second encoding means (30) for block encoding a block signal consisting of a predetermined number of obtained differential pixel signals, the first and second encoding means (24), ( 30
) in which the outputs of the first and second encoding means (24), (30)
According to the present invention, the encoding code tables for flock encoding in the first and second encoding means (2) are made different from each other.
4) In a still image transmission device in which the outputs of (30) are sequentially transmitted, the first and second encoding means (24)
) and (30) are performed using different encoding code tables.

〔Example〕

An embodiment of the still image transmission device according to the present invention will be described below, but since its overall configuration is substantially the same as that of the still image transmission device shown in FIG. An example in which the hierarchical compression encoding and the hierarchical expansion decoding shown in the figure are applied will be described. Further, in FIG. 1, parts corresponding to those in FIG. 8 are given the same reference numerals and explained.

Each memory in FIG. 1 is one of multiple areas of a buffer memory provided separately from each memory shown in FIG. 6, and this buffer memory is connected to the bus (5) in FIG. shall be However, the memory container of each memory is different from that shown in FIG.

Further, the communication memory (14) shown in FIG. 6 temporarily stores a header signal for each frame of a digital luminance signal and two digital color difference signals, which will be described later, and a subsequent compressed encoded signal during transmission and reception. used as memory for

First, compression encoding by hierarchical ADCT and decompression decoding by hierarchical IADCT by the microcomputer (1) and digital signal processing circuit (15) will be explained with reference mainly to FIG.

The microcomputer (1) resets the digital signal processing circuit (15) at the beginning of each encoding process and decoding process of the digital signal processing circuit (engineering 5), and controls the external The encoding and decoding memory banks of the memory (16) contain encoding and decoding programs, encoding quantization matrices, Huffman code tables (DC and AC Huffman code tables), and zigzag scanning. Each pointer data, each inverse quantization matrix for decoding, each inverse Huffman code table (inverse Huffman code table for DC and AC), each data of an inverse zigzag scanning pointer, etc. are loaded.

Also, under the control of the microcomputer (1), the digital luminance signal for one frame (768 x 480 pixel signals of 8 bits each constituting a matrix of 480 rows and 768 columns) stored in the video memory (6) is controlled by the microcomputer (1). ), 1
A digital red difference signal for one frame (consisting of 384x480 pixel signals of 8 bits each forming a matrix of 480 rows and 384 columns) and a digital blue difference signal for one frame (a matrix of 480 rows and 384 columns) (consisting of 384×480 pixel signals of 8 bits each) are divided into block signals for each digital chant signal, digital red difference signal, and digital blue difference signal, and are output for each block signal. External RAM (15)
The digital Signal processing circuit (
5) The beam is placed in the cent state.

Next, with reference to FIG. 1, hierarchical adaptive discrete cosine transform (hierarchical ADCT) and hierarchical inverse adaptive discrete cosine transform (layer j!IADCT) will be explained.
Here, the case of a still image signal as a luminance signal will be explained, and the explanation of the case of a red difference signal and a blue difference signal will be omitted in principle.

In the coding system (layered compression coding system) shown in Fig. 1, one frame that is α is recorded in the video memory (frame memory) (6) shown in Fig. 6 under the control of the microcomputer (1). digital luminance signal (still image signal) (this is composed of 768 x 480 pixel signals of 8 bits each, forming a matrix of 480 rows and 768 columns),
Divide into block signals consisting of 32x32 adjacent pixel signals forming a matrix of 2 rows and 32 columns, read out each block signal, and supply it to the input terminal (20) of the encoding system to perform low-pass processing. Filtering/1/2 thinning processing (2-dimensional low-pass filtering and subsequent horizontal and vertical decimation
This refers to thinning processing, and the same shall apply hereinafter) (21), and then reduction processing and writing to memory (22).

Also, under the control of the microcomputer (1), a block signal consisting of 16×16 adjacent pixel signals constituting a matrix of 16 rows and 16 columns written in the memory (22) is read out and subjected to low-pass filtering and 1/1 2 thinning process (2
3) to obtain a block signal consisting of 8/8 adjacent pixel signals constituting a matrix of 8 rows and 8 columns, which is subjected to an adaptive discrete cosine transform (ADCT) (24) by a digital signal processing circuit (15). )do.

This AD CT (24) transfers each block signal consisting of 8/8 pixel signals constituting a matrix of 8 rows and 8 columns to an external RAM (16) of a digital signal processing circuit (15).
This digital signal processing circuit (15) performs two-dimensional discrete cosine transformation (orthogonal transformation). In this way, as shown in Figure 7C, a DC coefficient signal (signal with the average value of 8/8 coefficient signals) comes in the upper left corner, and as it moves away from it in the horizontal and vertical directions, it changes from low to high. This results in a distribution of signals with frequency coefficients.

Then, each coefficient of these 8/8 coefficient signals is transferred to an external RA.
M 8/8 quantized coefficient signals forming an 8-column matrix are obtained. In these 8/8 quantized coefficient signals, the quantized DC coefficient signal is located in the upper left corner, and in the part far from the upper left corner, there are many coefficient signals with coefficients O (for example, 2/3 of the total ) are distributed.

In this way, among the 8/8 coefficient signals constituting the 8-by-8 matrix that has been subjected to two-dimensional discrete cosine transform and quantization, the DC coefficient signal in the upper left corner may be directly Huffman encoded. , here, the difference in coefficient between the previous block signal and the DC coefficient signal is taken, and the difference signal is stored in the external RAM.
Huffman encoding (variable length encoding) is performed using the DC Huffman code table written in (16).

Also, among the 8/8 coefficient signals, excluding the DC coefficient signal <8x
The 8-1 coefficient signal becomes 0 when Huffman encoded.
After zigzag scanning, the 8x8-1 zigzag scan pointers forming an 8-by-8 matrix stored in external RAM (16) increase the run length of the data and increase the compression ratio. , the O run length and the non-O value of the obtained 8X8-1 coefficient signals are set as a set, and the external RA
Huffman encoding is performed based on the AC Huffman code table stored in M (16).

Then, the Huffman coding coefficient signal for each block signal consisting of 8/8 pixel signals obtained in this way is as follows:
Starting with the header signal created by the microcomputer (1), it is sequentially written to the communication memory (14) through the output terminal (31), and is processed and modulated by the communication processing circuit/interface (12). The image is then transmitted to the other party's still image transmission device through the transmission line (13).

A Huffman coding coefficient signal corresponding to a block signal consisting of 8×8 pixel signals subjected to adaptive discrete cosine transform (ADCT) from an input terminal (39) of the decoding system is sent to a digital signal processing circuit (15). Inverse adaptive discrete cosine transform (IADCT) (40) is performed.

In this IAD CT (40), a Huffman coding coefficient signal corresponding to a block signal consisting of 8×8 pixel signals is converted into a Huffman code for direct current and an alternating current stored in an external RAM (16). Inverse Huffman encoding is performed using the table and inverse zigzag scanning pointers, respectively.
A quantization coefficient signal constituting an 8-by-8 matrix is obtained, and this is multiplied by a corresponding predetermined multiplier using the 8-by-8 quantization matrix stored in the external RAM (16). After inverse quantization, two-dimensional inverse cosine transformation is performed to obtain the original 8×
A block signal consisting of eight pixel signals is obtained.

A block signal consisting of 8×8 pixel signals obtained by A D CT (24) is processed by a microcomputer (
1), 2×1 interpolation processing (means extensive 2×1 interpolation processing in the horizontal and vertical directions, the same shall apply hereinafter) (
41), the image is enlarged and written into the memory (42). A block signal consisting of 16x16 pixel signals constituting a matrix of 16 rows and 16 columns written in this memory (22) is read out from this, and then subjected to 2x1 interpolation processing (4
3), a block signal consisting of 32×32 pixel signals forming a matrix of 32 rows and 32 columns is obtained.

This block signal consisting of 32×32 pixel signals is
If you write to the video memory (6) in Figure 6 in order, 480
A matrix of 768 rows and 768 columns, each consisting of 8 bits, 768X
An interpolated digital luminance signal (still image signal) for one frame consisting of 480 pixel signals is obtained.

This interpolated digital coating signal for one frame (
If the still image signal) is reproduced on the monitor receiver (8) shown in FIG. 6, the still image can be quickly viewed, although it is a rough still image.

Next, the creation, encoding, and decoding of a first modified difference signal for modifying the still picture signal of such a coarse still picture will be explained.

First, in the coding system, an adaptive discrete cosine transform (ADCT) (24) is output to an output terminal (25).
The resulting 8×8 block signals are processed by the digital signal processing circuit (15) to perform the same cosine as the inverse adaptive discrete cosine transform (IADCT) (26) (inverse adaptive discrete cosine transform CIADCT in the decoding system) (40). As a result, a block signal consisting of the original 8×8 pixel signals is obtained, and this is written into the buffer memory.

A block signal consisting of 8x8 pixel signals stored in this buffer memory is transmitted to a microcomputer (1
), the block signal consisting of 16x16 pixel signals obtained by the enlargement processing is Written to memo IJ (2B).

FIG. 2A shows the stored contents of this memory (28), with small rectangles indicating block signals consisting of 8×8 pixel signals. Then, in this memory (28), 16X
A block signal consisting of 16 pixel signals (this is 8x8
(corresponding to four block signals consisting of pixel signals) constitutes a matrix of 15 columns and 24 rows, that is, 8
A block signal consisting of ×8 pixel signals has 30 rows and 48
stored to form a matrix of columns.

Incidentally, FIG. 2 shows the stored contents of the memory corresponding to FIG. 2A in the case of color difference signals.

The flock signal consisting of 16x16 pixel signals written in this memory (28) is stored in the memory (42) of the decoding system.
) (The memory content of this is also the same as that of memory (28)), and this is the same as that stored in memory (
A block signal consisting of 16×16 pixel signals read out from 22) is subjected to subtraction filtering (29), and then subjected to 2×1 interpolation processing (41) in the decoding system.
A first modified difference signal (consisting of 8×8 differential pixel signals) for a block signal consisting of six pixel signals is obtained.

This first modified difference signal is subjected to adaptive discrete cosine transform (ADCT) (30) by a digital signal processing circuit (15), and the modified difference signal subjected to adaptive discrete cosine transform is output from an output terminal (31). are written to the communication memory (14) through the output terminal (31), starting with the header signal created by the microcomputer (1), and then being processed and processed by the communication processing circuit/interface (12). It is modulated and transmitted to the other party's still image transmission device through the transmission line (13).

In the decoding system, the digital signal processing circuit (15) converts the first modified difference signal from the input terminal (45) into an inverse adaptive discrete cosine transform (ADCT) using the digital signal processing circuit (15). A cosine transform (IADCT) (46) is performed to obtain a first modified difference signal, which is converted to a microcomputer (1
) read out from the memory (42) under the control of
After being added and filtered (47) with a block signal consisting of 16×16 pixel signals, it is subjected to 2/1 interpolation processing (48),
It is output to the output terminal (49). If the output is enlarged and written to the video memory (6) in FIG.
A corrected digital luminance signal (still image signal) for one frame consisting of 80 pixel signals is obtained.

In addition, the IA stored in the external RAM (16)
These Huffman code tables and quantization matrices for DC and AC in DCT (46) are rewritten by the microcomputer (1) according to the Huffman code table and quantization matrix for DC and AC in AD CT (30). It will be done.

This interpolated digital luminance signal for one frame (
If the still image signal) is reproduced on the monitor receiver (8) in FIG. Not only the roughness but also the roughness due to ADCT and IADCT can be corrected.

Next, the creation, encoding, and decoding of a second modified difference signal for further modifying the still picture signal of the still picture that has been modified more or less finely will be explained.

First, in the encoding system, an adaptive discrete cosine transform (ADCT) (30) is output to an output terminal (31).
The resulting first modified difference signal is subjected to an inverse adaptive discrete cosine transform (IAD CT) (32) (same as the inverse adaptive discrete cosine transform (IADCT) (46) in the decoding system), which allows the original 1 is returned to the corrected difference signal, and this and the memory (28
) is subjected to addition filtering (33).

This addition filtering (33) is processed by 2/1 interpolation (
34), then enlarged and written to the memory (35).

Furthermore, when a third modified difference signal is also created, encoded, and decoded, the same processing as the creation, encoding, and decoding of the second modified difference signal is performed. conduct,
The still image signal obtained at the output terminal (53) may be modified using the third modified difference signal.

FIG. 3A shows the stored contents of the memory (35), where small rectangles indicate block signals consisting of 8/8 pixel signals. Then, in this memory (35), 2/1 interpolation (34)
A block signal consisting of 16×16 pixel signals constituting a matrix of 16 rows and 16 columns (this corresponds to 4 block signals consisting of 8/8 pixel signals) is 3
A block signal consisting of 8/8 pixel signals is stored so as to constitute a matrix of 0 columns and 48 rows, that is, a matrix of 60 rows and 96 columns.

Note that this memory (35) requires the above memory capacity when creating the third modified difference signal;
If a corrected difference signal is not created, the capacity to store 192 block signals consisting of 8/8 pixel signals is sufficient if only 1/2 thinning processing is considered, but it is clear from what will be explained later. Since 9/9 pixel signals are required for low-pass filtering of 8/8 pixel signals, a capacity capable of storing 192 9/9 pixel signals is required. That is, when a block signal consisting of 8/8 pixel signals numbered 0.1, . , 1.96.97), but when A D CT (37) is performed, it is a block signal consisting of 8×8 pixel signals. Therefore, A D of a block signal consisting of 8×8 pixel signals with numbers 0.1.2, . . . 190,191.
This is because these block signals can be rewritten once CT (37) is completed.

On the other hand, the memory contents of the memory (28) are later stored in the first
Since it is also used when creating a modified difference signal, as described above, it requires a capacity to store 48x30 block signals each consisting of 8x8 pixel signals.

Incidentally, FIG. 3B shows the stored contents of the memory corresponding to FIG. 3A in the case of color difference signals.

The block signal consisting of 16 x 16 pixel signals written in this memory (35) is read out and subjected to subtraction filtering (36) from the block signal consisting of 32 x 32 pixel signals from the input terminal (20). Then, a second modified difference signal (
(consisting of 8×8 differential pixel signals) is obtained.

This second modified difference signal is subjected to adaptive discrete cosine transform (ADCT) (37) for each block signal by the digital signal processing circuit (15), and is converted into an adaptive discrete cosine transform (ADCT) (37) outputted from the output terminal (38). The converted first modified difference signal starts with the header signal created by the microcomputer (1), and then sequentially passes through the output terminal (38) to the communication memory (
14), is communication processed and modulated by the communication processing circuit/interface (12), and is transmitted to the transmission line (
13) to the other party's still image transmission device.

In the decoding system, the second modified difference signal that has been subjected to the adaptive discrete cosine transform (ADCT) from the input terminal (50) is subjected to the inverse adaptive discrete cosine transform (I AD CT).
) (51) to obtain a second modified difference signal, which is combined with the block signal consisting of 16×16 pixel signals from the video memory (6) in FIG. (47) and output to the output terminal (53), and if the output is enlarged and written to the video memory (6) in FIG. A corrected digital luminance signal (still image signal) for one frame is obtained.

The digital luminance signal (still image signal) for one frame from this output terminal (53) is sent to the monitor receiver (8) shown in Fig. 6.
If the still image is played back, the above-mentioned modified still image will be modified in detail in the still image transmission device of the other party. Note that this correction can also correct not only the roughness of still images due to interpolation, but also the roughness due to ADCT and IADCT.

After this, it is also possible to create third, fourth, etc. modified difference signals to more finely modify the still image of the still image signal, but up to the second modified difference signal is sufficient. , even if it is increased, it is up to the third modified difference signal.

Note that A performed by the digital signal processing circuit (15)
The DCT stores the quantization matrix, DC Huffman code table, and AC Huffman code table, which are stored in its external RAM (16), separately for the luminance signal and the red and blue difference signals, in the video memory (6). Depending on the content of the still image digital video signal for one frame stored, the microcomputer (1) rewrites it to an appropriate one, and the 8X8 signal is compressed and encoded by ADCT.
ADC
Depending on T (24), (30), and (37), the microcomputer (1) rewrites it to an appropriate one that takes into account the statistical properties of the signal to be encoded.

Note that by creating the DC and AC Huffman code tables in consideration of the statistical properties of the signal to be Huffman encoded, it is possible to increase the compression rate by Huffman encoding. Incidentally, the same can be said about general variable length code differentiation.

Also, IADCT (40), (26), (46), (32) performed by the digital signal processing circuit (15)
and (51), (37), external RAM (1
6), the quantization matrix, DC Huffman code table, and AC Huffman code table are stored in the corresponding AD
External RA in CT (24), (30), (37)
It is rewritten according to the quantization matrix, DC Huffman code table, and AC Huffman code table stored in M (16).

In the still image transmission device of the above-described embodiment, for example, in the case of a digital luminance signal (still image signal), the frame memory stores
A digital luminance signal for one frame consisting of 768x480 pixel signals constituting a matrix of 480 rows and 768 columns is stored, and this digital luminance signal is stored as a block signal (first block signal) constituting a matrix of 32 rows and 32 columns. ).

As a result, this frame memory stores 24×15 first block signals forming a matrix of 15 rows and 24 columns.

Then, the 24×15
For the first block signals of・Perform 1/2 thinning processing to form a matrix of 16 rows and 16 columns, respectively.
A block signal (referred to as the second block signal) consisting of 6×16 pixel signals is obtained, and each block signal is sequentially stored in a memory (referred to as the first memory) to form a matrix of 15 rows and 24 columns. Each first block signal read from the first memory is subjected to low-pass filtering and 1/2 decimation processing each time it is stored in the first memory. Block signal (third block signal) consisting of 8/8 pixel signals forming a matrix with 8 rows and 8 columns
is obtained, and the memory (which will be called the second memory) is recessed.

By the way, low-pass filtering processing for each pixel signal constituting a block signal is performed by converting a certain pixel signal into a weighted average of the levels of that certain pixel signal and eight surrounding pixel signals, that is, a total of nine pixel signals. This means replacing the pixel signal with a level of . Therefore, in order to perform low-pass filter processing on the second block signal, 17×17 pixel signals forming a matrix of 17 rows and 17 columns are required.

Therefore, in order to obtain a third block signal by performing low-pass filtering on the second block signal in the upper left corner of the first memory, it is necessary to 16+16+1=33 pixel signals are virtually provided outside the corner, and the level of the virtual pixel signals is set to the middle level between the minimum and maximum levels of the pixel signals, or 16+16-1=31 inside the corner. pixel signals may be used.

Also, in order to perform low-pass filtering on the second block signal on the right side of the second block signal at the upper left corner of the first memory, the upper side and corner of the second block signal must be filtered. 17 virtual pixel signals are provided outside the area, and the level of the virtual pixel signals is the level in the middle of the minimum to maximum levels of the pixel signals, or 16+■=17 at the lower and upper left corner. It is sufficient to adopt the levels of 8 pixel signals and to use the 8 pixel signals in one column on the right side of the second block signal in the upper left corner of the first memory. Moreover, low-pass filtering may be performed on each of the subsequent second block signals in the first row in the same manner.

In addition, in order to perform low-pass filtering on the second block signal immediately below the second block signal at the upper left corner of the first memory, the left side of the second block signal and the corner thereof must be filtered. 17 virtual pixel signals are provided outside of the virtual pixel signal, and the level of the virtual pixel signal is the level in the middle of the minimum to maximum level of the pixel signal, or the one on the right side and upper left corner.
While adopting the level of 6+1=17 pixel signals,
The lower 1 of the second block signal in the upper left corner of the first memory
It is sufficient to use eight pixel signals in a row. Also, following this,
For each second block signal in the first column, low-pass filtering may be performed in the same manner.

Further, for the 24×15 second block signals constituting a matrix of 15 rows and 24 columns stored in the first memory, the first
From the left end of the row to the right end, from the left end of the second row to the right end, etc.
. . . From the left end to the right end of the 15th row, low-pass filtering and 1/2 decimation processing are performed in order to obtain a pixel signal consisting of 8/8 pixel signals forming a matrix of 8 rows and 8 columns, respectively. When obtaining 3 block signals and sequentially writing them into the second memory so as to form a matrix of 15 rows and 24 columns, the second block signals in the first row on the upper side and the first column on the left side are When performing low-pass filtering on each second block signal excluding
As shown in FIG. 4, in the 16×16 pixel signals constituting the 16 rows and 16 columns matrix, each of the second block signals on the upper side, left side, and upper left corner adjacent to the second block signal, Low-pass filtering is performed on 17×17 pixel signals forming a matrix of 17 rows and 17 columns, which are obtained by adding 16+16+1=33 pixel signals.

As shown in FIG. 4, the second block signal consisting of 16x16 pixel signals forming a matrix of 16 rows and 16 columns is the same as the first block signal consisting of 32x32 pixel signals forming a matrix of 32 rows and 32 columns. 32+32+1=65 pixel signals are added to the left side, upper side, and upper left corner of the block signal of 3.
This is obtained by referring to 33x33 pixel signals that form a matrix of 3 rows and 33 columns, and is on the left side and above the second block signal that consists of 16x16 pixel signals that form a matrix of 16 rows and 16 columns. The 17×17 pixel signals forming a matrix of 17 rows and 17 columns with 16+16+1=33 pixel signals added to the upper left corner are 32+32+4=68 pixel signals to the left, upper side, and upper left corner of the first block signal. 35x3 which constitutes a matrix of 35 rows and 35 columns to which pixel signals of
It can be seen that this is obtained by referring to five pixel signals.

Next, with reference to FIG. 5, the low-pass filtering/1/2 decimation processing and 2/1 interpolation processing in the encoding system and decoding system of FIG. 1 and the low-pass filtering/1/2 processing in FIG. A supplementary explanation will be given regarding the thinning process. In FIG. 5, for simplicity, the first block signal is composed of 8/8 pixel signals forming a matrix of 8 rows and 8 columns, and the second block signal is composed of 8/8 pixel signals forming a matrix of 4 rows and 4 columns. The third block signal is composed of 4/4 pixel signals forming a matrix of columns, and the third block signal is composed of 2/2 pixel signals forming a matrix of 2 rows and 2 columns.

In FIG. 5A, for the first block signal, 8+8+1
= 9/9 pixel signals forming a matrix of 9 rows and 9 columns with 17 pixel signals added (small rectangle indicated by a broken line)
Then, low-pass filtering and 1/2 thinning processing are performed to obtain the second block signal (4/4 pixel signals forming a matrix of 4 rows and 4 columns) (the small rectangle shown by the solid line). The inside is filled with dots).

In FIG. 5B, 4+4+1=13 pixel signals are added to the second block signal obtained in FIG. The third block signal (a small rectangle whose inside is filled with dots) is processed by low-pass filtering and 1/2 decimation to produce the third block signal (2/2 which constitutes a 2-by-2 matrix). 2 pixel signals) (the small rectangle indicated by a solid line, the inside of which is filled with diagonal lines) are obtained. Then, the third block signal at the lower right portion of the boundary line a is subjected to ADCT processing.

In FIG. 5C, the third block signal subjected to ADCT processing is divided into 2/2 pixel signals (solid line The small rectangle indicated by , the inside of which is filled with diagonal lines), and the six pixel signals of the second block signal above and to the left of this third block signal (the small rectangle indicated by a broken line, whose inside is filled with diagonal lines) The interior is filled with dots and dashed diagonal lines) in the horizontal and vertical directions.
A pixel signal (the small rectangle indicated by the solid line, the inside of which is filled with dots) is interpolated between the pair of pixel signals, and the second pixel signal is interpolated between the pair of pixel signals. block signal (the small rectangle shown by the solid line,
The inside is filled with diagonal lines and dots). Then, the second block signal at the lower right portion of the boundary line is subjected to 2/1 interpolation in the fifth diagram.

In Figure 5, 4x4 pixel signals (
(a small rectangle indicated by a solid line, the inside of which is filled with dots) and a second block signal on the left side of this second block signal.
Using the four pixel signals of the block signal (the small rectangle indicated by the broken line, the inside of which is filled with dots 1), a pair of pixel signals is placed in the middle of a pair of pixel signals in the horizontal and vertical directions. The pixel signal at the average level of the pixel signal level (the small rectangle shown by the solid line, the inside of which is filled with dots) is interpolated to generate the third block signal (the small rectangle shown by the solid line). In this case, we obtained the dots filled with dots and the dots not filled with dots.

[Effects of the Invention] According to the present invention described above, in a still image transmission device that hierarchically encodes and transmits still image signals, block encoding in the first and second encoding means is performed by the encoding method. Optimal block encoding can be performed depending on the difference in target signals.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of layered compression encoding and layered expansion decoding according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of encoding according to the embodiment, and FIG. 3 is an explanatory diagram of decoding according to the embodiment. FIG. 4 is an explanatory diagram of low-pass filtering and thinning processing in the embodiment, FIG. 5 is an explanatory diagram of low-pass filtering and thinning processing and interpolation in the embodiment, and FIG. 6 is a block diagram showing a conventional still image transmission device. Figure 7 is an explanatory diagram of conventional encoding, Figure 8 is a block diagram showing conventional layered encoding and layered decoding, and Figure 9 is conventional layered encoding and layered decoding. FIG. (1) is a microcomputer, (6) is a video memory (frame memory), (12) is a communication processing circuit/interface, (13) is a transmission line, (14) is a communication memory, and (16) is its external RAM. , (17) is its internal RAM, (21), (23) are low-pass filtering/1/2 thinning processing, (27), (34), (41), (43),
(48) are 2/1 interpolation processing, (29) and (36) are subtractive filtering processing, and (33), (47), and (52) are additive filtering processing. ■ Explanation diagram of encoding Diagram explanatory diagram of encoding 8×8 6X16 2X32 Reference low pass 'al wave/interval explanation Figure 4 Low pass 11! Explanation of wave/interval and hli interval Fig. 5 1 Explanation of conventional encoding Fig. 7

Claims (1)

[Scope of Claims] A series-connected multi-stage thinning processing circuit to which an input still image signal is supplied, and a first processing circuit for block encoding a block signal consisting of a predetermined number of pixel signals obtained from the multi-stage thinning processing circuit. an encoding means, a decoding means for block decoding the output of the first encoding means, an interpolation means for interpolating the output of the decoding means, an output of the interpolation means and an output of the multi-stage thinning processing circuit. a multi-stage circuit comprising a difference detection means for detecting a difference between the two, and a second encoding means for block encoding a block signal consisting of a predetermined number of differential pixel signals obtained from the difference detection means; In a still image transmission device in which outputs of first and second encoding means are transmitted sequentially, encoding code tables for block encoding in the first and second encoding means are made to be different from each other. A still image transmission device characterized by: