JP2570788B2 - Decoding device for high efficiency coding of television signals - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-efficiency encoding method for a television signal.

[Summary of the Invention]

The present invention blocks a digital television signal, detects a dynamic range of each block,
In a decoding device of a device for performing high-efficiency encoding of a television signal by utilizing the fact that the dynamic range of each block is smaller than the dynamic range of the entire screen, a decoding operation is performed by a simple change of an arithmetic expression and a multiplier. as well as
This is realized by a simple configuration using a ROM.

[Conventional technology]

As a high-efficiency encoding method for television signals, the present inventors have adopted an adaptive dynamic range encoding method (hereinafter referred to as ADRC).
The method was referred to as “method” (December 11, 1986, The Institute of Electronics, Communication Engineers, MR 86-43).

The ADRC method is an encoding method that uses a strong spatiotemporal correlation of a television signal.

That is, when an image is divided into blocks, each block often has a smaller dynamic range than a local correlation. Therefore, this ADRC method divides the image into blocks, finds the dynamic range of each block, and adaptively re-encodes the pixel data so that each pixel data can be compressed to a smaller number of bits than the original number of bits. ing.

As a method of dividing an image into blocks, division is performed only in a horizontal line direction (one-dimensional ADRC), division by a rectangular region in both horizontal and vertical directions (two-dimensional ADRC), and division considering a spatial region over a plurality of frames (three-dimensional ADRC) ADRC) has been proposed (for example, JP-A-61-144990, JP-A-61-144990).
144989 and JP-A-62-92620).

In three-dimensional ADRC, motion between two frames is detected for each block, and in still blocks, so-called frame dropping is performed without sending data of a subsequent frame, for example, so that more efficient encoding can be performed. However, in this case,
Each block requires a 1-bit motion information code, but in a still area, 1/2 data compression can be performed.

Allocation of the number of bits for each block during re-encoding is as follows:
In addition to the method of changing the quantization step width according to the dynamic range of each block as a constant value smaller than the number of bits of the original pixel data (hereinafter referred to as fixed-length ADRC; see the above-mentioned publication), the dynamic A method of changing the number of bits assigned to each block according to the size of the range (hereinafter referred to as variable length ADRC) has also been proposed (for example, see Japanese Patent Application Laid-Open No. 61-147689).

FIG. 7 shows a configuration example of a variable length ADRC system.

That is, the television signal through the input terminal (1) is supplied to the A / D converter (2), for example, where each pixel is converted into 8-bit digital data. The digital data is supplied to a block dividing circuit (3), and divided into two-dimensional small blocks of, for example, 3 lines × 6 pixels. The data for each block is supplied to a maximum / minimum value detection circuit (4), and the maximum value of the pixel data in each block is obtained.
Find MAX and minimum value MIN.

The data for each block from the block dividing circuit (3) is supplied to the subtracting circuit (6) through the delay circuit (5) corresponding to the delay time in the detecting circuit (4). The subtraction circuit (6) is supplied with the minimum value MIN in the block from the detection circuit (4), and subtracts the minimum value MIN in the block from each pixel data of this block to obtain difference data ΔDATA.
Is obtained. Then, the difference data ΔDATA is supplied to the adaptive encoder (7).

On the other hand, the maximum value MA for each block from the detection circuit (4)
The data of X and the minimum value MIN are supplied to a dynamic range detection circuit (8), and as MAX-MIN = DR, a dynamic range DR in the block is detected, and an allocation bit in the block according to the dynamic range DR is detected. number
Information indicating BITS is formed. Then, the DR and BITS information from the detection circuit (8) is supplied to the encoder (7), and the difference data ΔDATA is converted into data BPL compressed to a smaller number of bits than the original 8 bits. In the variable-length ADRC, this data BPL has the same number of bits in a block, but differs for different blocks according to the dynamic range in the block.

Pixel data in one block is from the minimum value MIN to the maximum value M
It belongs to the dynamic range DR up to AX. The adaptive encoder divides the dynamic DR in the block according to the allocated bit number BITS in the block, sets a code corresponding to each division level range, determines which level range each pixel data belongs to, and determines each pixel data. In contrast, a code corresponding to the level range to which it belongs is set as output data BPL.

As examples of the encoding method in this case, two methods as shown in FIGS. 8 and 9 are proposed depending on which representative level is used as decoded data in each level range at the time of decoding. However, in the examples of both figures, the number of bits of the output data BPL is set to 2 bits for simplicity of description.

In the example of FIG. 8, the dynamic range DR in the block is 2
^BITS = 4 equal divisions, median L0, L of each division level range
1, L2 and L3 are used as values at the time of decoding. With this method, quantization distortion can be reduced. This encoding method is called no edge matching, and is hereinafter abbreviated as NEM.

In the example of FIG. 9, the representative minimum level L0 is the minimum value MIN, and the representative maximum level L3 is the maximum value MAX. That is, in this case, the dynamic range is divided into (2 ^{BITS + 1} -2) = 6, the minimum value MIN is used as a representative level of the division level range on the minimum level side, and the division level on the maximum level side is used. The maximum value MAX is used as the representative level of the range. In the meantime, the division level is divided into two division levels, and the boundary levels between the two division levels are respectively represented by the representative levels L1 and L2.
And

According to this method, the pixel data having the minimum value MIN and the maximum value MAX always exist in one block, and therefore, there is an advantage that the number of encoded codes having an error of 0 can be increased. This encoding method is called edge matching,
Hereinafter, it is abbreviated as EM.

The output data BPL of the encoder (7) is defined by the following equation.

For NEM, For EM, Output data BPL thus obtained (number of allocated bits BITS is constant in the case of a fixed-length ADRC) is transmitted through an output terminal (9 _1). Along with this, the dynamic range DR and the minimum block value MIN in the block is transmitted through an output terminal (9 ₂₎ and (9 _3).

In this case, the additional code to be transmitted in addition to the data BPL may be the dynamic range DR and the maximum value MAX in the block, or the minimum value MIN and the maximum value MAX in the block. The transmitted data BPL is input terminal (11 ₁ ) on the decoding side
To the adaptive decoder (12). The transmitted dynamic range DR in the block is supplied to the adaptive decoder (12) through the input terminal (11 ₃ ) and also to the BITS detection circuit (13), where the allocated bit according to the dynamic range DR in the block is assigned. A number BITS is then obtained and this information BITS is supplied to the adaptive decoder (12).

The transmission block within the minimum value MIN is supplied to the addition circuit (14) through an input terminal (11 _2).

In the adaptive decoder (12), as shown in FIG. 8 and FIG.
The difference data ΔDATA ^* obtained by subtracting the minimum value MIN from each of the representative levels L0, L1, L2, and L3 is obtained, and the difference data ΔDATA ^* is supplied to the adding circuit (14) to obtain the decoded pixel data DATA ^* . Since the decoded pixel data DATA ^* is data for each block, the block is decomposed in the block decomposing circuit (15) to return to the original time-series pixel data, which is converted into the D / A converter (1).
The signal is converted back to an analog signal by 6), and is output to an output terminal (17).

The operation performed by the decoder (12) can be represented by the following equation.

For NEM, For EM, However, when BITS = 0, NEM and EM are the same.

[Problems to be solved by the invention]

In the case of the NEM encoding method, the configuration of the decoder is basically multiplication as understood from the equation (3). Since the denominator 2 ^{BITS + 1} in parentheses is a power of 2, the division in the expression (3) can be realized by a simple digit shift.

However, in the case of the EM coding method, as understood from the expression (4), it is necessary to divide by the number (2 ^BITS -1) after the multiplication, which makes the configuration difficult.

The present invention particularly seeks to provide an EM-compatible decoder having a simple configuration.

[Means for solving the problem]

The decoder device according to the present invention comprises: In performing this operation, a conversion table (22) that stores a value S to be multiplied by the encoded code BPL and outputs an output value S according to the dynamic range DR and the allocated bit number BITS, and a conversion table (22). Value S from 22)
Multiplication means (2
(3) and means (24) for taking the multiplication result from the multiplication means (23) from the higher order (the number of bits of the difference data ΔDATA + 1) bits, rounding off the least significant bit, and decoding the difference data ΔDATA. .

[Action]

The conversion table (22) stores a value S to be multiplied by the encoded code BPL, receives information on the dynamic range DR and the allocated bit number BITS, and receives these values DR, BITS.
Is obtained from this. The multiplication of the value S and the transmitted encoded code BPL is performed by a multiplier (2
3).

Then, from the top of this multiplication result (difference data ΔDATA
+1) bits are taken as an output, the least significant bit is rounded off by means (24), and the difference data Δ
DATA ^* is obtained from this.

〔Example〕

FIG. 1 shows an embodiment of a decoder according to the present invention. In this embodiment, the NEM and EM decoders can be used together. The pixel data is 8 bits, and the number of bits BITS assigned to the encoded code BPL is 0, Variable length ADR that can take 5 ways of 1,2,3,4
This is the case for C.

When the operation definition formula of the decoder at the time of EM is shown again, In this equation (6), the value to be multiplied by the data BPL is S,
This is stored in a ROM or the like in advance and generated. In this way, by multiplying the transmitted data BPL by the value S generated from the ROM, the operation in the parentheses of the equation (6) can be performed.

However, in this case, the operation word length becomes long. Therefore,
In this example, in order to reduce the operation word length, the data BPL is padded with upper bits, and padded upward as shown in FIG. However, when BITS = 0, NEM
And the same operation as

The data BPL packed as shown in Fig. 2 is Can be expressed numerically. If this numerical value is Q, the equation (6) is = RND {Q × T} (7) Since the value Q is obtained by increasing the BPL, the value T may be generated by storing the value T in a ROM or the like.

Here, T in equation (7) is the same as BITS = 0... NEM = DR BITS = 1... 2DR BITS = 2... 4 / 3DR BITS = 3. ... 16 / 15DR, so that the maximum is 2DR, and it is sufficient that the decimal point is 9 bits. On the other hand, it has been found that, in this example, the data BPL has a maximum of 4 bits below the decimal point, and it is sufficient that the data BPL has only 3 bits after the decimal point in a system of 8 bits. Then, when the value T is expressed as shown in FIG. 3 (1) and the value Q is expressed as shown in FIG. 3 (2) and multiplied, the product T × Q is obtained in the form of FIG. 3 (3). . Then, the decoded data DATA ^* is obtained by rounding off the first decimal place of the product and adding it to the minimum value MIN in the block.

 Next, the case of NEM will be described.

The operation definition expression in this case is shown again. (BPL × 2 + 1) of the numerator in the parenthesis of this formula (8)
For example, when the maximum number of allocated bits BITS = 4, (BITS + 1) = 5 bits are padded as shown in FIG.

The value after this justification is Becomes This is equivalent to (BPL × 2 + 1) shifted by 4-BITS digits. Therefore, as shown in FIG. 4, if the most significant position of the data BPL in the upper part is the decimal point position, the value R = (BPL × 2 + 1) to be multiplied by the dynamic range DR in Expression (8). / 2 ^{BITS + 1} .

Therefore, if the value R and the dynamic range DR are multiplied by a multiplier, the calculation in the parentheses in the equation (8) is performed.

Therefore, the difference data ΔDATA can be obtained by taking (number of bits of the difference data ΔDATA + 1) bits from the higher order of the multiplication result and rounding off the least significant bit. The multiplication format at this time can be expressed as shown in FIG. FIG. 5 shows that the dynamic range DR is 8 bits, that is, the difference data ΔDATA is also 8 bits.
This is the case for bits.

Note that the decimal point added in FIGS. 3 and 5 is added for easy understanding, and may be added essentially anywhere.

Fig. 1 shows an example of the configuration of a decoder shared by NEM and EM.
The requantized data BPL (maximum 4 bits) transmitted from the encoder side is transferred to the upper end processing means (2) through the input terminal (11 ₁ ).
Supplied to 1). In addition, information (3 bits) of the allocated bit BITS is supplied to the terminal (1
3 ₀₎ switching signal N of NEM and EM is supplied through
EM / EM is supplied. In the processing means (21), at the time of NEM, as shown in FIG.
Bits are padded, and data BPL is set to “1” one bit below the least significant bit. If there is a space below the 5-bit area, "0" is assigned to that bit.

As described above, the work of (BPL × 2 + 1) at the time of the NEM is shifted to the upper 5 bits, and the value R is obtained. This 5-bit value R is supplied to the multiplier (22).

On the other hand, at the time of EM, as shown in FIG.
(FIG. 3 (2)) is obtained from this.

(22) is a ROM as a conversion table, in which the value T is stored in advance. Together with the information of the dynamic range DR and the terminal (13 ₀₎ the number of allocated bits through BITS through an input terminal (11 ₃₎ is supplied to the ROM (22)
A switching signal NEM / EM between NEM and EM is supplied. At the time of NEM, a dynamic range DR of the form shown in FIG. 3 (1) is obtained, and at the time of EM, the dynamic range DR shown in FIG. 6 (1) is obtained. Is obtained in accordance with the number of allocated bits BITS.

The output of the ROM (22) and the output of the upper padding circuit (21) are supplied to a multiplier (23). Therefore, this multiplier (2
3) In NEM, DR × R described above (see Fig. 5 (3))
Is multiplied by T × Q in EM (see FIG. 3 (3))
Is multiplied. That is, the expressions (8) and (6)
This gives the result of the operation in parentheses in the expression.

The output of the multiplier (23) is as shown in FIG.
Although it is 13 bits, considering the position of the decimal point and rounding off one digit after the decimal point in the subsequent stage, it is sufficient to obtain 8 bits as output data ΔDATA, so that the output of this multiplier (23) is Only the upper 9 bits of

The 9-bit output of the multiplier (23) is supplied to a rounding circuit (24), and one digit after the decimal point is rounded off to obtain 8-bit data, that is, decoded difference data ΔDATA ^* .

8-bit difference data ΔDA from the rounding circuit (24)
TA ^* is supplied to the adder circuit (25), is transmitted, it is added to the block minimum value MIN through the input terminal (11 _2). Accordingly, the adding circuit (25) pixels of the original 8-bit from the data DATA ^{* (block} division is) is obtained, is derived to the output terminal (14 _0).

The registers (101) to (108) are for performing pipeline processing to improve the processing speed, and the number of stages provided therein is determined by the required processing speed and device speed.

Incidentally, a ROM having a size of 4K × 12 is required as the ROM (22) in the example of FIG.

The ROM (22) only needs to output the dynamic range DR as it is at the time of NEM.
NEM / EM does not have to be entered in ROM (22). Therefore, the size of the ROM (22) can be reduced to half.

Considering EM time, when BITS = 0, NEM
ROM (22) is substantially the same as B
It is sufficient to output values corresponding to four types of ITS = 1, 2, 3, and 4. Therefore, the input of BITS to the ROM (22) only needs to be 2 bits, and the size of the ROM (22) is further reduced to half.

FIG. 6 shows an improved example of a decoder for both NEM and EM in consideration of the above.

In this example, the ROM (22) shown in FIG.
(1K × 12) ROM (31) and selector (32)
And a decoder (3) for controlling the ROM (31) and the selector (32).
3) is provided. Others are the same as the example of FIG.

Selector (32) and the dynamic range DR through the input terminal (11 _3), and an output of the ROM (32), selected by the select signal (1 bit) from the control decoder (33).

The ROM (31), 2-bit signal N from the control decoder (33) is supplied with the dynamic range DR from the input end (11 ₃₎ is supplied.

The control decoder (33) switching signal NEM / EM through pin (34) with pin (13 ₀₎ information (3 bits) of the allocated number of bits BITS through is supplied is supplied, the two input signals , The 1-bit select signal and the 2-bit signal N are generated.

The signal N supplied to the ROM (31) is for reassigning BITS in EM. That is, this signal N is BITS = 0.
Except in the case of (2), a 2-bit code is assigned to each of BITS = 1 to 4. Therefore, ROM
(31) outputs a value T corresponding to each BITS when BITS = 1 to 4.

The select signal is BITS = 0 in NEM and EM.
In the case of, select the dynamic range DR from the input terminal (11 ₃ ). When BITS = 1 to 4 in EM, ROM (31)
The selector (32) is controlled so as to select the output of (1).

The control decoder (33) can be constituted by ROM or logic, and in the case of ROM, 1K × 12 can be used. In other words, instead of the 4K × 12 ROM in the example of FIG. 1, 1K in FIG.
Only two × 12 ROMs need to be used, and the size of the ROM can be reduced.

In addition, when BITS = 1 at the time of EM, T = 2DR. This is equivalent to shifting the dynamic range DR by one bit to the higher order. So when BITS = 1 at the time of this EM is to be used to shift the dynamic range DR from the input end (11 ₃₎ to one bit higher. Then, ROM (31)
Is undefined when BITS = 1 in EM, so
The ROM (31) can be further reduced to a size of 640 × 12.

The above is the case of variable length ADRC, but fixed length ADRC
In this case, it goes without saying that the present invention can be applied only when BITS = constant.

Further, the present invention is applicable to an arbitrary block size of a digital television signal.

〔The invention's effect〕

According to the present invention, the term including the division of the operation definition formula is obtained by using the conversion table composed of the ROM as the decoder device for the EM, so that the actual operation can be performed only by multiplication and has a simple configuration. realizable. Further, it can be shared with a NEM decoder device with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a system diagram showing the configuration of one embodiment of the present invention, and FIG.
FIGS. 3 and 3 are diagrams for explaining the operation at the time of EM, FIGS. 4 and 5 are diagrams for explaining the operation at the time of NEM, FIG. 6 is a system diagram of another embodiment of the present invention, FIG. 7 is a block diagram of an example of a high-efficiency encoding device, FIG. 8 is an explanatory diagram of an encoding method NEM, and FIG. 9 is an explanatory diagram of an encoding method EM. (21) is a top-down processing circuit, (22) is a ROM, (23) is a multiplier, and (24) is a rounding circuit.

Claims (1)

(57) [Claims] And calculating a maximum value of a plurality of pixel data included in a predetermined block of the digital television signal and a minimum value of the plurality of pixel data, and subtracting the minimum value from each of the plurality of pixel data. Difference data ΔDATA, and the dynamic range DR of each block is detected from the maximum value and the minimum value, and the difference data ΔDATA is encoded with a smaller number of bits BITS than the original pixel data according to the detected dynamic range. Receiving the encoded code BPL and the additional code from means for transmitting the information of the dynamic range, at least two additional codes of the maximum value and the minimum value, and the encoded code BPL. A device for encoding the original difference data, wherein the method for decoding the encoded code is The calculation means includes a value S to be multiplied by the data BPL in parentheses in the above formula.
Is stored in advance, and the information of the dynamic range DR and the number of allocated bits BITS is received.
A multiplication means for multiplying the value S from the conversion table by the above-mentioned coding code BPL; and a multiplication result of the multiplication means from the higher order (difference data ΔDATA
Means for decoding the difference data ΔDATA ^* by taking the number of bits of the data + 1) and rounding off the least significant bit to decode the differential data ΔDATA ^* .