JPH01194584A - Decoder for high efficiency coding system of television signal - Google Patents

Abstract

PURPOSE:To simplify the constitution of a decoder by enabling a term including the division of a calculation definition formula to be obtained with the aid of a conversion table consisting of an ROM and executing only multiplication as actual calculation. CONSTITUTION:A coding code BPL and a value S which is multiplied are stored in the conversion table 22, the information of a dynamic range DR and allocated bit number BITS are received and the value S corresponding to the values DR and BITS is obtained from them. Then, the value S and the BPL are multiplied by a multiplier 23. The bit of (the bit number of differential data DELTADATA+1) is taken from the high-order of the multiplication result as output, the least significant bit is rounded by a rounding circuit 24 and the differential data DELTADATA' is obtained from it. As the decoding arithmetic operation can be executed by the simple change of the calculation formula and by using the multiplier and the ROM in that way, the decoder can be made to a simple constituted one.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a decoding device using a high efficiency encoding method for television signals.

[Summary of the invention]

This invention blocks digital television signals,
In a decoding device for a device that detects the dynamic range of each block and performs high-efficiency encoding of a television signal by utilizing the fact that the dynamic range of each block is smaller than the dynamic range of the entire screen,
The decoding operation can be performed by simply changing the arithmetic expression, using a multiplier and RO.
This was realized with a simple configuration using M.

[Conventional technology]

The present inventors have developed an adaptive dynamic range coding method (hereinafter referred to as ADR) as a high-efficiency coding method for television signals.
(December 11, 1986)
Address to the Institute of Electronics and Communication Engineers, Japan (MR86-43).

This ADRC method is an encoding method that utilizes the strong spatio-temporal correlation of television signals.

That is, when an image is divided into blocks, each block often has only a small dynamic range due to local correlation. Therefore, in this ADRC method, the image is divided into blocks, the dynamic range of each block is determined, and the pixel data is adaptively re-encoded, so that each pixel data can be compressed to a smaller number of bits than the original number of bits. ing.

Image block division methods include division only in the horizontal line direction (one-dimensional ADRC), division into rectangular areas in both horizontal and vertical directions (two-dimensional ADRC), and division considering spatial areas spanning multiple frames (three-dimensional ADRC). ADR
C) has been proposed (for example, JP-A-61-1449
90, JP-A-61-144989, and JP-A-62-92620).

In three-dimensional ADRC, motion detection between two frames is performed for each block, and even more efficient encoding can be achieved by performing so-called frame dropping for static blocks, for example, without sending data of subsequent frames.

However, in this case, each block requires a 1-bit motion information code, but data can be compressed to 1/2 in the still area.

The allocation of the number of bits for each block during re-encoding ′ζ is
In addition to the method of changing the quantization step width according to the dynamic range of each block as a constant value smaller than the number of bits of the original pixel data (hereinafter referred to as fixed length At) RC; see the above-mentioned publication), A method (hereinafter referred to as variable length ADRC) in which the number of bits allocated to each block is changed depending on the size of the dynamic range of the data has also been proposed (for example, see Japanese Patent Laid-Open No. 147689/1989).

FIG. 7 shows an example of the configuration of a variable length AtJRC system.

That is, the television signal at the input terminal (υ = 1ilL;

This digital data is supplied to a block division circuit (3) and divided into blocks, for example, into two-dimensional small blocks of 3 lines x 6 pixels. The data for each block is supplied to a maximum value/minimum value detection circuit (4) to determine the maximum value MAX and minimum value MIN of the pixel data in each block.

The data for each block from the block division circuit (3) is
In addition, a delay circuit (
5) to the subtraction circuit (6). This subtraction circuit (6) is supplied with the minimum value MIN within the block from the detection circuit (4), and the minimum value MIN within the block is subtracted from each pixel data of this block, resulting in difference data ΔD.
ATA is obtained. The differential data 26 AT is then supplied to the adaptive encoder (7).

On the other hand, the maximum value MA for each block from the detection circuit (4)
The data of Information indicating the number of allocated bits BITS within the block is formed. And l) R and BIT from this detection circuit (8)
The information of S is supplied to the encoder (7), and from this the difference data ΔDATA is compressed into data BPL having a number of bits smaller than the original 8 bits. In variable length ADRC, this data BPL has the same number of bits within a block, but differs depending on the dynamic range within the block if the block is different.

The pixel data within the l block belongs within the dynamic range DR from the minimum value MIN to the maximum value MAX. The adaptive encoder divides the intra-block dynamic DR according to the intra-block allocated bit number BITS, sets a code corresponding to each division level range, determines to which level range each pixel data belongs, and For,
Output data B that corresponds to the level range to which it belongs
PL.

As examples of encoding methods in this case, two methods have been proposed, as shown in FIGS. 8 and 9, depending on which representative level is used as decoded data for each level range during decoding. However, in the examples shown in both figures, the number of bits of the output data BPL is 2 bits because of Mffi in the explanation.

In the example in Figure 8, the intra-block dynamic range DR is 2.
1JITs-4, and the median value of each division level range is set to LO, L1 . L2. L3 is used as a value during decoding. This method can reduce quantization distortion. This encoding method is called no-edge matching, and is hereinafter referred to as NE
It is abbreviated as M.

In the example of FIG. 9, the representative minimum level LO is the minimum value MIN1, and the representative maximum level L3 is the maximum value MAX. In other words, in this case, the dynamic range is (2""+1-
2) = 6 ([1 minute! 1J L, the minimum value MIN as the representative level of the divided level range on the minimum level side
In addition, the maximum value MAX is used as the representative level of the division level range on the side of the maximum level. During that time, the data is divided into two division levels, and the boundary levels between the two division levels are defined as representative levels L1 and L2, respectively.

According to this method, pixel data having the minimum value MIN and maximum value MAX always exists within one block, so
There is an advantage that the number of encoded codes with zero error can be increased. This encoding method is called edge matching, hereinafter abbreviated as EM.

The output data BPL of the encoder (7) is defined by the following equation.

In the case of NEM, in the case of EM, (to fixed length ○ In the case of RC, the number of allocated bits BITS
is constant) The output data BPL obtained in this way is output to the output terminal (91).
transmitted through. At the same time, the intra-block dynamic range DR and the intra-block minimum value MIN are transmitted through output terminals (92) and (93).

In this case, the additional codes to be transmitted in addition to the data BPL are the dynamic range DR and the maximum value in the block MAX.
Or the minimum value within the block MIN and the maximum value within the block MAX
It may be. The transmitted data BPL is supplied to the adaptive decoder (12) through an input terminal (111) on the decoding side. In addition, the transmitted intra-block dynamic range DR is supplied to the adaptive decoder (12) through the input terminal (113) and is also supplied to the BITS detection circuit (12).
3), the number of allocated bits BITS corresponding to the intra-block dynamic range DR is obtained from this, and this information old TS is supplied to the adaptive decoder (12).

Further, the transmitted intra-block minimum value MIN is supplied to the adder circuit (14) through the input terminal (112).

In the adaptive decoder (12), as shown in FIGS. 8 and 9, representative levels LO, L1 . L2. Obtain difference data ΔDATA″′ by subtracting the minimum value MIN from each of L3,
This is supplied to the adder circuit (14), and the decoded pixel data DA
Obtain TA'. Since this decoded pixel data DATA'' is data for each block, the block is decomposed in the block decomposition circuit (15) and returned to the original time-series pixel data, which is converted into analog data by the D/A converter (16). It is converted back into a signal and led out to the output terminal (17).

The calculation performed by the decoder (12) can be expressed as the following equation.

In the case of NEM, however, when BITS=0, it is the same for NEM and EM.

(Problem to be Solved by the Invention) In the case of the NEM encoding method, as understood from equation (3), the decoder configuration is basically multiplication.Then, the denominator in parentheses 2uL1'u Since ÷1 is a power of 2, division in equation (3) can be achieved by simply shifting digits.

However, in the case of the EM encoding method, as can be understood from equation (4), it is necessary to divide by the number (2a'''-t) after multiplication, making the configuration difficult.

In particular, the present invention is intended to provide a simple configuration as an EM (1) compatible decoder.

[Means to solve the problem]

The decoder device according to the present invention stores a value S to be multiplied by the encoded code BPL when performing the following operation, and outputs an output value S according to the dynamic range DR and the allocated number of bits BITS. ) and this conversion table (22
) and the encoded code BPL, and the multiplication result from this multiplication means (23) is calculated from the upper order (number of bits of difference data ΔDATA +
1) means (24) for decoding the difference data ΔDATA by taking bits and rounding off the least significant bit;

(Operation) The conversion table (22) stores the code, the value S to be multiplied by the encoded code BPL, and the above dynamic range DR.
By receiving information on the number of allocated bits and the old TS, a value S corresponding to these values DR and BITS is obtained. Then, this value S is multiplied by the transmitted encoded code BPL in a multiplier (23).

Then, from the top of this multiplication result (difference data ΔDAT
The number of bits of A+1) bits is taken as an output, and the least significant focus is rounded off by means (24), thereby obtaining differential data ΔDATAM.

〔Example〕

FIG. 1 shows an embodiment of a decoder according to the present invention, in which NEM and EM decoders can be used.
Further, the case is 1) RC to a variable length in which the internal element data is 8 bits and the number of allocated bits BITS of the encoded code BPL is 0.1, 2° and 3.4.

Showing the calculation definition formula of the decoder at the time of EM again, this first (
The value to be multiplied by the data BPL in equation 6 is S, and this is stored in a ROM or the like in advance and generated. In this way, by multiplying the transmitted data BPL by the value S generated from this ROM, the calculation in parentheses in equation (6) can be performed.

However, if this continues, the operation word length will become long. Therefore, in this example, in order to reduce the operation word length, the data BPL is padded to the upper bits, as shown in FIG. 2. However, when BITS=0, the same operation as NEM is performed as described later.

'The data BPL that is top-justified as shown in Fig. S2 can be expressed numerically as PL z &IIc. If this value is Q, then equation (6) =
RND (QXT) ---
・(It can be written as 71. Since the value Q is the value obtained by increasing the BPL, it is sufficient to store the value T in a ROM etc. and generate it.

Here, 'r in equation (7) is BITS-0... Same as NEM -L)R old TS=1
... 2DR BITS Mi 2 ... 4/3DR Old TS Da 3 ... 8/7DR BITS = 4 ... 16/15D R, so the maximum is 2L)R, and 9 bits beyond the decimal point Good to have. On the other hand, in this example, the data BPL has a maximum of 4 bits below the decimal point, and in a system where the data is 8 bits, it has been found that 3 bits below the decimal point are sufficient. Therefore,
The value T is expressed as shown in Figure 3 (1), and the value Q is expressed as shown in Figure 3 (2).
When expressed as and multiplied, the product TXQ is shown in the same figure (3
) format. Then, the first decimal point of this product is
By rounding off the decimal place and adding it to the minimum value MIN within the block, decoded data DATA'' is obtained.

Next, the case of NEM will be explained.

To show the calculation definition formula in this case again, (BPLX2+1) of the numerator in the parentheses of this formula (8)
For example, when the maximum allocated bit number BITS=4, it is upper-justified by (BITS+1)-5 bits as shown in FIG.

The value after this upward adjustment is -(BPLX2+1)X2'-day ITS...
・It becomes (9). This is (BPLX2+1) 4-BI
This corresponds to shifting by the TS digit. Therefore, as shown in FIG. 4, if the upper part of this upper-justified data BPL is set as the decimal point position, then in equation (8), the value to be multiplied by the dynamic range DR = R = (B P L
X'l+l)/2HITs+x.

Therefore, by multiplying this value R and the dynamic range DH using a multiplier, the calculation in parentheses in equation (8) is performed.

Therefore, the difference data ΔDATA can be obtained by taking (the number of bits of the difference data ΔDATA + 1) bits from the higher order of the multiplication result as the calculation output and rounding off the lowest focus. The multiplication format at this time can be expressed as shown in FIG. 5 by aligning the decimal point positions. Figure 5 shows that the dynamic range DR is 8 points, that is, the difference data Δ
DATA is also in the case of 8 focus.

Note that the decimal point given in FIGS. 3 and 5 is added to make it easier to understand, and essentially it may be given anywhere.

Figure 1 shows an example of the configuration of a decoder for both NEM and EM, in which requantized data BPL transmitted from the encoder side is
(maximum 4 bits) is supplied to the upper filling processing means (21) through the input terminal (111). This top filling processing means (2
1) also includes the information f4(3) of the allocated bit number BITS.
A bit) is supplied through the terminal (13o) and a switching signal N)! between NEM and EM is supplied through the terminal (13o). M/EM is supplied. In the processing means (21), at the time of NEM, data HPL is upper-justified by 5 bits, and "1" is set one bit below the least significant bit of data BPL, as shown in FIG. If there is a gap further down the 5-bit area, "0" is assigned to that pit.

As described above, (BPLX2+1) in NEM is upper-justified by 5 bits, and the value R is obtained. This 5-bit value R is supplied to a multiplier (22).

On the other hand, at 8M, as shown in FIG. 2, the data BPL is shifted upward by the maximum allocated bit number BITS=4 bits, and the value Q ((2) in FIG. 3) is obtained from this.

(22) is a ROM serving as a conversion table, in which the value T is stored in advance. This ROM (22) is supplied with information on the dynamic range DR through the input terminal (l13) and the number of allocated bits BITS through the terminal (13o), as well as the switching signal NEM/EM between NEM and EM.
EM is supplied, and during NEM, the dynamic range DR in the format shown in Figure 3 (1) is obtained from this, and during EM, the dynamic range DR in the format shown in Figure 6 (1) is obtained according to the allocated bit number BITS in the format shown in Figure 6 (1). The value T is obtained.

The output of the ROM (22) and the output of the upper filling circuit (21) are supplied to a multiplier (23). Therefore, in this multiplier (23), at the time of NEM, 1) RXR (fifth
(see Figure (3))), and at the time of EM, 'rXQ(
The multiplication shown in FIG. 3 (see 3) is performed. That is, the first (
The calculation results in parentheses in equations 8) and 6 can be obtained from this.

The output of this multiplier (23) is 13 bits as shown in Figure 5 (3), but considering the decimal point position, one digit after the decimal point is rounded off at the subsequent stage to obtain 8 bits as the output data ΔDATA. Therefore, only the upper 9 bits of the 13 bits are obtained as the output of this multiplier (23).

The 9-bit output of this multiplier (23) is rounded to
is supplied to 8-bit data with one decimal place rounded off, that is, decoded difference data ΔDAT.
A″′ is obtained from this.

8-bit difference data ΔD from this rounding circuit (24)
ATA' is fed to the adder circuit (25), transmitted and summed with the intra-block minimum value MIN through the input terminal <112). Therefore, the original 8-bit pixel data DATAM (divided into blocks) is obtained from this adder circuit (25) and is led out to the output terminal (14o).

Note that (101) to (108) are registers, which are used for pipeline processing to improve processing speed, and the number of internal stages to be provided is determined by the required processing speed and device speed.

By the way, the ROM (22) in the example of Fig. 1 is 4K.
A ROM with a size of X12 is required.

ROM (22) is dynamic range DR when NEM
You just need to output it as is, so if you use a selector,
The switching signal NEW/HM does not need to be input to the ROM (22), so the size of the ROM (22) can be reduced to 1/2.
can be reduced to

Also, considering the EM time, when BITS = 0, the same operation as NEM is required, so ROM (22
) should essentially output values corresponding to the four types of BITS = 1.2.3.4, so RUM(22)
The BITS input to the RO only needs to be 2 bits.
The scale of M(22) is further reduced to 1/2.

Figure 6 shows the NEM when the above considerations are taken into consideration.

This is an example of an improved EM decoder.

In this example, instead of the ROM (22) in the example in Figure 1, a ROM (31) of 1/4 the size (lKX12), a selector (32), a ROM (31) and a selector (32
) is provided with a control decoder (33). The rest is the same as the example in FIG.

The selector (32) selects the dynamic range DR through the input terminal (113) and the output of the ROM (32) using a select signal (l bit) from the control decoder (33).

)<OM (31) is supplied with the dynamic range DR from the input terminal (113) and also supplied with the 2-bit signal N from the control decoder (33).

The control decoder (33) is supplied with information (3 bits) about the number of allocated bits BITS through the terminal (13o), and is also supplied with the switching signal NEM/EM through the terminal (34), and receives the information from these two input signals. The 1-bit select signal and 2-bit signal N are generated.

The signal N supplied to the ROM (31>) is the BITS during EM.
This is to reallocate the . That is, this signal N has a 2-bit code assigned to each of BITS-1 to BITS-4, except when BITS=0. Therefore, the ROM (31) is BITS-1 to BITS-4.
At this time, a value r corresponding to each BITS is output.

The select signal is BIT at NEM and EM.
When S-0, select the dynamic range DR from the input terminal (113), and when EM, when BITS = 1 to 4, select the selector (32) to select the output of the ROM (31). It is something to control.

The control decoder (33) can be composed of ROM or logic, and in the case of ROM, IKX12 can be used. That is, in place of the 4K×12 ROM in the example of FIG. 1, only 211&l of IKX12 ROMs are used in FIG. 6, and the scale of the ROM can be reduced.

In addition, when BITS=1 during EM, “r −2D
It is H. This is equivalent to the dynamic range DR shifted by 1 bit upwards. So at this EM time, BI
When TS=1, the dynamic range DR from the input terminal (113) is shifted one bit higher and used. Then, the ROM (31) is the BITS at the time of EM.
= 1, it can be indefinite, so ROM(3
1) can be further reduced to a scale of 640×12.

Note that the above is for variable length ADRC, but fixed length A
Needless to say, in the case of DRC, this invention can be applied just by keeping BITS=constant.

Furthermore, the present invention is applicable to any block size of digital television signals.

(Effects of the Invention) According to the present invention, as a decoder device for EM, terms including division in the calculation definition expression are obtained using a conversion table made of ROM, so that the only practical calculation is multiplication. It can be realized with a simple configuration. Also, it can be shared with a decoder device for NEM with a simple configuration.

[Brief explanation of the drawing]

ff11 is a system diagram showing the configuration of an embodiment of this invention,
Figures 2 and 3 are diagrams for explaining the operation during EM,
4 and 5 are diagrams for explaining the NEM mode, FIG. 6 is a system diagram of another embodiment of the present invention, FIG. 7 is a block diagram of an example of a high efficiency encoding device, and FIG. The figure shows encoding method N.
FIG. 9 is an explanatory diagram of the encoding method EM. (21) is an upper filling processing circuit, and (22) is a ROM. (23) is a multiplier, and (24) is a rounding circuit.

Claims (1)

[Claims] The maximum value of a plurality of pixel data included in a predetermined block of a digital television signal and the minimum value of the plurality of pixel data are determined, and the minimum value is subtracted from each of the plurality of pixel data. to obtain difference data ΔDATA, detect the dynamic range DR for each block from the maximum value and minimum value, and convert the difference data ΔDATA to the number of bits B smaller than the original pixel data according to the detected dynamic range.
The encoded code BPL and the encoded code BPL are encoded by the ITS and transmitted from the means for transmitting the dynamic range information, at least two additional codes among the maximum value and the minimum value, and the encoded code BPL. The apparatus receives the code and decodes the original difference data, and the encoding method of the encoded code is ΔDATA^*=RND{(DR×BPL)/(2^B
^I^T^S-1)}, the calculation means stores in advance the value S to be multiplied by the data BPL in the parentheses of the above calculation formula, and calculates the dynamic range DR and the allocated bits. After receiving information from several BITS,
A conversion table that outputs the value S corresponding to these, a multiplication means that multiplies the value S from this conversion table and the encoded code BPL, and a multiplication result of this multiplication means from the upper order (difference data
A decoding device using a high-efficiency encoding system for television signals, comprising means for decoding the difference data ΔDATA^* by taking the number of bits of TA+1) and rounding off the least significant bit.