JPH0786889A - Pulse signal generating circuit - Google Patents

Abstract

PURPOSE:To provide a pulse signal generating circuit which decreases the total number of its gates and secures a stable operation without using any delay circuit. CONSTITUTION:A clock signal selecting circuit 1 selects one of both clock signals CLK1 and CLK2 of different cycles and supplis it to a dividing circuit 2. The circuit 2 divides the received clock signal into different cycles. An external trigger signal TRG is supplied to a set terminal S1 of a 1st flip-flop circuit 3. The outputs P1 and P2 of the 1st and 2nd flip-flop circuits 3 and 4 are supplied to the circuit 1, and the clock signals are switched synchronously with inversion of both outputs P1 and P2. Thus it is possible to continuously send the pulse signal outputs P1 and P2 synchronizing with different signals CLK1 and CLK2 respectively only by a single pulse.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse signal generating circuit for continuously outputting two pulse signals each having a different pulse width in synchronization with a clock signal having two different periods by an external trigger signal. It is a thing.

[0002]

2. Description of the Related Art Conventionally, an external trigger signal has been used.
Pulse synchronized with two different clock signals
Two pulse signals with different widths are continuously output for one pulse
As a pulse signal generating circuit for inputting, as shown in FIG.
There is This pulse signal generation circuit is
The signal TRG is set by the first flip-flop circuit 3.
Terminal S₁Input to and output P₁Becomes H level,
2 with different periods input to the lock signal selection circuit 1
Two clock signals CLK₁, CLK₂Out of the clock signal
No. CLK₁Is output to the counter 6, and the counter 6
At clock signal CLK₁The number of pulses of a given cow
Count until reaching the number of₁Inside is first
Output P of the flip-flop circuit 3 of₁Is kept at H level
And the output P of the second flip-flop circuit 4₂
Is held at the L level (see FIG. 6), and the counter 6 sets a predetermined level.
The number of pulses is counted and the period T₁When is finished, the first
Flip Flip circuit 3 is reset and output P₁To L
2nd flip-flop with switching to level
Set path 4 and output P₂To H level, and
The clock signal selected by the clock signal selection circuit 1.
The clock signal CLK₂Switch to and coun
The counter 6 and reset the clock signal in the counter 6 again.
No. CLK₂Count the number of pulses until reaching a predetermined number
And then that period T ₂The inside of the first flip-flop circuit 3
Output P₁Is held at L level and second flip
Output P of flop circuit 4₂Is maintained at H level (see Fig. 6).
), Count the predetermined number of pulses with the counter 6 and
Period T₂After finishing, the second flip-flop circuit 4
Reset and output P₂By switching to L level
So, two pulse signals with different pulse widths are one pulse
Output continuously.

[0003]

In the above-mentioned conventional configuration, the counter 6 needs to be reset when the period T ₁ is switched to the period T ₂ , but the second flip-flop is reset before the counter 6 is reset. When the circuit 4 is set and the output P ₂ becomes H level, the second flip-flop circuit 4 is also reset by the subsequent reset of the counter 6, and a predetermined stable output P ₂ is obtained. There is a problem that there is no.

With respect to the above problem, in the conventional example shown in FIG. 5, the counter 6 to the second flip-flop circuit 4 are connected.
The set signal output to the set terminal S ₂ of the delay circuit 7
By delaying with, the timing at which the second flip-flop circuit 4 is set is delayed so that the second flip-flop circuit 4 is set after the counter 6 is reliably reset.

However, the plurality of delay elements constituting the delay circuit 7 require a large number of delay elements because the delay time is not so accurate, which significantly increases the number of gates in the entire pulse signal generating circuit. However, there is a problem that the chip size becomes large and cost is increased even when integrated into an IC. The present invention has been made in view of the above problems, and an object of the present invention is to provide a pulse signal generation circuit that does not require a delay circuit, reduces the number of gates in the entire circuit, and can perform stable operation.

[0006]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides only one pulse of two pulse signals having different pulse widths which are respectively synchronized with clock signals of two different periods by an external trigger signal. In a pulse signal generation circuit that outputs continuously, a clock signal selection unit that selects and outputs one of two clock signals having different periods by an external trigger signal, and the selected clock signal in a plurality of different periods stepwise. A frequency dividing circuit for dividing, a first flip-flop circuit in which a clock signal divided by the frequency dividing circuit is input to a reset terminal and an external trigger signal is input to a set terminal, and the first flip-flop circuit The frequency-divided clock signal input to the reset terminal of the first flip-flop circuit is input to the set terminal and frequency-divided by the frequency dividing circuit. A second flip-flop circuit to which a clock signal having a cycle shorter than that of the clock signal input to the reset terminal of the second flip-flop circuit is input to the reset terminal, and is output from the first and second flip-flop circuits. It is characterized in that the signal is taken out, and the clock signal selection unit switches the clock signal in synchronization with the inversion of the output of the first flip-flop circuit and the output of the second flip-flop circuit.

[0007]

According to the structure of the present invention, in the pulse signal generating circuit for continuously outputting one pulse of two pulse signals each having a different pulse width in synchronization with the clock signal of two different cycles by the trigger signal from the outside, A clock signal selection unit that selects and outputs one of two clock signals having different periods by a trigger signal, a frequency dividing circuit that frequency-divides the selected clock signal into a plurality of different periods, and the frequency dividing circuit. A first flip-flop circuit in which a clock signal divided by is input to a reset terminal and an external trigger signal is input in a set terminal, and a divided clock input to a reset terminal of the first flip-flop circuit A clock signal input to the set terminal, divided by the frequency divider circuit, and input to the reset terminal of the first flip-flop circuit. A second flip-flop circuit to which a clock signal having a shorter cycle that is divided in the preceding stage is input to the reset terminal, and output signals are taken out from the first and second flip-flop circuits, and the clock signal selection unit is provided. Since the clock signal is switched in synchronization with the inversion of the output of the first flip-flop circuit and the output of the second flip-flop circuit, the first flip-flop circuit is input after the external trigger signal is input. The pulse signal output from the first flip-flop circuit and the divided clock signal are input to the reset terminal of the first flip-flop circuit until the divided clock signal is input to the reset terminal of the first flip-flop circuit. Then, the output of the first flip-flop circuit and the output of the second flip-flop circuit are inverted, and then the second flip-flop circuit is inverted. The pulse output from the second flip-flop circuit in the period until the clock signal divided in the preceding stage of the divided clock signal is input to the reset terminal of the first flip-flop circuit in the flip-flop circuit. With signals, you can form continuous pulse signals with different pulse widths without using a counter,
Since the counter is not used, a delay element for timing adjustment accompanying the resetting of the counter is unnecessary, and the number of gates of the circuit can be reduced, which enables stable operation.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic block diagram of a pulse signal generation circuit of this embodiment. As shown in FIG. 1, the pulse signal generation circuit of the present embodiment includes a clock signal selection circuit 1,
It is composed of a frequency dividing circuit 2, a first flip-flop circuit 3 and a second flip-flop circuit 4.

Two clock signals CLK ₁ and CLK ₂ having different cycles are input to the clock signal selection circuit 1, and the clock signal CLK selected by the clock signal selection circuit 1 is input to the frequency dividing circuit 2. It Frequency divider 2
As shown in the time chart of FIG. 2B, the input clock signal CLK is divided into a plurality of different cycles (7 steps in this embodiment), and each step is performed as shown in FIG. Clock signal output OUT _{1 to} OUT ₇ divided for each frequency
Can be taken out.

Further, a trigger signal TRG from the outside is inputted to the set terminal S ₁ of the first flip-flop circuit 3, and a clock signal output OUT ₇ divided by the divider circuit 2 is inputted to the reset terminal R _1. Is entered. On the other hand, the second flip-flop circuit 4 receives the clock signal output OUT ₇ input to the reset terminal R ₁ of the first flip-flop circuit 3 at its set terminal S ₂ and
The clock signal output OUT ₇ short clock signals output OUT ₃ periodicity than the clock signal output OUT ₇ is divided by the previous stage than is input to the reset terminal R _2. Furthermore, the outputs P ₁ and P _{2 of} the first and second flip-flop circuits 3 and 4 are both input to the clock signal selection circuit 1, and the clock signal CLK selected by the _two outputs P ₁ and P ₂ is It can be switched.

FIG. 3 shows a circuit configuration diagram of a specific circuit of this embodiment, and the circuit operation will be described with reference to the time chart of FIG. First, as shown in FIG. 4, the clock signal is not output from the clock signal selection circuit 1 until the trigger signal TRG is input, and the outputs P ₁ and P ₂ are at L level. Here, when the trigger signal TRG is input from the outside and goes to H level, the set input S _{1 of} the first flip-flop circuit 3 also goes to H level and the output P ₁ switches to H level. At this time, the D flip-flops 5 _{1 to} 5 ₈ forming the frequency dividing circuit 2 are also reset. Output P
_{When 1} becomes H level, the clock signal CLK ₁ is selected in the clock signal selection circuit 1 and the clock signal CLK ₁
Is output as. At the same time, the D flip-flops 5 _{1 to} 5 ₈ forming the frequency dividing circuit 2 start operating.

Then, when the clock pulse of the clock signal CLK (ie, the clock signal CLK ₁ ) rises to the (7-1) th power of 2 from the first rise, that is, the 2nd to the 6th clock pulse, the D flip-flop of the seventh stage 5 ₇ of the clock signal output OUT ₇ is the output P ₁ and switched to H level to L level. At this time, the clock signal outputs OUT _{1 to} OUT ₆ of the D flip-flops 5 _{1 to} 5 _{6 in} the sixth stage and before are the D flip-flops 5 in the seventh stage.
Conversely it falls to L level of the clock signal output OUT ₇ of ₇ (see Figure 2 (b)).

Here, the third-stage D flip-flop 5 ₃
The clock signal output OUT ₃ are reset terminal R ₂ and the clock signal selection circuit 1 of the second flip-flop circuit 4
Further, the clock signal output OUT ₇ of the D flip-flop 5 _{7 in} the seventh stage is input to the set terminal S ₂ of the second flip-flop circuit 4. Therefore, when the output P ₁ is switched to the L level, the output P ₂ is switched to the H level, and the clock signal CLK selected by the clock signal selection circuit 1 is also switched to the clock signal CLK ₂ .

Next, the clock signal CLK is applied to the frequency dividing circuit 2.
₂ is input, and the clock pulse of the clock signal CLK (that is, the clock signal CLK ₂ ) is at the (3-1) th power of 2 from the first rise, that is, at the rise of the 2nd power clock pulse, the D flip-flop of the third stage 5 ₃
When the clock signal output OUT ₃ is switched to the H level, the output P ₁ is switched to the L level. When the outputs P ₁ and P ₂ both become L level, the clock signal is not output from the clock signal selection circuit 1 and the operation of the pulse signal generation circuit is stopped.

In the above configuration, during the period from the input of the trigger signal TRG to the switching of the clock signal output OUT ₇ of the seventh-stage D flip-flop 5 _{7 to} the H level by the clock signal CLK ₁ , the output P ₁ When only the output becomes H level and the output P ₁ switches to L level,
The clock signal CLK input to the frequency dividing circuit ₂ is switched to the clock signal CLK ₂ and the output P ₂ becomes H level, and the clock signal CLK ₂ causes the clock signal output OUT ₃ of the third-stage D flip-flop 5 ₃ to be output. Only the output P ₂ is at H level during the period until switching to H level. When the output P ₂ becomes L level, the output of the clock signal from the clock signal selection circuit 1 is stopped. That is, the outputs P ₁ and P ₂ having different pulse widths can be continuously output one pulse at a time according to the trigger signal TRG.

The cycles of the outputs P ₁ and P ₂ are set to the set terminals S ₁ and S _{1 of} the first and second flip-flop circuits 3 and 4, respectively.
It can be appropriately selected according to the clock signal outputs OUT _{1 to} OUT ₇ of the D flip-flops 5 _{1 to} 5 ₈ forming the frequency dividing circuit 2 input to S ₂ and the reset terminals R ₁ and R ₂ .

[0017]

As described above, the present invention provides a pulse signal generating circuit for continuously outputting one pulse of two pulse signals each having a different pulse width in synchronization with a clock signal having two different periods by an external trigger signal. A clock signal selection unit that selects and outputs one of two clock signals having different periods by a trigger signal, a frequency dividing circuit that frequency-divides the selected clock signal into a plurality of different periods, and the frequency dividing circuit. A first flip-flop circuit in which a clock signal divided by is input to a reset terminal and an external trigger signal is input in a set terminal, and a divided clock input to a reset terminal of the first flip-flop circuit A clock signal whose signal is input to the set terminal, which is frequency-divided by the frequency dividing circuit and which is input to the reset terminal of the first flip-flop circuit. A second flip-flop circuit to which a clock signal having a short cycle divided in the preceding stage is inputted to the reset terminal, and output signals are taken out from the first and second flip-flop circuits, and the clock signal selecting unit is provided. Since the clock signal is switched in synchronization with the inversion of the output of the first flip-flop circuit and the output of the second flip-flop circuit, the first flip-flop circuit is input after an external trigger signal is input. The pulse signal output from the first flip-flop circuit and the divided clock signal are input to the reset terminal of the first flip-flop circuit until the divided clock signal is input to the reset terminal of the first flip-flop circuit. Then, the output of the first flip-flop circuit and the output of the second flip-flop circuit are inverted and then the second flip-flop circuit is inverted. Pulse signal output from the second flip-flop circuit in the period until the clock signal divided by the preceding stage of the divided clock signal is input to the reset terminal of the first flip-flop circuit With, it is possible to form continuous pulse signals with different pulse widths without using a counter,
Since the counter is not used, the delay element for timing adjustment accompanying the resetting of the counter is unnecessary, and the number of gates of the circuit can be reduced, and stable operation is possible. Furthermore, by reducing the number of gates, there is an effect that the degree of integration can be increased and the chip size can be reduced and the cost can be reduced even in the case of IC.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing an embodiment.

2A and 2B show the above-described frequency dividing circuit, FIG. 2A is a block diagram, and FIG. 2B is a time chart showing the operation of the frequency dividing circuit.

FIG. 3 is a circuit configuration diagram showing an example of a specific circuit of the above.

FIG. 4 is a time chart showing the same operation.

FIG. 5 is a schematic block diagram showing a conventional example.

FIG. 6 is a time chart showing the same operation as above.

[Explanation of symbols]

1 clock signal selection circuit 2 frequency divider circuit 3 first flip-flop circuit 4 second flip-flop circuit TRG trigger signal P ₁ , P ₂ output CLK ₁ , CLK ₂ clock signal S ₁ , S ₂ first and second Flip-flop circuit set terminals R ₁ and R ₂ First and second flip-flop circuit reset terminals

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[Procedure amendment]

[Submission date] January 17, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction content]

Next, the clock signal CLK is applied to the frequency dividing circuit 2.
₂ is input, and the clock pulse of the clock signal CLK (that is, the clock signal CLK ₂ ) is at the (3-1) th power of 2 from the first rise, that is, at the rise of the 2nd power clock pulse, the D flip-flop of the third stage 5 ₃
When the clock signal output OUT _{3 of} is switched to H level
The output P ₂ switches to L level. When the outputs P ₁ and P ₂ both become L level, the clock signal is not output from the clock signal selection circuit 1 and the operation of the pulse signal generation circuit is stopped.

Claims (1)

[Claims] 1. A pulse signal generation circuit for continuously outputting one pulse of two pulse signals each having a different pulse width in synchronization with a clock signal of two different cycles by an external trigger signal, and a cycle of the external trigger signal. Of the two clock signals different from each other and outputting the selected clock signal, a frequency dividing circuit for stepwise dividing the selected clock signal into a plurality of different periods, and a frequency dividing circuit for dividing the frequency of the selected clock signal. A first flip-flop circuit having a clock signal input to a reset terminal and an external trigger signal input to a set terminal, and a divided clock signal input to a reset terminal of the first flip-flop circuit being a set terminal To the reset terminal of the first flip-flop circuit after being input to A second flip-flop circuit to which a divided clock signal having a short cycle is input to a reset terminal, and output signals are taken out from the first and second flip-flop circuits. A pulse signal generation circuit which switches a clock signal in synchronization with the inversion of an output of a flip-flop circuit and an output of a second flip-flop circuit.