JP2003241847A - Synchronous circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a synchronous circuit capable of reducing an instantaneous peak current. <P>SOLUTION: In the synchronous circuit that operates in synchronization with a clock signal, at least two clock signals whose operation timings differ each other are generated, and each generated clock signal is supplied to each of a grouped flip-flop circuits. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the technical field of reducing the instantaneous peak current of synchronous circuits that operate simultaneously in synchronization with the same clock signal.

[0002]

2. Description of the Related Art Generally, a synchronous circuit is designed so that the timings of clock signals supplied to the respective flip-flops are matched and all the flip-flops operate simultaneously.

FIG. 2 is a configuration circuit diagram of an example of a conventional synchronizing circuit. The synchronizing circuit 30 shown in the figure includes first, second and third flip-flop groups 14, 16 and 18 respectively arranged on the left side, the central part and the right side in the figure, the first flip-flop group 14 and the first flip-flop group 14. 2 flip-flop groups 16
A first logic (combinational circuit) 20 disposed between
And a second logic 22 arranged between the second flip-flop group 16 and the third flip-flop group 18.

Here, the signal output from the output terminal Q of each flip-flop of the first flip-flop group 14 is input to the first logic 20, and the signal output from the first logic 20 is the second. Data input terminal D of each flip-flop of the flip-flop group 16 of
Has been entered in. Similarly, the signal output from the second flip-flop group 16 is input to the second logic 22 and the signal output from the second logic 22 is input to the third flip-flop group 18.

The same clock signal Clock is commonly supplied to the clock input terminals of all the flip-flops included in each of the first, second and third flip-flop groups 14, 16 and 18. .

In this synchronizing circuit 30, the clock signal Cl
The first flip-flop group 14 operates in synchronization with the rise of ock. After that, the first logic 20 operates according to the signal output from each flip-flop of the first flip-flop group 14, and the signal output from the first logic 20 is the next clock signal Cloc.
The second flip-flop group 16 in synchronization with the rise of k
Held in their respective flip-flops.

The operation when the output signal of the second logic 22 is determined and this output signal is held in the third flip-flop group 18 is also the same.

[0008]

By the way, the flip-flop consumes current at the moment it operates. Therefore, in the conventional synchronous circuit 30, all the flip-flops in the circuit operate simultaneously, which causes a problem that an instantaneous peak current becomes extremely large.

It is an object of the present invention to provide a synchronous circuit which can solve the problems based on the prior art and reduce the instantaneous peak current.

[0010]

In order to achieve the above object, the present invention provides a clock generation circuit for generating at least two clock signals whose operation timings are shifted in a synchronous circuit which operates in synchronization with a clock signal. The present invention provides a synchronizing circuit, characterized in that each clock signal generated by the clock generating circuit is supplied to the grouped flip-flop group.

Further, according to the present invention, in a circuit in which a group of flip-flops and a combinational circuit are alternately connected, a clock generating circuit for generating at least two clock signals whose operation timings are shifted is provided, and the clock generating circuit generates the clock signals. A circuit is provided, in which the respective clock signals are grouped into the flip-flops forming the flip-flop group and are supplied to the respective grouped flip-flops.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION The synchronous circuit of the present invention will be described below in detail with reference to the preferred embodiments shown in the accompanying drawings.

FIG. 1 is a schematic circuit diagram of an embodiment of the synchronizing circuit of the present invention. The synchronizing circuit 10 shown in the figure is obtained by applying the present invention to the conventional synchronizing circuit 30 so that the synchronizing circuit 10 shown in FIG. 2 can be easily compared with the conventional synchronizing circuit 30. 30 further includes a clock generation circuit 12 that generates a clock signal whose operation timing is shifted and is supplied to the flip-flop group of each group.

That is, the synchronous circuit 10 of the illustrated example is composed of first, second and third flip-flop groups 14, 16 and 18 respectively arranged on the left side, the central part and the right side in the figure.
A first logic (combinational circuit) 20 arranged between the first flip-flop group 14 and the second flip-flop group 16; the second flip-flop group 16;
The second logic 22 arranged between the flip-flop group 18 and the clock generation circuit 12 described above.

Here, the clock generation circuit 12 generates a plurality of clock signals (multiphase clocks) whose operation timings are shifted from the original clock signal Clock. In the case of the present embodiment, the clock signal Clock is delayed by a time corresponding to the delay time of the delay element 24 to generate the clock signal Clock2, and further, the clock signal Clock.
ck2 is delayed by a time corresponding to the delay time of the delay element 26 to generate the clock signal Clock3.

Further, in this embodiment, the three flip-flops on the lower side in the figure are the flip-flop group of the first group, and the three flip-flops at the center are the flip-flop group of the second group and the flip-flop group on the upper side. These three flip-flops are set as a third group of flip-flops. The first, second and third flip-flop groups have clock signals Clock, Clock2 and Clock2 respectively.
Clock3 is supplied.

The concrete configuration of the clock generation circuit 12 is not limited at all, and any circuit configuration can be used as long as it can generate at least two clock signals with different operation timings. Good. Further, the number of clock signals generated by the clock generation circuit 12, grouping of flip-flops, which clock signal is supplied to which group of flip-flops, and the like may be appropriately determined.

In the synchronous circuit 10 of the illustrated example, the flip-flop group of the first group operates in synchronization with the rising of the clock signal Clock. Next, after a time corresponding to the delay time of the delay element 24, the flip-flop group of the second group operates in synchronization with the rise of the clock signal Clock2, and a time corresponding to the delay time of the delay element 26. , The flip-flop group of the third group operates in synchronization with the rising of the clock signal Clock3.

As described above, in the synchronizing circuit 10 of the present invention,
Not all flip-flops work simultaneously,
Since the plurality of groups are operated while being shifted stepwise, there is an advantage that the peak current does not momentarily increase.

In the synchronizing circuit 10, the first logic 20 operates according to the signal output from the first flip-flop group 14. Where the first logic 2
The value of the output signal of 0 is determined when the output signal of the flip-flop of the third group in the first flip-flop group 14 which operates in synchronization with the rising edge of the clock signal Clock3 having the latest operation timing. Once confirmed,
This is after the time corresponding to the output delay time of the first logic 20 has elapsed.

Therefore, the second operation is performed in synchronization with the rising edge of the clock signal Clock having the earliest operation timing.
Of the third group of flip-flops 16 of the first group of flip-flops 16 which operates in synchronization with the rising edge of the clock signal Clock3 having the latest operation timing. First logic 2 that is determined after the output signal is determined
It is necessary to design the output signal of 0 so that the setup time is satisfied.

However, due to the recent progress of the manufacturing process, the output delay time of the first and second logic parts 20 and 22 is extremely short, so that the design time is designed to satisfy the flip-flop setup time. In the case of a plurality of clock signals having the same period, the phase difference between the clock signal that rises earliest and the clock signal that rises latest must be within the period.

Some flip-flops operate in synchronization with the falling edge of the clock signal. In this case, however, the phase difference between the earliest falling clock signal and the latest falling clock signal. Must be within the cycle.

Further, in the type in which the flip-flop operates in synchronization with the rise and fall of the clock signal, the phase difference between the clock signal which rises earliest and the clock signal which rises latest falls from the rise of the clock signal to the fall. It is necessary to be within the time from the falling edge to the rising edge of the clock signal and the phase difference between the clock signal which falls earliest and the clock signal which falls the latest.

The operation when the output signal of the first logic 20 is determined and this output signal is held in the second flip-flop group 16 and the output signal of the second logic 22 are determined, The operation when this output signal is held in the third flip-flop group 18 is similar.

In the illustrated example, the flip-flops included in the first flip-flop group are divided into three groups, and the flip-flops included in the second and third flip-flop groups are also divided into three groups. , The corresponding flip-flops of the first, second, and third flip-flop groups are grouped together, but the present invention is not limited to this, and may be divided into any number of groups. You can go any way you want.

The synchronizing circuit of the present invention is basically as described above. Although the synchronous circuit of the present invention has been described above in detail, the present invention is not limited to the above-described embodiments, and it goes without saying that various improvements and modifications may be made without departing from the spirit of the present invention. .

[0028]

As described in detail above, the synchronous circuit of the present invention generates and generates at least two clock signals whose operation timings are shifted in the synchronous circuit which operates in synchronization with the clock signal. The clock signal of is supplied to the group of flip-flops of each group. As a result, according to the synchronization circuit of the present invention, not all flip-flops operate simultaneously, but the flip-flops operate in a stepwise manner for each group, so that the peak current does not momentarily increase. is there.

[Brief description of drawings]

FIG. 1 is a configuration circuit diagram of an embodiment of a synchronizing circuit of the present invention.

FIG. 2 is a configuration circuit diagram of an example of a conventional synchronization circuit.

[Explanation of symbols]

10,30 Synchronous circuit 12 clock generation circuit 14, 16, 18 flip-flops 20,22 logic 24,26 Delay element

Claims (2)

[Claims] 1. A synchronous circuit that operates in synchronization with a clock signal, comprising a clock generation circuit that generates at least two clock signals whose operation timings are shifted, and each clock signal generated by the clock generation circuit is: A synchronous circuit characterized by supplying to each group of flip-flops divided into groups. 2. A circuit in which a flip-flop group and a combinational circuit are alternately connected, comprising a clock generation circuit for generating at least two clock signals whose operation timings are shifted, and each clock generated by the clock generation circuit. A circuit characterized in that a signal is supplied to the flip-flops of each of the grouped flip-flops which are included in the flip-flop group.