JPH0583089A - Oscillation circuit - Google Patents

Abstract

PURPOSE:To obtain odd number harmonic frequency signals with respect to a fundamental oscillating frequency in a clear waveform and to prevent the power consumption from being changed in this case by applying logic arithmetic operation to a waveform symmetrical in both polarities through the use of a differential input and differential output stage. CONSTITUTION:Circuits 4-1, 4-2, 4-3 are formed to be differential input and differential output and a usual output and a reflected output are fed respectively to logic arithmetic operation circuits 7-1, 7-2, 7-3 as to an output signal waveform of each circuit stage. Then outputs of the circuits 7-1, 7-2, 7-3 are fed to a synthesis circuit 8 and its output is extracted at a terminal 3 as the output of the oscillation circuit. Since the output waveform of each circuit stage is identical and only each phase differs, the oscillation circuit is easily formed and the output of the oscillation circuit represents the odd number of multiple of the original waveform.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit in which a plurality of delay circuits are cascade-connected to oscillate a pulse output of higher frequency.

Conventionally, a pulse oscillator called a ring oscillator is known, but it has a drawback that power consumption increases when the oscillation frequency is increased without changing the circuit configuration. It was required to develop a technology to solve that point.

[0003]

2. Description of the Related Art A ring oscillator in which a plurality of delay circuits are connected in cascade is known as shown in FIGS. In FIG. 4, 1-1, 1-2, and 1-3 are inverters, which are cascaded in three stages in FIG. The oscillation output is obtained from the terminal 3 by feeding back the output of the final stage inverter 1-3 to the input terminal of the first stage inverter 1-1 through the feedback path 2.

In FIG. 5, reference numerals 4-1, 4-2, and 4-3 are differential input / differential output amplifiers, and two differential input terminals are connected to each other. Therefore, there are two return routes, 5 and 6. The oscillation output is obtained from terminal 3.

In FIGS. 4 and 5, 1-1, 1-2, 1-3 and 4-
Both 1,4-2,4-3 operate as a delay element and delay the pulse signal applied to the input terminal by a predetermined value. The sum of the delay times of the respective stages, that is, the number of circuit stages corresponds to the level of the oscillation output frequency. Therefore, the shorter the delay time and the smaller the number of circuit stages, the higher the oscillation frequency.

[0006]

In the configurations of FIGS. 4 and 5, in order to increase the oscillation frequency without changing the circuit configuration, it is necessary to shorten the delay time.
It was necessary to increase the current consumption especially in the circuit of. The whole current of the inverter circuit was processed so as to flow in a large amount. Alternatively, it is necessary to make the number of cascade connection stages small, but the minimum number of connection stages is 3, so it cannot be made smaller than that.

An object of the present invention is to improve the above-mentioned drawbacks, and to provide an oscillation circuit capable of increasing the oscillation frequency by an odd number of times without changing the number of stages of the oscillation circuit and without increasing the frequency of the oscillation loop circuit. To provide.

[0008]

FIG. 1 is a diagram showing the principle configuration of the present invention. In FIG. 1, 3 is an output terminal of an oscillator, 4-1, 4-2, 4-3 are amplifiers of differential input / differential output, 5,
6 is a two-way return path, 7-1 to 7-4 are logical operation circuits, 8
Indicates a synthesis circuit.

The present invention has the following configuration in an oscillation circuit constructed by connecting a plurality of stages of delay circuits in cascade connection and feeding back the final stage output to the first stage input. That is, the delay circuit is configured by differential input / differential output stages, and the normal output and the inverted output of the output signal waveform of each stage are taken out separately,
It is characterized in that it is provided with a logical operation circuit for applying the respective outputs to perform an operation and a synthesizing circuit of the outputs of the respective logical operation circuits, and making the synthesizing circuit output the oscillation circuit output.

[0010]

As shown in FIG. 1, each of the circuits 4-1, 4-2, and 4-3 has a differential input / differential output configuration, and the output signal waveform of each circuit stage has a normal output and an inverted output. Logical operation circuit 7-
Apply to 1,7-2,7-3. Next, each logic operation circuit 7-1 to 7-3
Is applied to the synthesizing circuit 8 and the output of the synthesizing circuit 8 is taken out to the terminal 3 and used as the output of the oscillation circuit. Since the output waveform of each circuit stage is the same and only the phase is different, it is easy to configure the oscillation circuit, and the output of the oscillation circuit has a frequency that is an odd multiple of the original waveform.

[0011]

FIG. 2 is a diagram showing the construction of an embodiment of the present invention. The logical operation circuits 7-1 to 7-3 are AND circuits, and the synthesis circuit 8 is an OR circuit. The output of each stage that operates as a delay circuit is applied to each AND circuit in combination with one output and an inverted output. That is, the AND circuit 7-1 has one output A of the first stage 4-1 and the inverted output B of the second stage 4-2.
The AND circuit 7-2 has the inverted output B of the second stage 4-2 and one output C of the third stage 4-3, and the AND circuit 7-3 has the third output C.
One output C of the stage (final stage) 4-3 and output A of the first stage 4-1 are applied.

FIG. 3 shows a waveform diagram of each part of FIG.
In FIG. 3, the output of the first stage 4-1 is represented by A, the output of the second stage 4-2 is represented by B, the output of the third stage 4-3 is represented by C, and the operation waveforms of the AND circuit are shown on the left side of each figure. The number of the corresponding AND circuit is shown in the parentheses. When the output waveforms of the respective AND circuits are combined, the waveform of the output 3 at the bottom is obtained. That is, the circuit of FIG. 2 provides a tripled frequency as shown at output 3 of FIG.

According to the present invention, three differential input / difference output stages are provided.
The above odd number can be connected in cascade. At that time, if a logical operation circuit is additionally installed, a waveform of a higher frequency can be easily obtained.

[0014]

As described above, according to the present invention, since a logical operation is performed on a positive / negative symmetrical waveform using a differential input / differential output stage, a high-frequency signal of an odd multiple of the reference oscillation frequency has a beautiful waveform. Has the effect obtained in. Moreover, when obtaining a high frequency signal, the power consumption hardly changes.

[Brief description of drawings]

FIG. 1 is a diagram showing a principle configuration of the present invention.

FIG. 2 is a diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 3 is a diagram showing a waveform of each part of FIG.

FIG. 4 is a diagram showing a configuration of a conventional ring oscillator using an inverter.

FIG. 5 is a diagram showing a configuration of an oscillation circuit using a conventional differential input / differential output stage.

[Explanation of symbols]

 4-1,4-2,4-3 Differential input / differential output stage 5,6 Feedback path 7-1,7-2,7-3 Logical operation circuit 8 Synthesis circuit

Claims (2)

[Claims] 1. An oscillator circuit configured by connecting a plurality of stages of delay circuits in cascade, and feeding back a final stage output to a first stage input, wherein the delay circuit is a differential input / differential output stage (4-1) (4). -2) (4-3)
A logical operation circuit (7-1) for calculating the output signal waveform of each stage by extracting the normal output and the inverted output separately, and applying the outputs
(7-2) (7-3) ─ and each logical operation circuit output synthesis circuit (8)
And an output of the synthesizing circuit (8) as an output of the oscillating circuit. 2. The logical operation circuit according to claim 1, wherein a circuit for logically operating one output of a certain stage and an inverted output of the next stage, an inverted output of the next stage and one output of the next stage. An oscillator circuit comprising: a circuit for logically performing the above operation, a circuit for repeatedly performing the above operation to the next stage, and a circuit for logically operating one output of the final stage and one output of the first stage.