JPH07336217A - Signal processing circuit - Google Patents

Abstract

PURPOSE:To reduce the lock-up time of a PLL circuit to improve the stability of locking in the signal processing circuit using the PLL circuit. CONSTITUTION:A PLL circuit 116 is newly added to the pre-stage of a frequency divider circuit 121 at the pre-stage of a PLL circuit 136. The two PLL circuits have phase comparators 112, 132 at their first stages, voltage controlled oscillators 114, 133 at their final stages and a signal obtained by frequency- dividing the output of the oscillators at frequency divider circuits 115, 135 depending on respective frequency division ratios is given to the phase comparators 112, 132. Since an input signal (a) is multiplied at a multiple of L by the pre-stage PLL circuit 116 added newly, phase comparison by the phase comparator 132 in the post-stage PLL circuit 136 is conducted frequency, resulting that the lock-up time of the PLL circuit 136 is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit using a PLL circuit.

[0002]

2. Description of the Related Art FIG. 5 shows a block diagram of a signal processing circuit using a conventional PLL circuit. As shown in the figure, the conventional circuit includes a frequency divider circuit 31 and a PLL circuit 36.
The input signal a is frequency-divided by the frequency dividing circuit 31, and the frequency-divided output b is supplied to the phase comparator 32 in the PLL circuit 36.
A phase comparison is performed between the output of the voltage controlled oscillator 34 and the frequency-divided output c obtained by dividing the frequency by the frequency dividing circuit 35. The voltage-controlled oscillator 34 is dynamically controlled by the comparison output of the phase comparator 32 and the low-pass filter 33 so that the frequencies of the signal b and the signal c become the same, that is, the locked state, and A synchronous clock having a frequency N / M times that of the signal a is oscillated.

[0003]

Problems in the above-mentioned conventional structure will be described with reference to waveform diagrams. In FIG. 6, M = 3, N
5 shows waveform diagrams of the signal a, the signal b, the signal c, and the output signal d of the phase comparator 32 in FIG. Since the phase comparator 32 performs the phase comparison at the rising edge of the input pulse, the phase comparison is actually performed only during the period in which the positive or negative pulse signal is shown in the waveform diagram of d. In other periods, d is in a high impedance state. Therefore, during that time, the voltage-controlled oscillator 34 in the subsequent stage of the low-pass filter 33 is not subjected to the dynamic control toward the locked state, and retains the previous state except for the influence of a slight leakage current. As shown in the figure, by performing the frequency division by the frequency dividing circuit 31, the high impedance state, that is, the period during which the voltage controlled oscillator 34 is not dynamically controlled toward the locked state is extended, and therefore, The time required for the PLL circuit 36 to lock up increases, and the stability of lock also decreases.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to shorten the lock-up time of the PLL circuit and improve the stability of lock.

[0005]

In order to achieve this object, the signal processing circuit of the present invention comprises a second P in the preceding stage of the frequency dividing circuit.
An LL circuit is provided, or a frequency divider and a first PLL are provided.
The second PLL circuit is provided between the circuits.

[0006]

With this configuration, the PLL circuit at the front stage has a function of multiplying the clock signal, and the phase comparison is frequently performed in the PLL circuit at the rear stage, whereby the lock-up time of the PLL circuit at the rear stage is shortened, In addition, the stability of lock is improved.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram of a signal processing circuit according to a first embodiment of the present invention.

In FIG. 1, 112 to 116 and 1
32 to 136 are 32 to 3 in FIG. 5 described above, respectively.
Since it has the same configuration as that of No. 6, its description is omitted. However, the frequency dividing ratio of the frequency dividing circuit 115 is L, and the frequency dividing ratio of the frequency dividing circuit 135 is N. This embodiment is characterized in that the second PLL circuit 116 is provided in the preceding stage of the frequency dividing circuit 121.
The frequency dividing ratio of the frequency dividing circuit 121 is M.

The operation of the signal processing circuit configured as described above will be described below. The input signal a is multiplied by L by the PLL circuit 116 at the preceding stage, is divided by M by the frequency dividing circuit 121, and is multiplied by N this time by the PLL circuit 136 at the succeeding stage, just like the PLL circuit 36 in FIG. . That is, the voltage controlled oscillator 134 at the final stage oscillates a synchronous clock having a frequency of L · N / M times the input signal a.

FIG. 2 shows a waveform chart at each point a to e in FIG. 1 when L = 3, M = 3 and N = 24. P in the previous stage
By the multiplication function of the LL circuit 116, the PLL circuit 1 in the subsequent stage is
The phase comparison of the signal c and the signal d by the phase comparator 132 in 36 is performed three times as frequently as in the case without the PLL circuit 116 (see e).

As described above, according to the first embodiment, by providing the PLL circuit 116 in the front stage of the frequency dividing circuit 121, the phase comparison is performed more frequently in the PLL circuit 136 in the rear stage. , The lock-up time of the PLL circuit is shortened, and the lock stability is improved.

In the present embodiment, 121 is a general expression of the frequency dividing circuit, but the same effect can be obtained even when M = 1, that is, when the frequency dividing circuit is not passed and is passed as it is. Needless to say. In this case, the block diagram of FIG. 1 is one in which two PLL circuits are cascade-connected. (Embodiment 2) FIG. 3 is a block diagram of a signal processing circuit according to a second embodiment of the present invention.

In FIG. 3, 222 to 226 and 2
32 to 236 have the same configurations as those of 32 to 36 in FIG. 5, respectively, and a description thereof will be omitted. However, the frequency dividing ratio of the frequency dividing circuit 225 is M, and the frequency dividing ratio of the frequency dividing circuit 235 is N. In this embodiment, the frequency divider circuit 211 and the first PLL circuit 2 are used.
It is characterized in that a second PLL circuit 226 is provided between 36. The frequency division ratio of the frequency dividing circuit 211 is L.

The operation of the signal processing circuit configured as described above will be described below. The input signal a is divided by L by the frequency dividing circuit 211, and then the PLL circuit 3 in FIG.
6, the PLL circuit 226 multiplies by M, and the PLL circuit 236 multiplies by N this time. That is, the voltage controlled oscillator 234 at the final stage oscillates a synchronous clock having a frequency of M · N / L times the input signal a.

FIG. 4 shows a waveform diagram at each point of a to e in FIG. 3 when L = 3, M = 4 and N = 18. If the PLL circuit 226 is not provided, the phase comparison by the phase comparator 232 is performed between the signal b and the signal d, and the comparison is performed only twice within the period shown in FIG. The signal b is multiplied by the multiplying function of the circuit 226 to obtain the signal c.
Is obtained, and the phase comparison in the phase comparator 232 is performed four times more frequently than in the case without the PLL circuit 226 (see e).

As described above, according to the second embodiment,
The PLL circuit 2 is provided between the frequency divider circuit 211 and the PLL circuit 236.
By including 26, the phase comparison is performed more frequently in the PLL circuit 236 in the subsequent stage.
The lock-up time of the L circuit is shortened and the lock stability is improved.

In the present embodiment, reference numeral 211 is a general expression of the frequency dividing circuit, but the same effect can be obtained even when L = 1, that is, when the frequency dividing circuit is passed through without any division. Needless to say. In this case, the block diagram of FIG. 3 is one in which two PLL circuits are cascade-connected.

[0018]

As is apparent from the above description of the embodiments, the signal processing circuit of the present invention has the second PL in the preceding stage of the frequency dividing circuit.
By providing the L circuit or by providing the second PLL circuit between the frequency dividing circuit and the first PLL circuit, the lockup time of the PLL circuit at the subsequent stage is shortened and the stability of lock is improved. , Its practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of a signal processing circuit according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram of representative points in the signal processing circuit according to the first embodiment.

FIG. 3 is a block diagram of a signal processing circuit according to a second embodiment of the present invention.

FIG. 4 is a waveform diagram of representative points in the signal processing circuit of the second embodiment.

FIG. 5 is a block diagram of a conventional signal processing circuit.

FIG. 6 is a waveform diagram of representative points in a conventional signal processing circuit.

[Explanation of symbols]

 112, 132 Phase comparator 114, 134 Voltage controlled oscillator 115, 121, 135 Dividing circuit 116, 136 PLL circuit

Claims (4)

[Claims] 1. A PLL circuit comprising two PLL circuits and one divider circuit, wherein an output of the PLL circuit of the preceding stage is divided by the divider circuit, and an output of the divider circuit is input to an input of the PLL circuit of the latter stage. A signal processing circuit characterized by: 2. The two PLL circuits each include a phase comparator in the first stage and a voltage controlled oscillator in the final stage, and the output of the voltage controlled oscillator is divided by a frequency dividing circuit into individual frequency division ratios. 2. The signal processing circuit according to claim 1, wherein the signal processing circuit has a configuration in which the frequency divided by is input to the phase comparator. 3. A PLL circuit comprising two PLL circuits and one frequency dividing circuit, wherein the output of the frequency dividing circuit is used as an input of the PLL circuit of the preceding stage, and the output of the PLL circuit of the preceding stage is the PLL of the latter stage.
A signal processing circuit characterized by being used as an input of a circuit. 4. The two PLL circuits both have a phase comparator in the first stage and a voltage controlled oscillator in the final stage, and the output of the voltage controlled oscillator is divided by a frequency divider into individual frequency division ratios. 4. The signal processing circuit according to claim 3, wherein the phase-divided signal is input to the phase comparator.