JPH07231223A - Frequency multiplier circuit - Google Patents

Abstract

PURPOSE:To form a frequency multiplier circuit suitable for circuit integration, with a small circuit scale, small current consumption and applicable to a high frequency up to a limit of a device capability. CONSTITUTION:An output of an original oscillation circuit 11 is given to one input of a phase comparator circuit 12, and an output of an n.m stage ring counter 13 is given to the other input of the phase comparator circuit 12. A phase difference output of the phase comparator circuit 12 is given to the ring counter 13 via an LPF 14 as a control voltage and a logic circuit 15 of EX-OR circuit configuration exclusively ORs n-sets of outputs of the ring counter 13 to obtain an output of a frequency nf.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is based on frequency f
The present invention relates to a frequency multiplying circuit for obtaining a frequency of f (n is an integer of 2 or more), and particularly to a frequency multiplying circuit having a PLL (Phase Locked Loop) circuit configuration.

[0002]

2. Description of the Related Art A frequency multiplication circuit is used in a high frequency signal processing circuit, for example, to obtain a frequency n times the original oscillation frequency f using a resonator. This is because there is an optimum range for the frequency obtained by the resonator. As this type of frequency multiplication circuit, conventionally, two types of circuit configurations are typically known. Two types of conventional examples will be described below.

FIG. 8 is a block diagram showing a conventional example. In the figure, the original oscillation frequency f (a) output from the original oscillation circuit 81 passes through the distortion circuit 82 and the resonance circuit 8
3 is supplied. The original oscillation frequency f (a) is converted into the distortion circuit 83.
The output (b) has a high-order high frequency by passing through.
By passing it through the resonance circuit 83, the output (c) of only the frequency of nf can be taken out. 9 (a)-
(C) shows the frequency spectra of the outputs (a) to (c) of the original oscillation circuit 81, the distortion circuit 82, and the resonance circuit 83.

[0004]

However, the conventional frequency multiplication circuit having the above-mentioned structure has a simple circuit structure but has the following drawbacks. That is, since the resonance circuit 83 is required, it is not suitable for being integrated into an IC. The spectrum other than nf cannot be completely removed, and the spectrum purity is low. If the purity of the spectrum is to be increased, the Q of the resonance circuit 83 becomes large and adjustment is required.

FIG. 10 is a block diagram showing another conventional example. In the figure, the oscillation output of the original oscillation circuit 101 is used as one input of the phase comparison circuit (PD) 102, the oscillation output of the VCO (voltage controlled oscillation circuit) 103 is derived as the output of the frequency nf, and the frequency is divided by 1 / N. The frequency is divided by the circuit 104 to be used as the other input of the phase comparison circuit 102, and the phase difference output of the phase comparison circuit 102 is passed to the LPF (low pass filter)
The PLL circuit configuration supplies the VCO 103 as a control voltage via V.

The frequency multiplying circuit having such a configuration can be constructed without using a resonance circuit as in the prior art example described above, so that an IC is used.
It has the advantage that it has high signal purity and there is no adjustment point. On the other hand, when the circuit scale increases and the desired frequency nf increases, V
There is a problem that the configuration of the CO 103 becomes difficult, the current consumption increases, and further the current consumption of the frequency dividing circuit 104 increases.

The present invention has been made in view of the above problems, and it is an object of the present invention to be suitable for use in an IC and to have a small circuit scale, to consume a small amount of current, and to reduce the device capacity to the limit. An object is to provide a frequency multiplication circuit applicable to high frequencies.

[0008]

According to a first aspect of the present invention, there is provided a frequency multiplication circuit, wherein an output of an original oscillation circuit is used as one input of a phase comparison circuit and a propagation delay time is variable in n · m (both integer) stages. The output of the ring counter is used as the other input of the phase comparison circuit, and the phase difference output of the phase comparison circuit is supplied to the ring counter via the LPF as a control voltage for controlling its propagation delay time. The output of the frequency nf is obtained by the logic circuit based on the above.

According to a second aspect of the present invention, there is provided a frequency multiplication circuit according to the first aspect, wherein the logic circuit is constituted by an n-input exclusive OR circuit. The frequency multiplying circuit according to claim 3 is the frequency multiplying circuit according to claim 1, in which the phases are shifted by 2π / n from each other and the width is π /.
a first gate circuit for generating n pulses corresponding to n;
A logic circuit is configured by a second gate circuit that takes the logical sum of n pulses.

The frequency multiplying circuit according to a fourth aspect is the frequency multiplying circuit according to the first, second or third aspect, in which a frequency dividing circuit is inserted and arranged between the ring counter and the phase comparing circuit. The frequency multiplication circuit according to claim 5,
In the frequency multiplying circuit according to claim 1, 2 or 3, a frequency dividing circuit is inserted and arranged between the original oscillation circuit and the phase comparison circuit.

[0011]

The frequency multiplication circuit according to the first aspect has a PLL circuit configuration using a ring counter instead of the VCO. In this frequency multiplier circuit, n of the ring counter is
As the individual outputs, pulse signals whose phases are shifted by π / n are obtained. Then, the output of the frequency nf can be obtained by combining the logics of these five output pulses.

In the frequency multiplier circuit according to claim 2,
The output of the frequency nf is obtained by taking the exclusive OR of the n output pulses of the ring counter. In this logical operation, a truth table is processed by a tournament method using a strictly defined two-input exclusive OR circuit. The frequency multiplier circuit according to claim 3, wherein n of a ring counter is provided.
By combining the logics of the output pulses, n pulses whose phases are shifted by 2π / n and whose width is equivalent to π / n can be obtained. By taking the logical sum of these n pulses, the output of frequency nf is obtained.

In the frequency multiplying circuit according to claim 4,
When a ring counter and a frequency dividing circuit are used in combination, the ring counter is n ₁ stages, and the frequency dividing ratio of the frequency dividing circuit is n ₂ ,
A multiplication ratio of n ₁ · n ₂ is obtained. In the frequency multiplication circuit according to the fifth aspect, by dividing the output of the original oscillation circuit and inputting it to the phase comparison circuit, frequencies other than simple integer multiples can be obtained.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. As shown in FIG. 1, in the frequency multiplication circuit according to the present invention, the oscillation output of the original oscillation circuit 11 is compared with the phase comparison circuit 12
Ring counter 1 with n inputs and m inputs
The output of 3 is used as the other input of the phase comparison circuit 12, the phase difference output of this phase comparison circuit 12 is used as the control input of the ring counter 13 via the LPF 14, and the n outputs of this ring counter 13 are passed through the logic circuit 15. As a result, the PLL circuit configuration is used to obtain the output of the frequency nf. The ring counter 13 has a configuration in which the propagation delay time t _pd is variable according to the control voltage supplied from the LPF 14.

In the ring counter 13, both n and m are integers, m is usually "1", and n is a multiplication number. From the ring counter 13, n outputs whose phases are shifted by π / n are taken out. When m = 1, an output signal whose phase is shifted by π / n is obtained as an output of each stage of the ring counter 13. The logic circuit 15 is constituted by, for example, an n-input EX-OR (exclusive OR) circuit, and outputs an event of n output from the ring counter 13, that is, an output signal whose polarity is inverted each time the signal is inverted, at a frequency nf. It is derived as the output of.

FIG. 2 is a timing chart for explaining the circuit operation of the frequency multiplier circuit having the above configuration. In this example, the operation in the case of multiplication by 5 (n = 5) is shown. In FIG. 2, the waveform a is the original oscillation waveform of the original oscillation circuit 11,
Waveforms b to f show output waveforms of the ring counter 13 having the same frequency as the original oscillation and a phase shifted by π / 5.
Further, the waveform g shows the EX-OR output of 5 inputs,
It can be seen that the output is obtained at a frequency of 5 times the original oscillation frequency.

Next, each component of the frequency multiplication circuit according to the present invention will be described with a concrete circuit example. FIG. 3 is a block diagram showing a specific configuration of an n-input (5-input in this example) EX-OR circuit. As is clear from the figure, the n-input EX-OR circuit has a 2-input EX-O
It is configured by a combination of R circuits 16 to 19. Two
The truth table of the input EX-OR circuit is strictly defined and widely known as shown in Table 1. The n-input EX-OR circuit may be processed in a tournament system by using the 2-input EX-OR circuits 16 to 19 as shown in FIG.

[0018]

[Table 1]

FIG. 4 is a block diagram showing a specific structure of the ring counter in the case of multiplying by 5. This ring counter is composed of five stages of buffers 20 to 2 which are connected in cascade.
4 and is configured to return the output of the final stage to the initial stage. As a result, five outputs V1 to V5 whose phases are shifted by π / 5 can be obtained as the output of each stage.

FIG. 5 is a circuit diagram showing an example of the configuration of the buffers 20 to 24 which form the ring counter 13. The buffer 20-24, a differential circuit 25 having an emitter composed of the transistors Q _1, Q ₂ and its load resistor R _1, R ₂ constituting the commonly connected with differential operation, common emitter of the transistors Q _1, Q ₂ Current source I connected to the connection point
and an emitter follower circuit 26 consisting of transistors Q ₃ and Q ₄ whose bases are connected to the collectors of the transistors Q ₁ and Q ₂ , respectively, and a current source Ic connected to the emitters of the transistors Q ₃ and Q _{4. 1} and Ic ₂ .

In the buffer having the above structure, the LP of FIG.
The current source I is controlled by the control voltage Vc supplied from F14.
The propagation delay time t _pd of the ring counter 13 can be changed by controlling c ₁ and Ic ₂ and changing the emitter voltages of the transistors Q ₃ and Q ₄ . When the frequency used is relatively low, as shown in FIG.
The propagation delay time t _pd can be positively increased by adding the capacitance C ₁ between the emitters of the transistors Q ₃ and Q ₄ .

As described above, in the frequency multiplication circuit having the PLL circuit configuration, the ring counter 13 of n · m stages is used in place of the VCO, so that a resonance circuit is not necessary, which is suitable for an IC, and a frequency division circuit. Since it is unnecessary, the circuit scale can be small. By the way, it is much easier to create a ring counter than to create a frequency divider circuit in terms of circuit creation.

Further, the desired frequency nf is, for example,
Considering the case of a considerably high frequency of 0 MHz, in the circuit of the conventional example shown in FIG. 10, in order for the VCO 103 to oscillate at the oscillation frequency determined by the resonance circuit or the time constant circuit, the circuit itself has a frequency considerably higher than the frequency nf. Need to work. For that purpose, it is necessary to pass a considerably large current. On the other hand, in the ring counter 13, t _pd = 1 / (2 · nf) is automatically set. This is like automatically setting the minimum current that operates at the minimum at the frequency nf.

Furthermore, the frequency divider circuit 104 in the conventional circuit shown in FIG. 10 also consumes a large amount of current. That is, in order to operate at the frequency nf, the propagation delay time of the gate circuit forming the frequency dividing circuit is t _pd <1 / (4 · n
It is necessary to perform f), and it is necessary to flow the current with a margin to satisfy this condition even in the worst case.

For the above-mentioned reason, the frequency multiplier circuit according to the present invention achieves a significantly lower current consumption than the conventional circuit shown in FIG. Regarding the frequency limit, in the conventional example, the transistor needs to have a sufficient margin with respect to the operating frequency, whereas in the present invention, the operating frequency can be increased to the limit at which the device operates at a minimum. Therefore, it can be applied to various high frequency ICs.

Although the EX-OR circuit is used as the logic circuit 15 in the above embodiment, the logic circuit 15 is not limited to this, and a logic circuit configuration as shown in FIG. 6 can be used.

This logical circuit is an AND circuit 27 that takes the logical product of the output V1 and the inverted signal of the output V2 among the n (five in this example) outputs V1 to V5 supplied from the ring counter 13. An AND circuit 28 for taking the logical product of the inverted signal of the output V2 and the output V3, an AND circuit 29 for taking the logical product of the inverted signal of the output V3 and the output V4, and an output V4
AND circuit 30 which takes the logical product of the inverted signal of V and the output V5
AND circuit 3 that takes the logical product of the output V5 and the output V1
1 that is the logical sum of 1 and each output of the AND circuits 27 to 31
And an R circuit 32.

FIG. 7 is a timing chart for explaining the circuit operation of the logic circuit having the above configuration. In FIG. 7, waveforms V1 to V5 represent five output waveforms of the ring counter 13, waveforms A to E represent output waveforms of the AND circuits 27 to 31, and waveform F represents an output waveform of the OR circuit 32. .

As is clear from these waveforms, AND
The circuits 27 to 31 have five outputs V1 of the ring counter 13.
~ V5 constitutes a first gate circuit for generating five pulses A to E whose phases are shifted by 2π / 5 from each other and whose width is equivalent to π / 5, and the OR circuit 32 is based on n pulses. A second gate circuit for obtaining an output pulse F of frequency nf.

That is, the logic circuit having the above configuration independently synthesizes n pulses having a phase shift of 2π / n and a width corresponding to π / n in one cycle of the original oscillation, and the logic of these pulses is used. It is to take the sum. According to this circuit configuration, the circuit can be simplified and the power consumption can be reduced, though slightly compared to the EX-OR circuit.

In the frequency multiplication circuit according to the present invention, if the multiplication ratio is, for example, 10 or more, the ring counter 13 becomes long. Therefore, in such a case, it may be implemented in combination with the conventional circuit shown in FIG. That is, in FIG. 1, a frequency dividing circuit is inserted and arranged between the phase comparison circuit 12 and the ring counter 13, the ring counter has n ₁ stages, and the frequency dividing ratio of the frequency dividing circuit is n ₂ .

As a result, the multiplication ratio of n ₁ · n ₂ can be obtained. Therefore, even when the multiplication ratio is 10 or more, the ring counter 13 does not become long. Further, since the frequency input to the frequency dividing circuit is simply 1 / n ₁ when the conventional example of FIG. 10 is applied, the power consumption can be significantly reduced. Further, as another application example, in FIG. 1, the original oscillation circuit 11 and the phase comparison circuit 12 are shown.
It is also possible to insert a frequency divider circuit between and. This makes it possible to obtain frequencies other than simple integral multiples.

[0033]

As described above, according to the first aspect of the invention, the output of the original oscillation circuit is used as one input of the phase comparison circuit, and the output of the ring counter of n · m stages is used as the phase comparison circuit. The phase difference output of this phase comparison circuit is supplied to the ring counter as its control voltage via the LPF, and a nf output is obtained by a logic circuit based on the n outputs of this ring counter. ,
By using a ring counter instead of a VCO,
Since the resonance circuit and the frequency dividing circuit which have been used conventionally are not necessary, it is suitable for an IC and the circuit scale can be small.

Further, since there is no frequency divider circuit that consumes a large amount of current, a significant reduction in current consumption can be achieved. Furthermore, since the operating frequency can be increased to the limit at which the device operates, it can be applied to various high frequency ICs.

According to the second aspect of the invention, an n-input E
By configuring the logic circuit with the X-OR circuit,
Since the n outputs of the ring counter can be processed in the tournament method by using the two-input EX-OR circuit whose truth table is strictly defined, it can be realized by the combination of only the two-input EX-OR circuits. According to the third aspect of the invention, a gate circuit for generating n pulses having a phase shift of 2π / n and a width corresponding to π / n, and a gate circuit for ORing the n pulses are used. By configuring the logic circuit, the circuit configuration can be simplified and the power consumption can be reduced, though slightly compared with the EX-OR circuit.

According to the invention described in claim 4, the frequency dividing circuit is inserted and arranged between the ring counter and the phase comparing circuit, and the ring counter and the frequency dividing circuit are combined to be used. Since the multiplication ratio of n ₁ · n ₂ can be obtained when the division ratio of the n ₁ stage and the division circuit is n ₂ , this circuit can be configured without lengthening the ring counter even if the multiplication ratio becomes large. become.

Further, since the frequency input to the frequency dividing circuit is simply 1 / n _{1 of} that of the conventional PLL circuit configuration, the current consumption can be greatly reduced. Claim 5
According to the described invention, a frequency divider circuit is inserted and arranged between the original oscillator circuit and the phase comparator circuit, and the output of the original oscillator circuit is divided by the frequency divider circuit before being input to the phase comparator circuit. By doing so, it is possible to obtain frequencies other than simple integral multiples.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the circuit operation of the present invention.

FIG. 3 is a block diagram illustrating an example of a logic circuit.

FIG. 4 is a block diagram showing an example of the configuration of a ring counter in the case of multiplication by 5.

FIG. 5 is a circuit diagram showing an example of a buffer forming a ring counter.

FIG. 6 is a block diagram showing another example of a logic circuit.

FIG. 7 is a timing chart for explaining the circuit operation of FIG.

FIG. 8 is a block diagram showing a conventional example.

9 is a diagram showing a frequency spectrum of a signal of each part of the circuit of FIG.

FIG. 10 is a block diagram showing another conventional example.

[Explanation of symbols]

 11 original oscillation circuit 12 phase comparison circuit 13 ring counter 15 logic circuit 16 to 19 2-input EX-OR circuit 20 to 24 buffer

Claims (5)

[Claims] 1. An original oscillation circuit that oscillates at a predetermined frequency f, a ring counter with n · m (both integer) stages whose propagation delay time is variable, and an output of the original oscillation circuit and an output of the ring counter. Based on a phase comparison circuit that detects a phase difference, a low-pass filter that supplies the phase difference output of the phase comparison circuit to the ring counter as a control voltage that controls the propagation delay time, and n outputs of the ring counter. Frequency nf
And a logic circuit that obtains the output of the frequency multiplication circuit. 2. The frequency multiplying circuit according to claim 1, wherein the logic circuit is an n-input exclusive OR circuit. 3. The logic circuits have a phase of 2π / n with respect to each other.
2. A first gate circuit for generating n pulses, each of which has a shift of π / n and a width corresponding to π / n, and a second gate circuit for ORing the n pulses.
The described frequency multiplication circuit. 4. A frequency divider circuit is provided between the ring counter and the phase comparator circuit.
The frequency multiplying circuit described in 2 or 3. 5. The frequency multiplying circuit according to claim 1, further comprising a frequency dividing circuit between the original oscillation circuit and the phase comparing circuit.