JP2009130544A - Clock signal generation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock signal generation circuit capable of generating high-speed clock signals from a low-speed reference clock and mitigating the limit of the frequency selection of the high-speed clock signals by a simple circuit configuration. <P>SOLUTION: The clock signal generation circuit 100 includes, in the order, a reference clock signal generation circuit 110 for generating a low-speed reference clock signal S1, a PLL circuit 130 for multiplying the low-speed reference clock signal S1 from the basic clock signal generation circuit 110 by N1 and outputting multiple output S2, a frequency divider circuit 140 for frequency-dividing the multiple output S2 of the PLL circuit 130 by 1/N and outputting a second reference clock signal S3 faster than the low-speed reference clock signal S1, and a PLL circuit 150 for multiplying the second reference clock signal S3 of the frequency divider circuit 140 by N2 and outputting multiple output S4 which is the high-speed clock signal. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a clock signal generation circuit, and more particularly to a clock signal generation circuit that generates a high-speed clock signal for signal processing from a low-speed reference clock.

  In order to supply a drive signal for a high-speed signal processing circuit of a semiconductor integrated device, a PLL (Phase Locked Loop) circuit multiplies the frequency of the low-speed reference clock signal generation circuit by N to generate a high-speed clock signal. A typical method is to use a signal as a drive signal for a high-speed signal processing circuit. In addition to keeping the oscillation frequency constant, the PLL circuit can also output a signal at a frequency that is an integral multiple of the input signal by incorporating a counter.

  As a method for generating a high-speed clock signal used in a conventional semiconductor integrated device, there is a semiconductor integrated device described in Patent Document 1.

  FIG. 6 is a diagram illustrating a clock signal generation circuit described in Patent Document 1. In FIG.

  In FIG. 6, the clock signal generation circuit 10 includes a reference clock signal generation circuit 11, a time base processing circuit 12, a PLL circuit 13, and a high-speed signal processing circuit 14.

  The reference clock signal generation circuit 11 generates a low-speed reference clock signal S1. The frequency range of the reference clock signal S1 is 10 kHz to 100 kHz. In this example, the frequency of the reference clock signal S1 is 32 kHz.

  The time base processing circuit 12 divides the reference clock signal S1 from the reference clock signal generation circuit 11 to generate and output time data. The time base processing circuit 12 performs various processes such as an interrupt process for the high-speed signal processing circuit 14 and monitoring by a watchdog timer function based on the time data.

  The PLL circuit 13 multiplies the low-speed clock signal S1 from the reference clock signal generation circuit 11 by N to generate a high-speed clock signal S2. The upper limit of the multiplication number N is not particularly limited as long as it is 100 or more, but the range is preferably, for example, 100 to 20000. The frequency range of the clock signal S2 generated by the PLL circuit 13 is several tens of MHz to several hundreds of MHz, for example, a range of 10 MHz to 700 MHz.

The high-speed signal processing circuit 14 drives the clock signal S2 generated by the PLL circuit 13 as a drive signal, performs predetermined data processing on the high-speed signal S3 input from the outside, and outputs the processed high-speed signal S4 to the external Output to.
JP 2005-165413 A

  However, such a conventional clock signal generation circuit has the following problems.

  Since the high-speed clock signal S2 is generated by multiplying the low-speed reference clock signal S1 by N using a PLL circuit having a multiplication number N, a high-speed clock signal that can be realized because the setting resolution is coarse when the multiplication number N is an integer multiplication. The frequency selection limit of S2 becomes large.

For example, in the clock signal generation circuit 10 of FIG. 6, the case where the high-speed clock signal S3 = 22.5 MHz is required from the low-speed reference clock signal S1 = 32 kHz is taken as an example. The multiplication factor N of the PLL circuit 13 is
N = 22.5MHz / 32kHz = 703.125
Therefore, since a multiplication number expressed by a decimal point is required, it cannot be realized by integer multiplication. Therefore, the frequency at which the high-speed clock signal S2 can be realized is limited when the PLL circuit 13 is multiplied by an integer. In order to relax the restriction on the frequency selection of the high-speed clock signal S2, the frequency divider used in the PLL circuit 13 is changed to a method that can set the frequency division number in a fractional manner such as the fractional N method, and the setting resolution There is a way to make it fine. However, this method requires a frequency divider capable of setting the frequency division number in a fraction, and has a drawback that the configuration of the frequency divider becomes complicated.

  The present invention has been made in view of the above points, and can generate a high-speed clock signal from a low-speed reference clock with a simple circuit configuration, and can ease restrictions on frequency selection of the high-speed clock signal. An object of the present invention is to provide a clock signal generation circuit that can be used.

  A clock signal generation circuit according to the present invention includes a reference clock signal generation circuit that generates a first reference clock signal, a first PLL circuit that multiplies the first reference clock signal by N1, and the first PLL circuit. A frequency dividing circuit that divides the multiplied output by 1 / N and outputs a second reference clock signal that is faster than the first reference clock signal, and a second reference clock signal of the frequency dividing circuit is multiplied by N2. And a second PLL circuit that outputs a high-speed clock signal.

  According to the present invention, a high-speed clock signal can be generated from a low-speed reference clock with a simple circuit configuration. In addition, since the frequency that can be realized is further (N2 / N) times higher than the conventional multiplication number, it is possible to relax the restriction on the frequency selection of the high-speed clock signal and to shorten the stabilization time. .

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a diagram showing a configuration of a clock signal generation circuit according to Embodiment 1 of the present invention. This embodiment is an example applied to a clock signal generation circuit that creates a high-speed clock signal for signal processing from a low-speed reference clock.

  In FIG. 1, a clock signal generation circuit 100 includes a reference clock signal generation circuit 110, a time base processing circuit 120, a PLL circuit 130 (first PLL circuit), a frequency divider circuit 140, and a PLL circuit 150 (second circuit). PLL circuit) and a high-speed signal processing circuit 160 including a PCM (Pulse Code Modulation) CODE block 160A and an Audio DA / AD block 160B.

  The reference clock signal generation circuit 110 generates a low-speed reference clock signal S1 (first reference clock signal).

  The time base processing circuit 120 divides the reference clock signal S1 from the reference clock signal generation circuit 110 to generate and output time data until the high-speed signal processing circuit 160 is put into an operation state based on the time data. Performs various processes such as time setting and interrupt processing.

  The PLL circuit 130 is a PLL frequency synthesizer that multiplies the low-speed reference clock signal S1 from the reference clock signal generation circuit 110 by N1 (N1 is an arbitrary natural number) and outputs a multiplied output S2.

  The frequency divider circuit 140 divides the multiplied output S2 of the PLL circuit 130, to which the low-speed reference clock signal S1 is input, by 1 / N (N is an arbitrary natural number) and serves as a second reference clock signal S3 of the PLL circuit 150. Output.

  The PLL circuit 150 is a PLL frequency synthesizer that multiplies the second reference clock signal S3 from the frequency divider circuit 140 by N2 (N2 is an arbitrary natural number) and outputs a multiplied output S4.

  The high-speed signal processing circuit 160 drives the clock signal S4 generated by the PLL circuit 150 as a drive signal, performs predetermined data processing on the high-speed signals S5a and S5b input from the outside, and the processed high-speed signal S6a , S6b is output to the outside. Specifically, the high-speed signal processing circuit 160 includes a PCM CODEC block 160A and an Audio DA / AD block 160B, and the PCM CODEC block 160A processes the audio signal S5a by the PCM codec function. The Audio DA / AD block 160B performs DA conversion processing and AD conversion processing on the audio signal S5b.

  Thus, the clock signal generation circuit 100 includes the reference clock signal generation circuit 110 that generates the low-speed reference clock signal S1 (first reference clock signal), and the low-speed reference clock signal S1 from the reference clock signal generation circuit 110. Is multiplied by N1, and the multiplied output S2 of the PLL circuit 130 and the multiplied output S2 of the PLL circuit 130 are divided by 1 / N, and a second reference clock signal S3 that is faster than the low-speed reference clock signal S1 is output. And a PLL circuit 150 that multiplies the second reference clock signal S3 of the frequency divider circuit 140 by N2 and outputs a frequency-multiplied output S4 that is a high-speed clock signal.

  The low-speed reference clock signal S1 generated by the reference clock signal generation circuit 110 is supplied to the PLL circuit 130, and the multiplied output S2 of the PLL circuit 130 is divided by the frequency dividing circuit 140. The clock signal S3 is input to the PLL circuit 150. Then, the multiplication output S4 of the PLL circuit 150 is input to the high-speed signal processing circuit 160.

  Further, the lock-up time τ1 of the PLL circuit 130 and the lock-up time τ2 of the PLL circuit 150 set the response characteristics of the PLL circuits 130 and 150 so that the relationship of τ1 ≧ τ2 is established.

  FIG. 2 is a diagram illustrating specific circuit configurations of the PLL circuit 130 and the PLL circuit 150. Since the PLL circuit 130 and the PLL circuit 150 have the same configuration, the PLL circuit 130 will be described as a representative.

  In FIG. 2, the PLL circuit 130 includes a phase comparator 131, a charge pump circuit 132, a loop filter 133, a voltage controlled oscillation circuit 134, and a frequency divider circuit 135.

  The phase comparator 131 compares the output of the frequency divider circuit 135 with the phase of the low-speed reference clock signal S1, generates an UP signal and a DOWN signal, and outputs the UP signal and the DOWN signal to the charge pump circuit 132.

  The charge pump circuit 132 converts the UP signal and DOWN signal from the phase comparator 131 into a current or voltage and outputs the current or voltage to the loop filter 133.

  The loop filter 133 extracts a low frequency component from the output of the charge pump circuit 132 and outputs the low frequency component to the voltage controlled oscillation circuit 134.

  The voltage controlled oscillation circuit 134 receives the low frequency component from the loop filter 133 as an input voltage, and outputs the output frequency VOUT corresponding to the input voltage to the outside and also outputs it to the frequency divider circuit 135.

  The frequency dividing circuit 135 divides and outputs the output frequency of the voltage controlled oscillation circuit 134.

  FIG. 3 is a circuit diagram showing a configuration of the loop filter 133 of the PLL circuit 130.

  In FIG. 3, the loop filter 133 includes a resistor 133a, a resistor 133b, and a capacitor 133c.

  The loop filter 133 smoothes the voltage pulse of the charge pump circuit 132 by a filter composed of a resistor 133a, a resistor 133b, and a capacitor 133c, converts it to a DC level, and then outputs it as an input voltage of the voltage controlled oscillation circuit 134.

  The lock-up time of the PLL circuit 130 can be changed by changing N1 of the frequency divider circuit 135 of FIG. 2 and the time constant determined by the resistor 133a, the resistor 133b, and the capacitor 133c constituting the loop filter 133. . Details will be described later in the description of the operation.

  Hereinafter, the operation of the clock signal generation circuit 100 configured as described above will be described.

  The PLL circuit 130 has a lock-up time τ1, and multiplies the frequency of the input signal by N1 and outputs it. The PLL circuit 150 has a lock-up time τ2 and outputs the input signal frequency multiplied by N2.

  The frequency divider circuit 140 has a function of reducing the frequency of the input signal to 1 / N.

  The lockup time τ1 of the PLL circuit 130 to which the reference clock signal S1 from the reference clock signal generation circuit 110 is first input is sufficiently longer than the lockup time τ2 of the PLL circuit 150 that drives the high-speed signal processing circuit 160. That is, it is set so that τ1> τ2.

  In the clock signal generation circuit 100 configured as described above, the high-speed clock signal S4 output from the PLL circuit 150 can be determined from the reference clock signal S1 using the following equation (1).

S4 = S1 × N1 × (1 / N) × N2 (1)
Equation (1) is modified to obtain the following equation (2).

S4 = S1 × N1 × (N2 / N) (2)
When (N2 / N) in the above equation (2) is 1, the multiplication factor is the same as the high-speed clock signal generation method used in the conventional semiconductor integrated device. According to the present embodiment, the PLL circuit 130 that multiplies the low-speed reference clock signal S1 from the reference clock signal generation circuit 110 by N1, and the frequency divider circuit 140 that divides the multiplied output S2 of the PLL circuit 130 by 1 / N. Since the PLL circuit 150 that multiplies the second reference clock signal S3 from the frequency dividing circuit 140 by N2 is provided, the frequency that can be realized is further increased by (N2 / N) times the conventional multiplication number. Thereby, the limitation of the frequency selection of the high-speed clock signal S4 that can be realized is relaxed.

  For example, the multiplication number necessary for generating the high-speed clock signal S4 = 22.5 MHz from the reference clock signal S1 = 32 kHz is expressed by the following equation (3) based on the above equation (2).

N1 × (N2 / N) = S4 / S1
= 22.5MHz / 32kHz
= 703.125 (3)
In the above formula (3), the values of N2, N, and N1 may be combined so as to be 703.125. If N1 is set to an integer value 700 close to 703.15 in the PLL circuit 130, the ratio of N in the frequency divider circuit 140 and the multiplication factor N2 in the PLL circuit 150 is expressed by the following equation (4).

N2 / N = 703.125 / 700 (4)
Here, in order to reduce N of the frequency dividing circuit 140 and the multiplication number N2 of the PLL circuit 150, the ratio of the above equation (4) is set to the smallest possible integer ratio. The method for setting the integer ratio is, for example, in the above formula (4), after expressing N2 and N as a ratio of decimal numbers within the third decimal place, the denominator and the numerator may be multiplied by 1000. (5)

N2 / N = 0.225 / 0.224 = 225/224 (5)
In this case, N2 and N can be realized by integer values of 700 or less.

  With the above combination, the frequency of the high-speed clock signal S4 is expressed by the following equation (6) using the reference clock signal S1 = 32 kHz.

S4 = 32 kHz × (225/224) × 700 = 22.5 MHz (6)
As described above, by using the integer multiplying PLL circuits 130 and 150 and the integer dividing circuit 140, a fractionally multiplied clock signal that cannot be generated conventionally can be generated.

  In the present embodiment, a frequency divider circuit 140 is connected between the output of the PLL circuit 130 and the input of the PLL circuit 150. This is based on the following reason.

  That is, assuming that the output of the PLL circuit 130 and the input of the PLL circuit 150 are connected and the frequency divider 140 is connected to the output of the PLL circuit 150, the operating frequency of the PLL circuit 150 becomes very high, and the operation of the semiconductor device This is because the limit may be reached. For example, when the input of the high-speed signal processing circuit 160 is 22.5 MHz as described above, the PLL circuit 130 multiplies 32 kHz by 700, so that 32 kHz × 700 = 22.4 MHz is input to the PLL circuit 150. Since the PLL circuit 150 further multiplies this by 225, its output frequency is 22.4 MHz × 225 = 5040 MHz, and a very high operating frequency is required. However, when the PLL circuit 150 operates at the above frequency, if the frequency dividing circuit 140 divides the frequency by 224, the final output is similarly 22.5 MHz.

  Therefore, from the equations (1) and (2), although it is considered that the N1 multiplication PLL circuit 130, the 1 / N frequency division circuit 140, and the N2 multiplication PLL circuit 150 can be connected in any order, In reality, there is an operation limit of the semiconductor device, and thus this embodiment in which the frequency dividing circuit 140 is connected between the output of the PLL circuit 130 and the input of the PLL circuit 150 is desirable.

  Next, the lock-up time of the clock signal generation circuit 100 will be described.

  FIG. 4 is a diagram for explaining the lock-up time of the PLL circuit 130 and the PLL circuit 150. 4A and 4B show the lock-up time characteristics of the PLL circuit 130 and the PLL circuit 150 alone, and FIG. 4C shows the case where the PLL circuit 130, the frequency dividing circuit 140, and the PLL circuit 150 are connected. Represents the lock-up time characteristics. In FIG. 4, Flck is a lock-up frequency, and the lock-up time is a time during which the PLL reaches the lock-up frequency Flck from the start of operation and locks.

  As shown in FIGS. 4A and 4B, in the PLL circuit 130 and the PLL circuit 150 alone, the frequency of the PLL circuit 130 is locked at τ1, and the frequency of the PLL circuit 150 is locked at τ2. As shown in FIG. 4B, the lock-up time of both PLL circuits 130 and 150 is such that τ1> τ2, so that the PLL circuit 150 is more than the PLL circuit 130 of FIG. 4A. Lock in early time.

  4C shows lockup time characteristics when the PLL circuit 130 and the PLL circuit 150 are connected in the order shown in FIG. 1, and shows an output waveform S4 of the PLL circuit 150. FIG.

  In the clock signal generation circuit 100 of FIG. 1, the lockup time τ1 of the PLL circuit 130 to which the reference clock signal S1 is first input is sufficiently larger than the lockup time τ2 of the PLL circuit 150 that drives the high-speed signal processing circuit 160. Since it is long, the lockup time τ1S shown in FIG. 4C is limited by τ1. For this reason, when the configuration of the present embodiment is adopted, it is not equal to τ1 + τ2, but is substantially equal to τ1. Further, when the magnitude relationship between the lock-up times of the PLL circuit 130 and the PLL circuit 150 is set opposite to that of the present embodiment, that is, the PLL circuit 130 having the lock-up of τ1, and the PLL circuit having the lock-up of τ2. Under the condition that the relationship of τ1 <τ2 is established at 150, the lockup time τ1S when the PLL circuit 130 and the PLL circuit 150 are connected does not become τ1, but remains τ1 + τ2, and the lockup time cannot be reduced. This is because the frequency change rate per unit time of the PLL circuit 150 is smaller than the frequency change rate per unit time of the PLL circuit 130, so that the PLL circuit 150 has a frequency from the start of operation until the PLL circuit 150 locks up at τ 1. This is because the lock-up time τ2 of the PLL circuit 150 is added to the lock-up time τ1 of the PLL circuit 130 because it hardly changes.

  Next, operations of the PLL circuit 130 and the PLL circuit 150 will be described.

  FIG. 2 is a diagram showing a specific circuit configuration of the PLL circuit 130.

  As shown in FIG. 2, the PLL circuit 130 outputs the output frequency VOUT of the voltage controlled oscillation circuit 134 to the outside and also outputs it to the frequency dividing circuit 135. The frequency dividing circuit 135 divides the output frequency VOUT and inputs it to the phase comparator 131. The phase comparator 131 compares the reference clock signal S1 with the output of the frequency divider circuit 135, generates an UP signal or a DOWN signal from the phase relationship between the reference clock signal S1 and the output signal of the frequency divider circuit 135, and generates a charge pump circuit. It outputs to 132. The charge pump circuit 132 converts the UP signal or DOWN signal into a current or a voltage and outputs the current or voltage to the loop filter 133. The loop filter 133 converts the charge pump signal to DC and outputs it to the voltage controlled oscillation circuit 134.

  In the PLL circuit 130 configured as described above, when the frequency dividing circuit 135 is 1 / N1 (N1 is an integer), the PLL circuit 130 multiplies the reference clock signal S1 by N1 and outputs it.

  The PLL circuit 150 has the same configuration and operation, and the PLL circuit 150 multiplies the second reference clock signal S3 from the frequency divider circuit 140 (FIG. 1) by N2 to the high-speed signal processing circuit 160 (FIG. 1). Output.

  FIG. 3 is a loop filter of the PLL circuit 130 and the PLL circuit 150. The voltage pulse of the charge pump circuit 132 is smoothed by a filter composed of a resistor 133a, a resistor 133b, and a capacitor 133c and converted to a DC level. Thereafter, the input voltage of the voltage controlled oscillation circuit 134 is obtained. Here, the lock-up time of the PLL can be changed by the time constant determined by N1 of the frequency divider circuit 135 shown in FIG. 2 and the resistors 133a, 133b, and the capacitor 133c constituting the loop filter 133.

  For example, the conversion gain KV of the phase comparator 131 of the PLL circuit 130 and the PLL circuit 150 in FIG. 1 is commonly expressed by the following equation (7), and the conversion gain KΦ of the voltage-controlled oscillation circuit 134 is also the PLL circuit 130 and the PLL. It is assumed that the circuit 150 is common and is represented by the following equation (8).

KV = 3V / (4π) (7)
KΦ = 36MHz / V (8)
At this time, in order to set the lock-up time τ1 of the PLL circuit 130 multiplied by 700 to 10 msec, when the loop filter constant shown in FIG. 3 is obtained by simulation under the condition of the damping factor = 0.2, the resistance 133a = 144 kΩ and the resistance 133b = 1.6 kΩ and capacitance 133c = 0.1 μF. Further, in order to set the lock-up time τ1 of the PLL circuit 150 multiplied by 225 to 1 msec, when the loop filter constant shown in FIG. 3 is obtained by simulation under the condition of the damping factor = 0.2, the resistance 133a = 4.4 kΩ and the resistance 133b = 0.13 kΩ and capacitance 133c = 0.1 μF.

  As described above in detail, according to the present embodiment, the clock signal generation circuit 100 includes the reference clock signal generation circuit 110 that generates the low-speed reference clock signal S1 and the low-speed from the reference clock signal generation circuit 110. A PLL circuit 130 that multiplies the reference clock signal S1 by N1 and outputs a multiplied output S2, and a second reference clock that is faster than the low-speed reference clock signal S1 by dividing the multiplied output S2 of the PLL circuit 130 by 1 / N. A frequency dividing circuit 140 that outputs the signal S3 and a PLL circuit 150 that multiplies the second reference clock signal S3 of the frequency dividing circuit 140 by N2 and outputs a multiplied output S4 that is a high-speed clock signal are provided in this order. As a result, it is possible to generate a high-speed clock signal for signal processing that is a fractional multiplication that cannot be generated in the past from a low-speed reference clock with a simple circuit configuration. It can be.

  In particular, since the frequency that can be realized is further (N2 / N) times higher than the conventional multiplication number, the restriction on the frequency selection of the high-speed clock signal can be relaxed.

  In this embodiment, the lock-up time τ1 of the PLL circuit 130 and the lock-up time τM of the PLL circuit 150 are set so that τ1 ≧ τM. The PLL circuit 130 can be reduced to about a single unit.

(Embodiment 2)
FIG. 5 is a diagram showing the configuration of the clock signal generation circuit according to the second embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals, and description of overlapping portions is omitted.

  In FIG. 5, a clock signal generation circuit 200 includes a reference clock signal generation circuit 110, a time base processing circuit 120, a PLL circuit 130, a frequency divider circuit 140, and PLL circuits 210 and 220 (second PLL circuit). The selection circuit 230 and the high-speed signal processing circuit 160 are provided.

  The low-speed reference clock signal S1 generated by the reference clock signal generation circuit 110 is supplied to the PLL circuit 130. The output S2 of the PLL circuit 130 is input to the frequency dividing circuit 140, the output S3 of the frequency dividing circuit 140 is input to the PLL circuit 210 and the PLL circuit 220, and the output S4 of the PLL circuit 210 and the output S7 of the PLL circuit 220 are selected. Input to the circuit 230.

  The selection circuit 230 selects the output S4 of the PLL circuit 210 when the control signal SEL is at a low level, and selects the output S7 of the PLL circuit 220 when the control signal SEL is at a high level, and selects the selection output S8 as a high-speed signal processing circuit. To 160.

  The PLL circuit 210 and the PLL circuit 220 can select an operation state or a stop state by a control signal SEL. When the control signal SEL is at a low level, the PLL circuit 210 operates to stop the PLL circuit 220 and the control signal SEL is high. At the level, the PLL circuit 220 operates and the PLL circuit 210 stops. The PLL circuit 210 is different only in that the operation state is controlled by the control signal SEL from the selection circuit 230, and the characteristics such as the multiplication number are the same as those of the PLL circuit 150 in FIG.

  That is, the PLL circuit 130 has a lock-up time τ1 and outputs the input signal frequency multiplied by N1. The PLL circuit 210 has the same lock-up time τ2 as the PLL circuit 150 of FIG. 1, and outputs the frequency of the input signal multiplied by N2. The PLL circuit 220 has a lock-up time τ3 and outputs the input signal frequency multiplied by N3 (N3 is an arbitrary natural number).

  The frequency divider circuit 140 has a function of reducing the frequency of the input signal to 1 / N. The lock-up time τ 1 of the PLL circuit 130 to which the reference clock signal S 1 from the reference clock signal generation circuit 110 is first input is the lock-up time τ 2 of the PLL circuit 210 that drives the high-speed signal processing circuit 160 and the PLL circuit 220. The lockup time τ3 is set to be sufficiently long, that is, τ1> τ2 and τ1> τ3.

  The difference in configuration from the clock signal generation circuit 100 of FIG. 160 is input. Here, the high-speed clock signal S7 of the PLL circuit 220 can be determined from the reference clock signal S1 using the following equation (9), as in the first embodiment.

S7 = S1 × N1 × (N3 / N) (9)
S1, N1, and N used in the first embodiment are the same in the present embodiment. When N3 = 228, the output S7 of the PLL circuit 220 is expressed by the following equation (10).

S7 = 32 kHz × 700 × 228/224
= 22.8 MHz (10)
Thus, according to the present embodiment, the clock signal generation circuit 200 includes the plurality of PLL circuits 210 and 220 and the selection circuit 230 that selects one of the PLL circuits 210 and 220. The high-speed clock signals S4 and S7 multiplied by a fraction that could not be generated conventionally can be generated. The fractionally multiplied high-speed clock signals S4 and S7 cannot be generated using an integer-multiplied PLL and an integer divider circuit as in the prior art.

  Here, the high-speed clock signal S4 generated by the PLL circuit 210 via the frequency divider 140 from the PLL circuit 130 and the high-speed clock signal S4 generated by the PLL circuit 220 via the frequency divider 140 from the PLL circuit 130 are: Since the rate is limited by the lock-up time τ1 of the PLL circuit 130, it is substantially equal to τ1 as in the case of the first embodiment. Therefore, according to the present embodiment, the two types of high-speed clock signals S4 and S7 can be set to the same lock-up time. Further, the lockup time τ3 of the PLL circuit 220 is equal to the lockup time τ2 of the PLL circuit 150, that is, even when τ2 = τ3, the lockup time is limited by τ1, so it is not equal to τ1 + τ3 but substantially equal to τ1.

  In the present embodiment, the two PLL circuits connected to the frequency divider circuit 140 are described as the PLL circuit 210 and the PLL circuit 220, but two or more may be used. In addition, it is preferable that the maximum lockup time τM among the plurality of PLL circuits connected to the frequency divider circuit 140 has a relationship of τ1 ≧ τM with the lockup time τ1 of the first PLL. With this configuration, the number of PLLs connected to the frequency divider circuit 140 is not particularly limited, and a plurality of fractionally multiplied clock signals can be realized in which an increase in lockup time is minimized.

  The above description is an illustration of a preferred embodiment of the present invention, and the scope of the present invention is not limited to this. For example, each of the above embodiments is a case of a clock signal generation circuit, but the same effect can be obtained also in the case of a semiconductor integrated circuit and a high-speed signal processing device using the same.

  In each of the above embodiments, the name of the clock signal generation circuit is used. However, this is for convenience of explanation, and it is needless to say that the clock supply circuit, the semiconductor integrated circuit device, the signal processing circuit, or the like may be used. .

  Further, the type, number, connection method, and the like of each circuit unit constituting the clock signal generation circuit, for example, the PLL circuit, are not limited to the above-described embodiments.

  The clock signal generation circuit according to the present invention is useful for a high-speed signal processing circuit or the like as a clock signal generation circuit that generates a high-speed clock signal for signal processing from a low-speed reference clock. The high-speed signal processing circuit can be applied to, for example, a PCM CODE / Audio DA / AD circuit. Further, the present invention can be widely applied to clock signal sources in various electronic devices that use a high-speed clock signal from a low-speed reference clock.

The figure which shows the structure of the clock signal generation circuit which concerns on Embodiment 1 of this invention. The figure which shows the specific circuit structure of the PLL circuit of the clock signal generation circuit which concerns on the said Embodiment 1. FIG. The circuit diagram which shows the structure of the loop filter of the PLL circuit of the clock signal generation circuit which concerns on the said Embodiment 1. FIG. The figure explaining the lockup time of the PLL circuit of the clock signal generation circuit according to the first embodiment. The figure which shows the structure of the clock signal generation circuit which concerns on Embodiment 2 of this invention. The figure which shows the conventional clock signal generation circuit

Explanation of symbols

100, 200 Clock signal generation circuit 110 Reference clock signal generation circuit 120 Time base processing circuit 130 PLL circuit (first PLL circuit)
140 Dividing circuit 150, 210, 220 PLL circuit (second PLL circuit)
160 High-speed signal processing circuit 160A PCM CODEC block 160B Audio DA / AD block 230 selection circuit

Claims (7)

A reference clock signal generation circuit for generating a first reference clock signal;
A first PLL circuit that multiplies the first reference clock signal by N1 (N1 is an arbitrary natural number);
A frequency divider that divides the multiplied output of the first PLL circuit by 1 / N (N is an arbitrary natural number) and outputs a second reference clock signal that is faster than the first reference clock signal;
A second PLL circuit for multiplying the second reference clock signal of the frequency divider circuit by N2 (N2 is an arbitrary natural number) and outputting a high-speed clock signal;
A clock signal generating circuit. The first PLL circuit includes:
An oscillator that changes the output frequency according to the input voltage;
A second frequency divider that divides and outputs the output frequency of the oscillator;
A phase comparator that compares and outputs the output of the second frequency divider and the phase of the first reference clock signal;
A charge pump circuit for converting the output of the phase comparator into a phase comparison signal;
A loop filter for extracting a low frequency component from the output of the charge pump circuit,
2. The clock signal according to claim 1, wherein the oscillator receives a low-frequency component from the loop filter as an input voltage, outputs an output frequency corresponding to the input voltage to the outside, and outputs the output frequency to the second frequency divider circuit. Generation circuit. The second PLL circuit includes:
An oscillator that changes the output frequency according to the input voltage;
A second frequency divider that divides and outputs the output frequency of the oscillator;
A phase comparator that compares and outputs the output of the second divider circuit and the phase of the second reference clock signal;
A charge pump circuit for converting the output of the phase comparator into a phase comparison signal;
A loop filter for extracting a low frequency component from the output of the charge pump circuit,
2. The clock signal according to claim 1, wherein the oscillator receives a low-frequency component from the loop filter as an input voltage, outputs an output frequency corresponding to the input voltage to the outside, and outputs the output frequency to the second frequency divider circuit. Generation circuit.   2. The clock signal generation circuit according to claim 1, wherein the lock-up time τ1 of the first PLL circuit and the lock-up time τM of the second PLL circuit satisfy τ1 ≧ τM.   The clock signal generation circuit according to claim 1, wherein the first PLL circuit and the frequency divider circuit are configured by integer frequency division. The second PLL circuit is plural,
The clock signal generation circuit according to claim 1, further comprising a selection circuit that selects one of the plurality of second PLL circuits.   The clock signal generation circuit according to claim 1, further comprising a high-speed signal processing circuit that performs high-speed signal processing on a high-speed signal input from the outside using the clock signal generated by the second PLL circuit as a drive signal.

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