JPS63290409A - Frequency division circuit - Google Patents

Abstract

PURPOSE:To simply execute the frequency division of non-integral numbers by providing a clock phase switch, a 1/N frequency divider and a 2nd frequency divider applying further 1/2 frequency division to the output and giving the result to the clock phase switch. CONSTITUTION:A clock signal S1 whose duty is 50% is given to a clock phase switch 10, and an EK-OR gate 7 applies 180 deg. phase shift to the phase when the logic level of a phase switching signal S4 is at 'H' and 0 deg. phase shift when the level is at 'L' so as to send a clock S2 to a 1st frequency divider 3a. The 1st frequency divider 3a is a 1/3 frequency divider and its output becomes a clock signal S3 of the 2nd frequency divider 3b. Since a J-KFF8f applies toggle operation at the leading of the clock signal S3, the clock signal S4 goes to 'L' and the phase shift is switched to 0 deg. by the clock phase switch 10. Thus, the clock signal S3 falls down after a period T/2 elapses and the period reaches 2.5T(sec), then a non-integral number frequency divider is attained.

Description

Detailed Description of the Invention [Field of Industrial Application] This invention provides a clock signal having a non-integer frequency division ratio and an odd number division ratio with a duty ratio of 50% for the repetition frequency of an input clock signal. This relates to a frequency dividing circuit that can perform

[Conventional technology]

Figure 4 shows an example of a conventional non-integer frequency divider circuit.
In the figure, 1 is a clock signal input terminal into which a clock signal fi is input, 2v'i is a clock multiplier circuit that doubles the clock signal input to input terminal 1 to 2fi, and 3 is a multiplier of this clock multiplier circuit 2. A frequency divider that divides the signal output 2fi into 1/(2N-t), 4 is this frequency divider 3
This is an output terminal for the frequency-divided signal output (f i /N --L) from the . Here, N is an integer greater than or equal to 2, so 2N-1 is an odd number, for example, N=
If it is 3, then 2N-1 becomes 5, which is an odd number.

Further, the above N-172 indicates that it is a non-integer; for example, when N=3, N-1/2 becomes 2.5, which is a non-integer.

5a of the clock multiplier circuit 2 is a buffer gate that temporarily stores the input clock signal f1, 6 is a delay line that delays the signal from this buffer gate 5a, and 5b is a buffer that temporarily stores the signal from this delay line 6 again. Gate,
7 is an exclusive OR gate (hereinafter referred to as EX-) which inputs the delayed and temporarily stored signal from this buffer gate 5b and the clock signal f1 from the clock signal input terminal 1. It is called an OR gate).

8a, 8b, and f3c in the frequency divider 3 are J-fluid lag flop circuits (hereinafter referred to as J-KFF),
Among them, the J-KFF 8a receives a multiplied signal output 2fi from the clock multiplier circuit 2 and an output signal from the J-KFF 8C, which will be described later.

Further, the J-KFF 13b receives the multiplied signal output 2fi from the clock multiplier circuit 2 and the output signal from the J-KFF 3a. 9 is a negative OR circuit (NOR gate, hereinafter referred to as NOR gate) which inputs the output signal of this J-KFF 9b and the output signal of the J-KFF 8a;
J-KFF8c inputs the multiplied signal output 2fi of the clock multiplier circuit 2 and the output signal of this NOR gate 9,
It is configured to input the output signal to the J-KFF 3a.

Next, the operation will be explained with reference to the configuration diagram in FIG. 4 and the timing chart in FIG. 5.

The block diagram shown in FIG. 4 shows an example of the configuration of a conventional frequency dividing circuit that divides the input clock signal frequency fi by a non-integer, for example, 1/2.5. The clock multiplier circuit 2 receives an input clock signal input from the clock signal input terminal 1 with a duty ratio of 1/2).
Then, this clock signal (a) is converted into a clock period T (sec) i by a delay line 6 and buffers 5a and 5b.
EX-OR the exclusive OR of C with the delayed clock signal (b) that gives a delay Δt of period T/2 (sec).
2 having a frequency 2fi (Hz) that is twice the input clock signal frequency fi (Hz) is obtained by gate 7.
A double clock signal (c) is output and sent to the frequency divider 3.

Frequency divider 3 includes J-KFF8a to 8c and Non, gate 9
It is a 115 frequency divider consisting of 2 times the clock signal ←−
1 (frequency 2fi (Hz)) is divided by 115, and a divided clock signal (g) of frequency f i /2.5 (Hz) is sent to output terminal 4 of the frequency divided clock.

By adding the clock multiplier circuit 2 that doubles the frequency of the clock signal, in order to realize a frequency division ratio that can be a fraction of 0.5, the clock signal period can be reduced because a general frequency divider can only divide the frequency by an integer. This is to obtain a non-integer frequency division ratio with respect to the original clock signal period by doubling the frequency division ratio by 1/2 (double the frequency) KL and converting it into an integer.

Let m be the division ratio with a fraction, and let N be an integer greater than or equal to 2, then ■ m=N　-- Therefore, the frequency division ratio of frequency divider 3 is becomes.

In this case, in exchange for giving a frequency division ratio that is about 1/2 smaller than the integer frequency division ratio N, the circuit operating speed will be doubled, so a frequency division ratio that is close to twice the frequency division ratio N is required. becomes.

[Problems to be solved by the invention] Since the conventional frequency divider circuit is configured as described above, the clock multiplier circuit 2 is required to perform fractional frequency division in non-integer numbers). The operating frequency of the clock multiplier circuit 2 increases, resulting in an increase in power consumption and disadvantages in the operating speed of the multiplier circuit. 2 of the circuit that performs
The problem was that the value had to be nearly doubled, the circuit scale had to be increased, and the price would be extremely high.

This invention was made to solve the above-mentioned problems. Non-integer frequency division eliminates the need for a multiplier circuit, does not increase the operating frequency of the multiplier circuit, and reduces the frequency division ratio of the internal frequency divider. By suppressing the , the circuit scale is extremely small,
The purpose is to obtain a frequency dividing circuit with low power consumption and low cost.

[Means for solving problems]

The frequency dividing circuit according to the present invention includes a clock phase switch that shifts the phase of a clock signal using a phase switching signal, a first frequency divider that divides the output of the clock signal by l/N, and the first frequency divider. and a second frequency divider which further divides the output by 1/2 and inputs the resulting output to the clock phase switch.

[For production]

The second frequency divider and phase switch in this invention control the phase of the clock signal input to the first frequency divider to be shifted by 180' every time the divided output signal rises, thereby 1/2 time slot (compared to when not switching)
The frequency division period of the first frequency divider is shortened by a clock period) (T/2 (sec)) to provide a fractional frequency division ratio.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is a clock signal input terminal for inputting a clock signal S1 having a frequency of fi (Hz), and 10 is a clock signal input terminal for switching the phase of the clock signal S1 from the clock signal input terminal 1 by a phase switching signal S4, which will be described later. The clock phase switch is configured to obtain an output signal S2 by means of a T;X-OR gate 7.

3a is the output signal S2 of the clock phase switch 10.
/N, and is configured to obtain an output signal S8 by two J-KFFs 8d and 8e.

A second frequency divider 3b divides the output signal S8 of the first frequency divider 3a into 1/2, and is configured to obtain a phase switching signal S4 using a J-KFF 8f.

4 is an output terminal of the output signal S8 of the first frequency divider 3a,
Output signal fi/(N −1/2) of non-integer frequency division
It is configured so that it can be taken out.

Reference numeral 13 denotes an output terminal of the phase switching signal S4 of the second frequency divider 3b, which is configured to be able to output an odd frequency divided clock fi/(2N-1).

Next, the operation of one embodiment of the present invention will be explained with reference to the configuration diagram in FIG. 1 and the timing diagram in FIG. 2.

An embodiment of the present invention shown in FIG. 1 shows a circuit that obtains the same non-integer frequency division ratio of 1/2.5 as the conventional circuit (FIG. 4). That is, the clock signal S1 with a duty ratio of 50 inputted from the clock signal input terminal 1 in the figure is as follows.
When the logic level of the phase switching signal S4 inputted to the clock phase switching device 10 and described later is "H", the phase tl-180°
When it is “L”, the deviation of Oo is nx-o gate 7
This is done by the function of the clock signal S2 which causes the first frequency divider 3a to operate.

The first frequency divider 3a is 1/3 by J-KFF8d to 3e.
If the frequency divider does not have the clock phase switch 10 and is operated directly by the input clock signal S1, 85 in FIG.
As shown in the figure, the clock period T (sec)K has a clock period of 3T (sec).

In one embodiment of the present invention, since the phase switching signal S4 is at the "H" level at points ■ to ■ in FIG. At the 0 point after period 2 T (sec), l/
The clock signal S8 whose frequency has been divided by 3 rises.

The clock signal S8 is connected to the second frequency divider 3b,
Since the J-KFF 8f performs a toggle operation when the clock signal S8 rises at 9, the clock signal S4 changes to the "L" level at the 0 point. As a result, the clock phase switch 10 switches the phase shift to O0, so that the divided clock signal S8 that rises at the 0 point rises after a period T (sec) has elapsed from the 0 point like the clock signal S5. Rather than falling, it falls at the 0 point after a period of T/2 (sec), and the period is 2.5T (see).

That is, the clock phase switch 10 is controlled by the second frequency divider 3b during the period of frequency division at the falling edge of the clock signal St (between ■ and ■) and the period during which the frequency is divided at the rising edge of the clock signal St (between ■ and ■). By alternately creating
2 (sec), creating a non-integer frequency division period.

In this invention, if the fractional frequency division ratio m=N-1/2, the frequency division ratio of the first frequency divider 3a is N, which is the same as in the conventional example, but in the conventional circuit (2N-1 ), it can be seen that the present invention requires only a minimum value.

Further, when paying attention to the phase switching signal 84, an odd frequency division output of 175 frequency division with a duty ratio of 50% appears at the output terminal 13 of the odd frequency division clock signal. A general odd integer frequency divider circuit operates only on the rising or falling edge of the operating clock signal, so the duty ratio is 50%.
Since it is not possible to obtain an operating output of 50%, when used in a circuit device that requires a 50% duty ratio, the
A % duty conversion circuit was added.

In the embodiment of the present invention, a frequency-divided output signal having a duty ratio of 50% and an odd division ratio of 1/(2N-1), such as the phase switching signal S4, can be obtained without adding any circuit.

In the above embodiment, E is used as the clock phase switch 10.
In this case, the circuit configuration is very simple, but in order to accurately shift the phase of the clock signal by 180 degrees, the duty ratio of the input clock signal S1 is 50. limited to %. In this clock phase switch 10, 1
Any device that can switch and output signals with a phase difference of 80° may be used. For example, as shown in the block diagram shown in FIG. 3, the input clock signal 81 has a period of T/2 (5ec).
is applied to the terminals Xo and Xl of the selection circuit 12, and the first
Phase switching signal S sent out from the second frequency divider 3b shown in the figure
4 is input, and the operation clock signal S2 of the first frequency divider 3a is sent from the selection output terminal Z. In this case, since the EX-0 gate 7 does not shift the phase, the duty ratio of the input clock signal S1 does not matter much.

Regarding the first and second frequency dividers 3a and 3b, in the above embodiment, J-KFFgd to 8f are used, but frequency dividers that can realize the same operation, such as a D flip-flop or a T flip-flop, are used. , a logic element such as a shift register, or a ring counter type may be used.

〔Effect of the invention〕

As described above, according to the present invention, since the frequency dividing circuit is configured by the clock phase switcher, the first frequency divider, and the second frequency divider, it can be used as a non-integer frequency division means as in the conventional method. This eliminates the need for a multiplier circuit that increases the frequency, and the division ratio can be kept to a minimum. Small-scale circuits and low power consumption make the equipment inexpensive, and odd-number divided output with a duty ratio of 50% is easily possible. There are benefits to be gained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a frequency dividing circuit according to an embodiment of the present invention, FIG. 2 is an operation timing diagram of the same embodiment, and FIG. 3 is a block diagram showing another embodiment of the clock phase switch of the present invention. , FIG. 4 is a block diagram of the conventional example, and FIG. 5 is an operation timing diagram of the conventional example. 3a is a first frequency divider, 3b is a second frequency divider, 6 is a delay line, 7
1 is an EX-OR gate (exclusive OR circuit), 10 is a clock phase switch, Ila and 11b are differentiating circuits, 12 is a selection circuit, Sl is a clock signal, and S4 is a phase switching signal. In addition, in the drawings, the same reference numerals indicate the same or corresponding parts. Patent applicant: Mitsubishi Electric Corporation (2 others) - -rQl') dimension -N (> dimension
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Claims (3)

[Claims] (1) A clock phase switch that inputs a clock signal and a phase switch signal and shifts the phase of the input clock signal by 0 degrees or 180 degrees, and a clock phase switch that inputs the output signal of this clock phase switch and a first frequency divider that performs frequency division by N; and inputting the output signal of the first frequency divider, dividing the frequency by 1/2, and inputting the output signal as a phase switching signal to the clock phase switching device. A frequency dividing circuit comprising a second frequency divider. (2) The clock phase switch is constituted by an exclusive OR circuit that inputs the clock signal and the frequency-divided output signal from the second frequency divider as a phase switching signal. Frequency divider circuit according to range 1. (3) The clock phase switch includes two differentiating circuits that differentiate a delay line that gives a delay of T/2 to the clock signal and a line that does not give a delay to the clock signal, and these two differentiating circuits. 2. The frequency dividing circuit according to claim 1, further comprising a selection circuit inputting the respective outputs of the frequency divider and the phase switching signal from the second frequency divider.