JPH09223951A - Delay circuit and signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a delay circuit with which the propagation delay time of pulse signal can be extremely easily shortened. SOLUTION: Concerning a delay circuit 2 constituted by successively connecting plural inverters L1, L2..., 2nd inverters K1, K2... are provided respectively corresponding to the respective inverters L1, L2..., the input terminal of an inverter Kn at an n-th step and the input terminal of an inverter Ln corresponding to it are mutually connected and further, the output terminal of the inverter Kn at the n-th step is connected to the input terminal of an inverter Ln+3 connected while being separated forward from the correspondent inverter Ln just for three inverters at the relevant delay circuit 2. Concerning such a delay circuit 2, since the inverting operations of inverters L4, L5... are started in advance by the outputs of the 2nd inverters K1, K2..., when an input signal SIN is inputted to the input terminal of the inverter L1 at the 1st step, the propagation delay time of the pulse signal is shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit formed by connecting a plurality of inverting circuits, and a signal processing device having the delay circuit.

[0002]

2. Description of the Related Art Conventionally, there is provided a delay circuit in which a plurality of inverting circuits (inverters) are connected, and signal processing is performed with the inverting operation time of each inverting circuit (that is, the signal propagation delay time by each inverting circuit) as the time resolution. As a signal processing device to perform,
For example, there is a variable delay device (programmable delay line) that delays and outputs an input signal by a time corresponding to external data.

That is, this type of variable delay device inputs a signal to be delayed to an inversion circuit at the first stage of the delay circuit and configures the delay circuit as disclosed in, for example, Japanese Patent Laid-Open No. 5-129910. By increasing or decreasing the number of connected inversion circuits according to the external data, the delayed signal obtained by delaying the input signal by the time corresponding to the external data is extracted from the final stage inversion circuit of the delay circuit. It is known that instead of changing the number of connected inversion circuits in a circuit, an inversion circuit for extracting a delay signal is changed according to external data.

According to such a variable delay device, the delay signal obtained by delaying the input signal can be obtained with the inversion operation time of one inversion circuit forming the delay circuit as the minimum time resolution. Still further, conventionally, as a signal processing device having a delay circuit in which a plurality of inverting circuits are connected like the variable delay device, a phase difference between pulse signals input from outside at different timings is encoded. There is known a pulse phase difference encoding device and a digitally controlled oscillation device configured to generate and output an oscillation signal corresponding to digital data from the outside.

That is, a pulse phase difference encoding device is disclosed in, for example, Japanese Patent Laid-Open No. 3-220814 and Japanese Patent Laid-Open No. 60-253.
As disclosed in Japanese Patent Publication No. 994, the first pulse signal is input to the inverting circuit at the first stage of the delay circuit, and when the pulse signal is input next, the input pulse reaches in the delay circuit. The inversion circuit is detected, and the number of connected inversion circuits from the first stage to the inversion circuit is encoded to obtain digital data corresponding to the phase difference of the pulse signals.

Further, as disclosed in, for example, Japanese Unexamined Patent Publication No. 7-106923, the digital device controlled oscillator inputs a pulse signal to an inversion circuit at the first stage of the delay circuit to propagate the pulse signal in the delay circuit. To start the operation, and after that, the oscillation signal is output when the pulse signal is output from the inversion circuit of the connection position corresponding to the digital data in the delay circuit, and the digital data is updated. Thus, the oscillation signal is output at a cycle corresponding to the digital data.

As a delay circuit used in a pulse phase difference encoder and a digitally controlled oscillator, the above-mentioned Japanese Patent Laid-Open No.
As disclosed in JP-A-220814 and JP-A-7-106923, a pulse circulating circuit having a configuration in which a plurality of inverting circuits are connected in a ring shape and sequentially inverting and circling a pulse signal by each inverting circuit By using, the pulse phase difference can be encoded and the oscillation signal can be output, respectively, even if the number of inverting circuits forming the delay circuit is small.

That is, in the pulse phase difference encoder, the total number of inverting circuits through which the pulse signal propagates is detected by the delay circuit between the input of the first pulse signal and the input of the next pulse signal. Then, by encoding the total number, digital data corresponding to the phase difference of the pulse signal is obtained. Therefore, when a pulse circulation circuit is used as the delay circuit, how many times the pulse signal has circulated on the pulse circulation circuit between the input of the first pulse signal and the input of the next pulse signal. , And by detecting which inverting circuit on the pulse circulation circuit the pulse signal reaches, the pulse signal propagates (that is, the inverting operation is performed).
Since the total number of inverting circuits is known, digital data corresponding to the pulse phase difference can be obtained even if the number of inverting circuits connected is small.

In addition, in the digital control oscillator, when the total number of inverting circuits to which the pulse signal propagates in the delay circuit reaches the value corresponding to the digital data after outputting the oscillation signal this time, the next oscillation signal is output. By repeating such an operation, an oscillation signal having a cycle corresponding to digital data is output. Therefore, when the pulse circulation circuit is used as the delay circuit, the time interval (that is, the oscillation cycle) from the time when the oscillation signal is output this time to the next output is defined as the number of circulations of the pulse signal on the pulse circulation circuit. , Outputting the oscillation signal of the cycle corresponding to the digital data, even if the number of connected inverting circuits is small, by designing by the digital data that represents the arrival position of the pulse signal on the pulse circulation circuit. Will be able to.

Further, according to the pulse phase difference encoding device and the digital control oscillating device as described above, the pulse is obtained with the time resolution determined by the delay time (inversion operation time) of each inverting circuit forming the delay circuit. Since the phase difference can be detected or the oscillation frequency can be controlled, the pulse phase difference detection accuracy or the oscillation frequency control accuracy can be improved.

Further, since the pulse phase difference encoding device and the digital control oscillation device can detect the pulse phase difference or control the oscillation frequency with high precision, for example, Japanese Patent Laid-Open No. 7-183800. JP-A-7-28
As disclosed in Japanese Patent No. 3722, a frequency conversion device which combines a pulse phase difference encoding device and a digital control oscillation device, and divides or multiplies an external reference signal to output an oscillation signal of a predetermined frequency. Or a PLL (Phase Locked Lo) that outputs an oscillation signal synchronized with an external reference signal.
op) By configuring the device, it is possible to realize a highly accurate frequency conversion device and a PLL device.

[0012]

By the way, in order to improve the time resolution when performing signal processing in the above-mentioned various signal processing devices, the inverting operation of each inverting circuit constituting the delay circuit is set fast. Then, it is necessary to shorten the propagation delay time of the pulse signal. Then, in order to reduce the time, a method of finely processing an LSI forming an inverting circuit can be considered.

However, in order to finely process an LSI, a huge amount of equipment and an extremely advanced manufacturing technique are required, which cannot be easily realized. Therefore, in the above-described conventional signal processing device that performs signal processing using a delay circuit in which a plurality of inverting circuits are connected, there is a limit in improving the time resolution.

The present invention has been made in view of the above problems, and it is possible to extremely easily reduce the propagation delay time of a pulse signal, and a time resolution of signal processing using the delay circuit. An object is to provide a signal processing device that can be improved.

[0015]

Means for Solving the Problems and Effects of the Invention A delay circuit according to the present invention as set forth in claim 1 for achieving the above object comprises a plurality of first inversions for inverting and outputting an input signal. It is configured by connecting circuits, and basically, a pulse signal is propagated by sequentially inverting the output of each first inverting circuit.

Here, in the delay circuit of the present invention, the second inverting circuit is provided in correspondence with the predetermined first inverting circuit, and the input terminal of the second inverting circuit and the predetermined first inverting circuit are provided.
The input terminals of the inverting circuit are connected to each other. Further, the output terminal of the second inverting circuit is connected to the input terminal of the first inverting circuit which is connected to the predetermined first inverting circuit by three or more and an odd number of destinations in the delay circuit. There is.

Therefore, in the delay circuit, the predetermined first
When the output of the first inverting circuit connected to the preceding stage of the inverting circuit is inverted, the output of the second inverting circuit is inverted together with the output of the predetermined first inverting circuit, and the output of the second inverting circuit With the inversion, the first inversion circuit to which the output of the second inversion circuit is input in the delay circuit tries to start the inversion operation earlier.

Therefore, according to the delay circuit of the present invention, L
The propagation delay time of the pulse signal can be shortened as compared with the conventional configuration in which the second inversion circuit is not provided, without using a special manufacturing technique such as SI fine processing. Next, the delay circuit according to claim 2 is configured as a pulse circulation circuit in which a plurality of first inversion circuits are connected in a ring shape, and the pulse signal is sequentially inverted by each first inversion circuit to rotate. Let

Here, also in the delay circuit as the pulse circulating circuit according to the second aspect, the second inverting circuit is provided corresponding to the predetermined first inverting circuit, and the input terminal of the second inverting circuit is provided. And an input terminal of the predetermined first inverting circuit are connected to each other, and an output terminal of the second inverting circuit is connected to the output terminal of the predetermined first inverting circuit from the predetermined first inverting circuit in the delay circuit.
It is connected to the input terminals of the first inverting circuits which are connected more than one and an odd number first.

Also, according to the delay circuit of the second aspect, the propagation delay time of the pulse signal can be extremely easily shortened, just like the delay circuit of the first aspect. Further, since the delay circuit according to claim 2 is configured as a pulse circulation circuit for circulating a pulse signal,
If the pulse phase difference encoding device or the digitally controlled oscillator described above is configured using the delay circuit, even if the number of the first inverting circuits configuring the delay circuit is small, the pulse phase difference encoding or oscillation is performed. It becomes possible to output a signal.

Next, in the delay circuit according to claim 3, in the delay circuit according to claim 2, a specific first inverting circuit among the first inverting circuits constituting the delay circuit is
It is configured as a starting inverting circuit capable of controlling the inverting operation of the input signal by a control signal from the outside.

According to this delay circuit, the inversion operation of the starting inversion circuit is stopped by the control signal input from the outside, so that the pulse signal circulation operation of the delay circuit (pulse circulation circuit) is forcibly stopped. Can be made. Therefore, according to the delay circuit of claim 3,
When it is unnecessary to circulate the pulse signal, it is possible to stop the entire operation of the delay circuit to reduce the current consumption, and also to initialize the output level of each inverting circuit forming the delay circuit. it can.

Next, the signal processing device according to claim 4 is
The delay circuit according to claim 1 is provided, and an input signal from the outside is input to the first inverting circuit at the first stage of the delay circuit, and output from any one of the first inverting circuits forming the delay circuit. A delayed signal obtained by delaying the input signal by the delay time determined by the number of connected first inverting circuits from the first inverting circuit at the first stage to any one of the first inverting circuits. Is configured to be taken out as. And, the changing means, depending on the data from the outside,
The number of connected first inverting circuits from the first inverting circuit at the first stage to the first inverting circuit that extracts the delay signal is changed.

That is, the signal processing device according to the fourth aspect is configured as a variable delay device which delays an input signal by a time corresponding to external data and outputs the delayed signal.
Further, according to this signal processing device, since the delay circuit according to claim 1 is used, it is possible to output a delayed signal obtained by delaying the input signal with a time resolution of a smaller value.

When the delay signal is taken out from the first inverting circuit at the final stage of the delay circuit, the changing means uses the number of connected first inverting circuits forming the delay circuit as the external data. It may be configured to increase or decrease according to the number.
On the other hand, if the number of connected first inverting circuits in the delay circuit is fixed, the changing means selectively selects the first inverting circuit for extracting the delay signal according to the external data. It can be configured as one that does.

Next, the signal processing device according to claim 5 is
A pulse which is provided with the delay circuit according to any one of claims 1 to 3, and is sequentially output from a plurality of first inversion circuits which are predetermined among the first inversion circuits which constitute the delay circuit. Predetermined signal processing is performed with the phase difference time of the signal as a unit.

According to this signal processing device, since the signal processing is performed using the delay circuit according to any one of claims 1 to 3, it is possible to process the signal with a small time resolution. . By the way, examples of the signal processing device according to claim 5 include the devices according to claims 6 to 9.

That is, the signal processing device according to the sixth aspect is
A pulse signal which is provided with the delay circuit according to any one of claims 1 to 3, and which is sequentially output from a plurality of first inversion circuits which are predetermined among the first inversion circuits forming the delay circuit. It is configured as a pulse phase difference encoding device that encodes the phase difference of a pulse signal input from the outside at different timings with the phase difference time as a unit. According to this signal processing device, since the delay circuit according to any one of claims 1 to 3 is used, the propagation delay time of the pulse signal is short. Can be encoded.

Further, the signal processing device according to claim 7 is
A pulse signal which is provided with the delay circuit according to any one of claims 1 to 3, and which is sequentially output from a plurality of first inversion circuits which are predetermined among the first inversion circuits forming the delay circuit. The phase difference time is used as a unit to generate an oscillation signal corresponding to frequency control data input from the outside, and output the generated oscillation signal as a digitally controlled oscillator. Further, according to this signal processing device, since the delay circuit according to any one of claims 1 to 3 is used, the propagation delay time of the pulse signal is short, so that the oscillation signal can be obtained with a smaller time resolution. Frequency control can be performed.

On the other hand, the signal processing circuit according to claim 8 is
A pulse signal which is provided with the delay circuit according to any one of claims 1 to 3, and which is sequentially output from a plurality of first inversion circuits which are predetermined among the first inversion circuits forming the delay circuit. A digitally controlled oscillator that generates an oscillation signal corresponding to frequency control data input from the outside with the phase difference time as a unit and outputs the generated oscillation signal,
A pulse signal which is provided with the delay circuit according to any one of claims 1 to 3, and which is sequentially output from a plurality of predetermined first inverting circuits among the first inverting circuits constituting the delay circuit. The pulse phase difference encoding device for encoding the cycle of the reference signal input from the outside in the unit of the phase difference time of, and the data generating means, and the data generating means is the pulse phase difference encoding device. Based on the encoded period data of the reference signal, the digital control oscillator generates frequency control data for outputting an oscillation signal that is a predetermined number of times the frequency of the reference signal, and the generated frequency control data is digitally controlled. Output to oscillator. Then, the signal processing device outputs the oscillation signal from the digitally controlled oscillator as an output signal obtained by frequency-converting the reference signal.

That is, the signal processing device according to the eighth aspect is configured as a frequency conversion device that divides or multiplies a reference signal from the outside and outputs an oscillation signal of a predetermined frequency. Further, according to this signal processing device, since the delay circuit according to any one of claims 1 to 3 is used, the propagation delay time of the pulse signal is short. Since it is possible to perform the encoding of the period and the frequency control of the oscillation signal, it is possible to perform highly accurate frequency conversion.

The signal processing apparatus according to claim 9 is
A pulse signal which is provided with the delay circuit according to any one of claims 1 to 3, and which is sequentially output from a plurality of first inversion circuits which are predetermined among the first inversion circuits forming the delay circuit. A digitally controlled oscillator that generates an oscillation signal corresponding to frequency control data input from the outside with the phase difference time as a unit and outputs the generated oscillation signal,
A pulse signal which is provided with the delay circuit according to any one of claims 1 to 3, and which is sequentially output from a plurality of predetermined first inverting circuits among the first inverting circuits constituting the delay circuit. The pulse phase difference encoding device for encoding the phase difference between the externally input reference signal and the oscillation signal in units of phase difference time, and the data generating means, the data generating means Based on the phase difference data between the reference signal and the oscillation signal encoded by the phase difference encoding device, frequency control data for synchronizing the phase of the reference signal and the oscillation signal is generated, and the frequency control data is digitally controlled. Output to oscillator. Then, the signal processing device outputs the oscillation signal from the digitally controlled oscillator as an output signal that is phase-synchronized with the reference signal.

That is, the signal processing device according to the eighth aspect is configured as a PLL device which outputs an oscillation signal synchronized with a reference signal from the outside. Further, according to this signal processing device, since the delay circuit according to any one of claims 1 to 3 is used, the propagation delay time of the pulse signal is short. Since it is possible to encode the phase difference between the oscillation signal and the oscillation signal and control the frequency of the oscillation signal, it is possible to realize a highly accurate PLL device.

In the signal processing device according to claim 8 or 9, each of the digital control oscillation device and the pulse phase difference encoding device has a delay according to any one of claims 1 to 3. Although it may be configured to include a circuit, if the digital control oscillator and the pulse phase difference encoder are configured to include one delay circuit in common as described in claim 10, The device configuration can be simplified and the size can be reduced. Moreover, the time resolutions of the digitally controlled oscillator and the pulse phase difference encoder can be completely matched, so that the accuracy of signal processing can be further improved.

[0035]

Embodiments of the present invention will be described below with reference to the drawings. It is needless to say that the embodiments of the present invention are not limited to the following examples, and can take various forms as long as they belong to the technical scope of the present invention.

[First Embodiment] First, the delay circuit 2 of the first embodiment will be described with reference to FIGS. FIG.
As shown in (A), the delay circuit 2 of the first embodiment includes a first inverter circuit group including a plurality of inverters L1, L2, L3, ... And a plurality of inverters K shown by hatching in the figure.
, K2, K3, ... And a second inverting circuit group. And, in each of the inverters L1, L2, L3, ... Which constitute the first inverting circuit group, the output terminal of the preceding stage is sequentially connected to the input terminal of the next stage in a line. That is, in the delay circuit 2 of the present embodiment, the portion including the first inverting circuit group (inverters L1, L2, L3, ...)
It constitutes a conventional delay circuit 2'shown in FIG. 1 (B).

On the other hand, the inverters K1, K2, K3, ... Forming the second inverting circuit group are provided corresponding to the inverters L1, L2, L3, ... Forming the first inverting circuit group, respectively. Therefore, the input terminal of the first-stage inverter K1 and the input terminal of the inverter L1 are connected, the input terminal of the second-stage inverter K2 and the input terminal of the inverter L2 are connected, and so on. Inverter K
The n input terminal and the corresponding input terminal of the inverter Ln are connected to each other. In addition, the inverter K1
Is connected to the input terminals of the inverters L4 and K4, and the output terminal of the inverter K2 is connected to the inverters L5 and K5.
The output terminal of the n-th stage inverter Kn forming the second inverting circuit group is connected to the input terminal of
It is connected to the input terminal of the inverter Ln + 3 connected in advance.

According to the delay circuit 2 of this embodiment having such a configuration, the propagation delay time of the pulse signal can be shortened as compared with the conventional delay circuit 2'shown in FIG. 1 (B). That is, first, in the conventional delay circuit 2 ′, when the input signal SIN is input from the outside to the input terminal of the first-stage inverter L1, the inverters L1, L2, L3, ... , The pulse signals are sequentially inverted and propagated, and the inverters L1, L2, L3, ...
Output delay signals (delay pulses) P1, P2, P3, ... According to the number of connected inverters.

On the other hand, the delay circuit 2 of the present embodiment basically performs the same operation as the conventional delay circuit 2 ', but an input signal from the outside is input to the input terminal of the inverter L1 in the first stage. When SIN is input, the inverter L1 and the inverter K1 invert, and the inverter K1
Since the inverter L4 tries to directly invert the output by the output of, the inverter L4 starts the inversion operation earlier than in the case of the conventional delay circuit 2 '. Furthermore, when the output of the inverter L1 is inverted, the inverter K2 operates to invert, and the output of the inverter K2 causes the inverter L to operate.
5 starts the inversion operation, and thereafter, similarly, the inverters K3,
As K4, K5, ... Invert, the inverter L
6, L7, L8, ... Try to start the inversion operation.

As described above, according to the delay circuit 2 of this embodiment, the second inverting circuit group (inverters K1, K2, K3,
..) causes the inversion operation of the inverters L4, K5, L6, ... In the fourth and subsequent stages of the first inversion circuit group to start earlier, so that the propagation delay time of the pulse signal becomes shorter.

Here, in order to clarify the difference between the delay circuit 2 of this embodiment and the conventional delay circuit 2 ', FIG. 2 shows a result of simulating the circuit operation of each of the delay circuits 2 and 2'. Show. 2A shows the result of the delay circuit 2 of this embodiment, and FIG. 2B shows the result of the conventional delay circuit 2 '.

As is apparent from FIG. 2, the delay signals P7, P8, P are inputted after the high level input signal SIN is inputted.
9, the time until the level changes, and the delay signal P
4, P5, P6, ... Each have a time interval (that is, a phase difference of the delay signal P) in which the level of the delay signal 2'changes.
It can be seen that the delay circuit 2 of this embodiment is shorter than the delay circuit 2 of this embodiment.
This is because the second inverting circuit group starts the inverting operation of the first inverting circuit group earlier, as described above.

As described above, according to the delay circuit 2 of the present embodiment, the propagation delay time of the pulse signal can be shortened as compared with the conventional configuration without using a special manufacturing technique such as LSI microfabrication. be able to. [Second Embodiment] Next, as a second embodiment, a variable delay device 6 for delaying an input signal by a time corresponding to external data and outputting the same will be described with reference to FIG.

As shown in FIG. 3, the variable delay device 6 of this embodiment outputs from the delay circuit 2 of the first embodiment and the inverters L1, L2, L3, ... Of the delay circuit 2, respectively. A pulse selector 4 which receives the delay signals P1, P2, P3, ... And selectively selects the delay signal corresponding to the select data DS from the outside and outputs it as the output signal SOUT. There is. If the decimal value of the select data DS is “n”, the pulse selector 4 connects the inverter L connected to the nth stage in the delay circuit 2.
The delayed signal Pn from n is output as the output signal SOUT.

In the variable delay device 6 of this embodiment as described above, for example, the select data D whose decimal value is "8" is
If S is input to the pulse selector 4 and the input signal SIN is input to the first stage inverter L1 of the delay circuit 2, the pulse selector 4 outputs the signal at the timing when the output of the eighth stage inverter L8 is inverted in the delay circuit 2. The output signal SOUT of changes the level. In this way, the variable delay device 6 of this embodiment is
According to the above, each inverter L1, L2, L of the delay circuit 2 is
The output signal SOUT obtained by delaying the input signal SIN can be obtained with the time interval (that is, the phase difference) of the delay signals P1, P2, P3, ... When the decimal value of the select data DS is odd, the output signal SOUT changes its level in the direction opposite to the level change of the input signal SIN.

As described above, in the delay circuit 2 of the first embodiment, since the propagation delay time of the pulse signal is small and the time interval for changing the level of each delay signal P is also small, this delay circuit 2 is used. According to the variable delay device 6 of this embodiment, the output signal SOUT can be obtained by delaying the input signal SIN with a smaller time resolution.

In this embodiment, the number of connected inverters in the delay circuit 2 is fixed, and the pulse selector 4 as the changing means selects the inverter for taking out the output signal SOUT. When the output signal SOUT is taken out from the final stage inverter of the delay circuit 2, the number of connected inverters forming the delay circuit 2 may be increased or decreased according to external data. .

[Third Embodiment] Next, as a third embodiment,
A ring oscillator 8 as a pulse circulation circuit that sequentially inverts and circulates a pulse signal will be described with reference to FIGS. 4 and 5. First, as shown in FIG. 4A, the ring oscillator 8 according to the present embodiment includes a NAND gate LN1 as a starting inverting circuit and 14 inverters LI2 to L1.
It is composed of a first inverting circuit group consisting of I15, two NAND gates KN1, KN14, one NOR gate KN15, and a second inverting circuit group consisting of twelve inverters KI2 to KI13. The second inverting circuit group is shown by hatching in FIG. Further, the NOR gate KN15 has one input terminal serving as an inverting input terminal for inverting and inputting the level of the input signal.

Here, a NAND gate LN1 which is an inverting circuit forming the first inverting circuit group and 14 inverters L are provided.
In I2 to LI15, the output terminal of the previous stage is sequentially connected to the input terminal of the next stage in a ring shape, and the NAND gate LN1
The control signal PA from the outside is input to the input terminal which is not connected to the inverter LI15. That is, in the ring oscillator 8 of the present embodiment, the first inverting circuit group (the NAND gate LN1 and the inverters LI2 to LI2.
The portion composed of the LI15) constitutes the conventional ring oscillator 8'shown in FIG. 4 (B).

On the other hand, the NAND gate KN1 and the inverters KI2 to KI, which are the inverting circuits constituting the second inverting circuit group.
13, NAND gate KN14, and NOR gate KN15
Are provided respectively corresponding to the respective inverting circuits forming the first inverting circuit group. That is, the NAND gate KN1 corresponds to the NAND gate LN1 and each of the inverters KI2 to KI1.
3 corresponds to the inverters LI2 to LI13, the NAND gate KN14 corresponds to the inverter LI14, and the NOR gate KN15 corresponds to the inverter LI15.

The two input terminals of the NAND gate KN1 in the first stage are connected to the two input terminals of the NAND gate LN1, respectively, and the input terminal of the inverter KI2 in the second stage is connected to the input terminal of the inverter LI2. The input terminal of the inverter KI3 is connected to the input terminal of the inverter LI3, and so on. The input terminals are the respective inverting circuits (the NAND gate LN1 and the inverter L that compose the first inverting circuit group).
I2 to LI15) of the corresponding inverting circuit. The control signal PA is input to the input terminal of the NAND gate KN14 that is not connected to the inverter LI14 and the input terminal of the NOR gate KN15 that is not connected to the inverter LI15 (the above-mentioned inverting input terminal).

Further, the output terminal of the NAND gate KN1 is connected to the input terminals of the inverters LI4 and KI4,
The output terminals of the inverter KI2 are inverters LI5 and KI
5, the output terminal of the inverter KI3 is connected to the input terminals of the inverters LI6 and KI6,
Thus, the output terminals of the n-th inverting circuit forming the second inverting circuit group are connected three (n + 3) stages ahead of the corresponding inverting circuit in the first inverting circuit group. It is connected to the input terminal of the eye inverting circuit.

According to the ring oscillator 8 of this embodiment having such a configuration, the propagation delay time of the pulse signal can be shortened as compared with the conventional ring oscillator 8'shown in FIG. 4 (B). That is, first, the conventional ring oscillator 8'shown in FIG. 4B will be described. When the control signal PA is at the low level, the NAND gate LN1 is shown.
Output is forced to High level, the output of the inverter LI2 of the next stage becomes Low level, and the output of the inverter LI3 of the next stage becomes High level, so that each inverting circuit sequentially inverts to the NAND gate LN1. Means that a signal of the same level as the output signal is input, and the ring oscillator 8'is stable in this state.

When the control signal PA changes to the high level, the NAND gate LN1 starts the inversion operation, and the inversion operation time in each inversion circuit (that is, the propagation delay time of the pulse signal in each inversion circuit) Td is almost the same. 15 times the time (15.
When Td) has elapsed, a signal of the same level as the output signal is input to the NAND gate LN1 and the NAND gate LN1 is again input.
The operation of inverting the output level of N1 is repeated. Therefore, in this ring oscillator 8 ', the pulse signal is transmitted to each inverting circuit (the NAND gate LN1 and the inverter L).
I2 to LI15) are sequentially inverted and circulate, and each inversion circuit outputs pulse signals P1 to P15 whose levels are inverted at each time (15 · Td).

On the other hand, the ring oscillator 8 of this embodiment basically operates in the same manner as the conventional ring oscillator 8 ', but the first stage NAND gate LN is used.
When a high-level control signal PA is input to the input terminal 1 of the NAND gate KN1, the NAND gate LN1 and the NAND gate KN1 are inverted, and the output of the NAND gate KN1 is used to directly invert the inverter LI4. Inverter LI
4 starts the reversing operation earlier. Further, when the output of the NAND gate LN1 is inverted, the inverter KI2 operates to invert, and the output of the inverter KI2 causes the inverter LI5 to start the inversion operation. Thereafter, similarly, the inverters KI3, KI4, ..., KI12, KI13, the NAND gate Inverter LI6, LI7, ..., LI15, NAND gate LN1, inverters LI2, LI3, ... Try to start the inversion action as KN14, NOR gate KN15 ,.

As described above, according to the ring oscillator 8 of the present embodiment, the second inverting circuit group (the NAND gate KN1, the inverters KI2 to KI13, the NAND gate KN14) is exactly the same as the delay circuit 2 of the first embodiment. , And NOR gate KN15), each inverting circuit (a NAND gate LN1 and an inverter LI2) forming the first inverting circuit group.
Since the inversion operation of ˜LI15) is started earlier, the propagation delay time of the pulse signal is shortened.

In the ring oscillator 8 of this embodiment, 14 out of the inverting circuits forming the second inverting circuit group are used.
The reason why the control signal PA is input to both the inverting circuits KN14 and KN15 with the NAND gate KN14 at the stage and the NOR gate KN15 at the stage 15 is as follows.

That is, the 14th and 15th stages of the second inverting circuit group
If the inverting circuit of the stage is an inverter like the other inverting circuits, when the external control signal PA is at the low level,
Output level of the 14th inverting circuit and NAND gate LN1
Is opposite to the output level of the inverter, and the output level of the inverting circuit of the fifteenth stage is opposite to the output level of the inverter LI2, and the current consumption due to the output short circuit increases. In this embodiment, when the control signal PA is at the low level, the NAND gate KN14
Since the outputs of the NAND gate LN1 and the NAND gate LN1 both become the High level, and the outputs of the NOR gate KN15 and the inverter LI2 both become the Low level, the above-mentioned output short circuit does not occur.

Here, in order to clarify the difference between the ring oscillator 8 of this embodiment and the conventional ring oscillator 8 ', FIG. 5 shows the result of simulating the circuit operation of each of the ring oscillators 8 and 8'. Show. FIG.
Represents pulse signals P1 to P15 output from the respective inverting circuits (the NAND gate LN1 and the inverters LI2 to LI15) that form the first inverting circuit group,
(A) shows the result about the ring oscillator 8 of the present embodiment, and (B) shows the result about the conventional ring oscillator 8 '.

As is apparent from FIG. 5, the phase difference between the pulse signals P1 to P15 output from the respective inverting circuits is shorter in the ring oscillator 8 of this embodiment than in the conventional ring oscillator 8 ', and is approximately half. You can see that.
This is because, as described above, the second inverting circuit group starts the inverting operation of the first inverting circuit group ahead of time. In addition, in FIG. 5, the time t1 is
The gate delay time of two inverting circuits in the ring oscillator 8 of this embodiment is shown, and the value is about 87 ps. Further, the time t2 represents the gate delay time of two inversion circuits in the conventional ring oscillator 8 ', and its value is about 164 ps.

As described above, according to the ring oscillator 8 of this embodiment, the propagation delay time of the pulse signal can be shortened as compared with the conventional configuration without using a special manufacturing technique such as fine processing of LSI. be able to. Then, it is possible to sequentially output the pulse signals P1 to P15 having extremely small phase differences from the respective inverting circuits that form the first inverting circuit group.
In the present embodiment, the output terminals of the respective inverting circuits forming the second inverting circuit group are connected to the input terminals of the inverting circuits connected three units ahead of the corresponding inverting circuit in the first inverting circuit group. Although the connection is made, the gate delay time per one inverting circuit can be shortened to about one-third of that of the conventional one when it is configured to be connected to the input terminal of the inverting circuit 5 units ahead. Can be confirmed by circuit operation simulation.

Further, in the ring oscillator 8 of the above embodiment, a NOR gate KN15 is used instead of the inverter LI2.
The same NOR gate is used and the inverter LI3 is used.
Instead of this, a NAND gate similar to the NAND gate KN14 may be used, and the control signal PA may be input to the other input terminal of the NOR gate and the NAND gate in the same manner as the NOR gate KN15 and the NAND gate KN14. Further, according to this configuration, the first inverting circuit group and the second inverting circuit group are configured by exactly the same inverting circuit, so that the pulse circulation operation is well balanced.

[Fourth Embodiment] In the ring oscillator 8 of the third embodiment, the present invention is applied to a ring oscillator 8'in which an odd number (15) of inverting circuits are connected in a ring shape. However, the present invention can also be applied to a ring oscillator in which an even number of inverting circuits are connected in a ring shape.

Then, next, as a fourth embodiment, as shown in FIG. 6, a ring oscillator 1 including 32 inversion circuits.
For 0 ′, the ring oscillator 10 to which the present invention is applied
Will be described. First, as shown in FIG. 8, the ring oscillator 10 of this embodiment has two NAND gates NAN.
D1, 32 and 30 inverters INV2 to INV3
First inversion circuit group consisting of 1 and two NAND gates K
N1, KN31, one NOR gate KN32, and 29
And a second inverting circuit group composed of individual inverters KI2 to KI30. The second inverting circuit group is shown by hatching. Further, in FIG. 8, the inverters INV7 to INV12, IN forming the first inverting circuit group are arranged.
V21 to INV26 and the inverters KI7 to KI12 and KI21 to KI26 forming the second inverting circuit group are omitted. Further, in the NOR gate KN32, one input terminal is an inverting input terminal for inputting the level-inverted input signal, as in the case of the ring oscillator 8 of the third embodiment.

Here, a NAND gate NAND1 and an inverter INV, which are inverting circuits constituting the first inverting circuit group, are provided.
2 to INV31 and the NAND gate NAND32, the output terminal of the previous stage is sequentially connected in a ring shape to the input terminal of the next stage, and the NAND gate N1 of the NAND gate NAND1.
A control signal PA from the outside is input to the input terminal which is not connected to the AND 32, and the NAND gate NAN
The output signal of the inverter INV18 is input to the input terminal of D32 that is not connected to the inverter INV31 (hereinafter, this input terminal is referred to as a control terminal). Then, on the output side of the inverting circuits connected to the even-numbered stages counting from the NAND gate NAND1, the pulse signals R1 to
A signal terminal for outputting R16 to the outside is provided.

That is, the ring oscillator 10 of the present embodiment.
In the first inverting circuit group (nand gate NAND
1, 32 and the inverters INV2 to INV31) form a conventional ring oscillator 10 'shown in FIG. On the other hand, the NAND gate KN1 and the inverters KI2 to K that are the inverting circuits that form the second inverting circuit group.
I30, NAND gate KN31, and NOR gate KN3
2 is provided corresponding to each inverting circuit forming the first inverting circuit group, just like the case of the ring oscillator 8 of the third embodiment, and the connection state thereof is also that of the third embodiment. It is exactly the same as the case.

That is, the two input terminals of the first-stage NAND gate KN1 are respectively connected to the two input terminals of the NAND gate NAND1, and the input terminal of the second-stage inverter KI2 is connected to the input terminal of the inverter LI2. The input terminal of each inverting circuit forming the second inverting circuit group is connected to the input terminal of the corresponding inverting circuit among the inverting circuits forming the first inverting circuit group. The control signal PA is input to the input terminal of the NAND gate KN31 which is not connected to the inverter LI31 and the input terminal of the NOR gate KN32 which is not connected to the NAND gate NAND32 (the above-mentioned inverting input terminal). The output terminal of the NAND gate KN1 is connected to the input terminals of the inverters INV4 and KI4, and the output terminal of the inverter KI2 is connected to the inverters INV5 and KI5.
The output terminal of the n-th stage inverting circuit forming the second inverting circuit group is connected to the corresponding input terminal of the first inverting circuit group three points ahead of the corresponding inverting circuit in the first inverting circuit group. It is connected to the input terminal of the inverted (n + 3) th inverting circuit.

Next, the operation of the ring oscillator 10 of the fourth embodiment constructed as described above will be explained. First, regarding the operation of the ring oscillator 10 'of FIG. 6 which is a basic part of the ring oscillator 10 of the present embodiment, that is, the ring oscillator composed of an even number of inverting circuits, the above-mentioned JP-A-7-106923. 7, the output P01 of the NAND gate NAND1 is forcibly set to the high level when the external control signal PA is at the low level. Therefore, the NAND gate NAND1 is described in detail. The output of the even-numbered inverting circuit is low level and the output of the odd-numbered inverting circuit is high level and stable. However, in this initial state, the output P18 of the inverter INV18 input to the control terminal of the NAND gate NAND32 is
Since it is at the low level, only the NAND gate NAND32 outputs the high level even though it is connected to the even-numbered stages.

The control signal PA is changed from Low level to Hi.
When changed to the gh level, the ring oscillator 10 'has a
A main edge (edge indicated by a dot in FIG. 7) sequentially transmitted as a falling output of the odd-numbered inverting circuit and a rising output of the even-numbered inverting circuit, and this main edge is output from the inverter INV18 to the NAND gate NAND.
The NAND gate NAND3 is input to the control terminal 32.
As the output P32 of the second inverter is inverted before the output P31 of the inverter INV31, a reset edge that is sequentially transmitted as a rising output of the odd-numbered inverting circuit and a falling output of the even-numbered inverting circuit (in FIG. 7, The edge indicated by X) and the same circle go around.

That is, in the ring oscillator 10 'including the first inversion circuit group, two pulse signals (main edge and reset edge) having different generation timings are circulated on the same circulation, and the NAND gate NAND1 is , The output is inverted by the reset edge before the self-generated main edge returns, and the NAND gate NAND32 inverts the output by the main edge before the self-generated reset edge returns. Although the ring oscillator 10 'is composed of an even number of inverting circuits, it does not enter a stable state and always circulates the pulse signal. Then, from each of the signal terminals of the ring oscillator 10 ′, a time (32 · Td) 32 times the inversion operation time in each inversion circuit (that is, the propagation delay time of the pulse signal in each inversion circuit) Td is set to 1 Pulse signals R1 to R1 having a cycle
6 is output, and the phase difference time Ts of the pulse signals output from the adjacent signal terminals is the inversion operation time T
It is twice as long as d (2 · Td).

On the other hand, the ring oscillator 10 of the present embodiment configured as shown in FIG. 8 basically performs the same pulse circulation operation as the conventional ring oscillator 10 '. Just like the case of the ring oscillator 8 of the third embodiment, since the second inversion circuit group (the NAND gate KN1, the inverters KI2 to KI30, the NAND gate KN31, and the NOR gate KN32) is provided, the conventional ring oscillator 10 'is provided. In comparison, the propagation delay time of the pulse signal becomes shorter.

That is, the ring oscillator 10 of the fourth embodiment.
Also in the NAND gate NA as the inverting circuit for start-up
When the high-level control signal PA is input to the input terminal of ND1, the NAND gate NAND1 and the NAND gate KN are input.
1 inverts the inverter LI4 to start inversion earlier, and the NAND gate NAND1
When the output of the inverter is inverted, the inverter KI2 performs the inversion operation, and the inverter LI5 starts the inversion operation. Thereafter, similarly, the inverters KI3, ..., KI28, KI29, KI
30, NAND gate KN31, NOR gate KN32, ...
Inverter INV6, ..., I
NV31, NAND gate NAND32, NAND1, inverters LI2, LI3, ... Try to start the inversion operation. In this way, the ring oscillator 1 of the fourth embodiment is
Even if 0 is set, just like the case of the ring oscillator 8 of the third embodiment, the inverting operation of each inverting circuit forming the first inverting circuit group is started forward by the second inverting circuit group. Therefore, the propagation delay time of the pulse signal is shortened.

Therefore, according to the ring oscillator 10 of the fourth embodiment, as in the case of the ring oscillator 8 of the third embodiment, the conventional ring oscillator 10 'shown in FIG. 6 is used.
Compared with the above, the propagation delay time of the pulse signal can be halved, and the phase difference of the pulse signals R1 to R16 respectively output from the 16 signal terminals can be shortened to half. be able to.

[Fifth Embodiment] Next, as a fifth embodiment,
The pulse signal R1 to R output from the ring oscillator 10 includes the ring oscillator 10 of the fourth embodiment described above.
External reference signal P in units of 16 phase difference times
A pulse phase difference encoding circuit configured to convert the phase difference (cycle) of B into a binary digital value will be described. The configuration and operation of this type of pulse phase difference encoding circuit are described in detail in Japanese Patent Application Laid-Open No. 7-183800 and Japanese Patent Application Laid-Open No. 7-283722, so that FIG. A brief description will be given by using. Further, in the following description, the inverting circuit refers to the inverting circuit that constitutes the first inverting circuit group of the ring oscillator 10, and the inverting circuit of the even-numbered stages is the pulse signal as shown in FIG. Inverters INV2, INV4, ..., I provided with signal terminals for outputting R1 to R16 to the outside
It indicates NV30 and NAND gate NAND32.

As shown in FIG. 9, the pulse phase difference encoding circuit 12 of the present embodiment is the ring oscillator 1 of the fourth embodiment.
0 and a pulse signal Rn (pulse signals R1 to R1) output from any one of the signal terminals of the ring oscillator 10.
By counting the rising edges of any one of R16), the number of times the main edge circulates in the ring oscillator 10 is counted, and a 10-bit counter (10-bit counter that outputs 10-bit data representing the count value) is output. (Hereinafter, simply referred to as a counter) 14 and the pulse signals R1 to R16 from the signal terminals of the ring oscillator 10, and when the external reference signal PB changes from Low to High level (rising timing of the reference signal PB). ,
Which of the pulse signals R1 to R16 is Low
Pulse selector that detects which inversion circuit the main edge has reached in the ring oscillator 10 by detecting whether it has changed from the high level to the High level, and encodes and outputs the reached position into 4-bit data. Based on the encoder circuit 16 and the 10-bit data from the counter 14 and the 4-bit data from the pulse selector / encoder circuit 16, the time from the rise of the reference signal PB to the next rise (that is, the cycle of the reference signal PB) is determined. And a data generation circuit 18 for generating and outputting the represented 14-bit data DOUT.

In the pulse phase difference encoding circuit 12 of the present embodiment having such a configuration, the ring oscillator 1
When 0 is activated by the control signal PA to start the circulation operation of the pulse signal as described above, the counter 14 counts the number of revolutions of the main edge in the ring oscillator 10 and the pulse selector / encoder circuit 16
However, each time the reference signal PB from the outside rises, the arrival position of the main edge in the ring oscillator 10 is detected.

Then, every time the reference signal PB rises, the data generation circuit 18 raises the reference signal PB last time based on the 10-bit data from the counter 14 and the 4-bit data from the pulse selector / encoder circuit 16. From the start up to this time, the ring oscillator 10 generates 14-bit data representing the total number of even-numbered inversion circuits in which the main edge propagates (that is, half the total number of inversion circuits in which the main edge propagates). Then, the data is output as data DOUT representing the cycle of the reference signal PB. Therefore, the pulse signal R is added to the value of the data DOUT.
The value obtained by multiplying the phase difference time Ts of 1 to R16 is the reference signal P
It becomes the cycle of B.

According to the pulse phase difference encoding circuit 12 as described above, the data DOUT which encodes the cycle of the reference signal PB is obtained with the phase difference time Ts of the pulse signals R1 to R16 output from the ring oscillator 10 as the resolution. Although it can be obtained, the pulse phase difference encoding circuit 12 of the fifth embodiment uses the ring oscillator 10 of the fourth embodiment, which has a very short propagation delay time of the pulse signal as described above. , The period of the reference signal PB can be encoded with a smaller time resolution.

The pulse phase difference encoding circuit 1 of this embodiment is used.
If 2 is applied to, for example, a sensor detection circuit that encodes the period of the pulse signal output from the sensor, the detection resolution will be improved to more than double that in the case of using the conventional ring oscillator 10 '. be able to. And, the chip area of this day's LSI is the same as that of the conventional ring oscillator 1.
Compared with the case where 0'is used, the increase is only about 10%. Therefore, the detection resolution can be increased without significantly increasing the chip area of the LSI.

[Sixth Embodiment] Next, as a sixth embodiment,
The pulse signal R1 to R output from the ring oscillator 10 includes the ring oscillator 10 of the fourth embodiment described above.
A digitally controlled oscillator circuit configured to generate and output an oscillation signal corresponding to frequency control data CD from the outside will be described with 16 phase difference times as a unit. Since the configuration and operation of this type of digitally controlled oscillator circuit are described in detail in the above-mentioned JP-A-7-106923 and JP-A-7-183800, FIG. 10 is used here. Briefly explained. In the following description, the inverting circuit refers to the inverting circuit that constitutes the first inverting circuit group of the ring oscillator 10.

As shown in FIG. 10, the digitally controlled oscillator circuit 20 of this embodiment is similar to the ring oscillator 1 of the fourth embodiment.
0 and a pulse signal Rn (pulse signals R1 to R1) output from any one of the signal terminals of the ring oscillator 10.
By counting the rising edges of any one of R16), it is possible to count how many times the main edge has circulated in the ring oscillator 10, and when the count value reaches the value of the 10-bit count data CDH. Hi
A 10-bit counter (hereinafter, simply referred to as a counter) 22 that outputs a gh level output signal CN and pulse signals R1 to R16 from each signal terminal of the ring oscillator 10 are received, and corresponding to 4-bit select data CDL The pulse selector 24 that selects the pulse signal from the selected signal terminal and outputs the selected signal as the select signal PSO.
Then, after the counter 22 outputs the high-level output signal CN, the select signal P from the pulse selector 24
When SO rises, the output circuit 26 that outputs the output signal POUT and the 14-bit frequency control data CD that is input from the outside are received, and the output circuit 26 receives the frequency control data CD and the two signals in the ring oscillator 10. Inversion operation time of the inversion circuit 2 · Td (that is, the propagation delay time of the pulse signals of two inversion circuits and the phase difference time Ts of the pulse signals R1 to R16) and a fixed period (CD × 2 ·
The count data CDH and the select data CDL are generated so that the output signal POUT is repeatedly output at Td = CD × Ts), and the generated data CDH, CDL.
Are provided to the counter 22 and the pulse selector 24, respectively.

In the digital control oscillator circuit 20 of this embodiment having such a configuration, the frequency control data CD is input from the outside and the control signal PA is input to the ring oscillator 10 to generate the pulse in the ring oscillator 10. When the circulating operation of the signal is started, the output circuit 26 outputs the output signal POUT as an oscillation signal at the above-mentioned constant period (CD × Ts).

According to the digital control oscillator circuit 20 as described above, the phase difference time Ts of the pulse signals R1 to R16 output from the ring oscillator 10 is used as the resolution to correspond to the frequency control data CD input from the outside. Although the oscillation signal (output signal POUT) can be obtained, in the digitally controlled oscillation circuit 20 of the sixth embodiment, as described above, the ring oscillator of the fourth embodiment has a very short propagation delay time of the pulse signal. Since 10 is used, the frequency control of the oscillation signal can be performed with a smaller time resolution.

[Seventh Embodiment] Next, as a seventh embodiment,
A frequency conversion device 30 including the above-described ring oscillator 10 of the fourth embodiment and configured to divide or multiply the external reference signal PB and output an oscillation signal of a predetermined frequency will be described. Regarding the configuration and operation of this type of frequency conversion device, the above-mentioned Japanese Patent Laid-Open No. 7-1838.
Since it is described in detail in Japanese Patent Publication No. 00, it will be briefly described here with reference to FIG.

As shown in FIG. 11, the frequency converter 30 of this embodiment is similar to the pulse phase difference encoding circuit 1 of the fifth embodiment.
2, the digital control oscillation circuit 20 of the sixth embodiment, and the data DOUT from the pulse phase difference encoding circuit 12 is multiplied / divided by a predetermined value, and the data after the operation is frequency controlled to the digital control oscillation circuit 20. An arithmetic circuit 32 as data generating means according to claim 8 for outputting as data CD. In the frequency conversion device 30 of the present embodiment, the pulse phase difference encoding circuit 12 and the digital control oscillation circuit 20 form one ring oscillator 10.
Is shared.

In the frequency converter 30 of this embodiment having such a configuration, as described above, the control signal PA is input to the ring oscillator 10 to start the circulation operation of the pulse signal in the ring oscillator 10. When the reference signal PB is input to the pulse phase difference encoding circuit 12, the pulse phase difference encoding circuit 12 outputs data DOUT representing the cycle of the reference signal PB. And that data DOUT
Is multiplied by a predetermined value or divided by a predetermined value by the arithmetic circuit 32.
Is calculated and input to the digital control oscillation circuit 20, and the digital control oscillation circuit 20 outputs an output signal POUT having a cycle corresponding to the data after the calculation.

Therefore, if the arithmetic circuit 32 is operated as a multiplication circuit which multiplies the data DOUT from the pulse phase difference encoding circuit 12 by a predetermined value, the device 30 is operated as the reference signal PB.
Can be used as a frequency divider for outputting an oscillation signal whose period is multiplied by a predetermined value. Conversely, the arithmetic circuit 32 divides the data DOUT from the pulse phase difference encoding circuit 12 by a predetermined value. If operated as a circuit, the device 30
Can be used as a multiplication device that outputs an oscillation signal in which the period of the reference signal PB is divided by a predetermined value.

Further, according to the frequency conversion device 30 of the present embodiment, since the ring oscillator 10 of the fourth embodiment is used, which has a very short propagation delay time of the pulse signal as described above, the time of a smaller value is used. Reference signal PB at resolution
Since it is possible to perform the encoding of the period and the frequency control of the output signal POUT, it is possible to perform highly accurate frequency conversion.

Further, in the frequency conversion device 30 of the present embodiment, since one ring oscillator 10 is shared by the pulse phase difference encoding circuit 12 and the digital control oscillation circuit 20, the device configuration is simplified and the size is reduced. Can be realized. Moreover, the time resolution of the data DOUT obtained by the pulse phase difference encoding circuit 12 and the digital control oscillation circuit 2
Since the time resolution of the output signal POUT output from 0 becomes the phase difference time Ts between the pulse signals R1 to R16 output from the same ring oscillator 10, the accuracy in frequency conversion of the reference signal PB is improved. It can be further improved.

[Eighth Embodiment] Next, as an eighth embodiment,
A PLL device 34 including the ring oscillator 10 of the above-described fourth embodiment and outputting an oscillation signal phase-locked with a reference signal PB from the outside will be described. In the following description, the inverting circuit refers to the inverting circuit forming the first inverting circuit group of the ring oscillator 10, and the inverting circuit of the even-numbered stages is the pulse signal as shown in FIG. R1
Inverters INV2, INV4, ..., INV30 and a NAND gate NAND32 provided with signal terminals for outputting R16 to the outside.

As shown in FIG. 12A, the PL of this embodiment is
The L device 34 is the digital control oscillator circuit 20 of the sixth embodiment.
A pulse phase difference encoding circuit 38 for converting the phase difference between the reference signal PB input from the outside and the output signal POUT from the digital control oscillation circuit 20 into a digital value DA, and the pulse phase difference encoding circuit 38. 10. The loop as the data generating means according to claim 9, which receives the digital value DA and outputs the frequency control data CD to the digital control oscillation circuit 20 so that the phases of the reference signal PB and the output signal POUT match. A filter (digital filter) 40,
It has. The pulse phase difference encoding circuit 38 is constructed in substantially the same manner as the pulse phase difference encoding circuit 12 of the fifth embodiment, but from the rise of the output signal POUT to the rise of the reference signal PB. The ring oscillator 10 generates data representing the total number of even-numbered stage inverting circuits in which the main edge propagates, and outputs the data as data (digital value) DA representing the phase difference between the reference signal PB and the output signal POUT. To do.

In such a PLL device 34, as shown in FIG. 12B, the reference signal PB input from the outside and the output signal POUT from the digital control oscillation circuit 20.
The pulse phase difference encoding circuit 38 obtains the phase difference between and as the digital value DA, and the loop filter 40 generates the frequency control data CD so that the digital value DA becomes “0”. Then, the frequency control data CD is input to the digital control oscillation circuit 20, and as a result, the phase of the reference signal PB and the phase of the output signal POUT match.

According to the PLL device 34, the pulse phase difference encoding circuit 38 and the digital control oscillation circuit 20 are provided.
And the ring oscillator 10 of the fourth embodiment, the phase difference encoding between the reference signal PB and the output signal POUT and the output signal POU are performed with a smaller time resolution.
Since the frequency of T can be controlled, highly accurate PL
L device can be realized.

In the PLL device 34 of the present embodiment, each of the digital control oscillation circuit 20 and the pulse phase difference encoding circuit 38 is provided with the ring oscillator 10, but in the above-described seventh embodiment. Like the frequency conversion device 30, the digitally controlled oscillator circuit 20 and the pulse phase difference encoding circuit 38 may be configured to share one ring oscillator 10. And with this configuration,
In addition to simplifying the device configuration and achieving miniaturization,
Digitally controlled oscillator circuit 20 and pulse phase difference encoding circuit 3
Since the time resolutions in 8 can be perfectly matched, the accuracy of signal processing can be further improved.

On the other hand, in the PLL device 34 of the above-mentioned embodiment, the pulse phase difference encoding circuit 38 encodes only the phase difference between the reference signal PB and the output signal POUT. As described in Kaihei 7-283722, the pulse phase difference encoding circuit 38 also encodes the cycle of the reference signal PB, and the loop filter 40 causes the phase difference between the digital value representing the cycle of the reference signal PB and the phase difference. Frequency control data CD using the digital value and
, The reference signal PB and the output signal POUT can be synchronized in phase more quickly.

[Others] In the fifth to eighth embodiments described above, the pulse phase difference encoding circuits 12 and 38 and the digital control oscillation circuit 20 are configured by using the ring oscillator 10 of the fourth embodiment. However, the ring oscillator 8 of the third embodiment may be used, or
If the number of connected inverting circuits (inverters) can be extremely increased, the delay circuit 2 of the first embodiment may be used. In the latter case, the counter 14 in FIG. 9 and the counter 22 in FIG. 10 are unnecessary.

[Brief description of drawings]

FIG. 1 is an explanatory diagram illustrating a configuration of a delay circuit according to a first embodiment.

FIG. 2 is a diagram showing a result of simulating a circuit operation of the delay circuit of FIG.

FIG. 3 is a configuration diagram illustrating a configuration of a variable delay device according to a second exemplary embodiment.

FIG. 4 is an explanatory diagram illustrating a configuration of a ring oscillator according to a third embodiment.

5 is a diagram showing a result of simulating a circuit operation of the ring oscillator of FIG.

FIG. 6 is a circuit diagram showing a conventional ring oscillator which is a premise of the ring oscillator of the fourth embodiment.

7 is a time chart explaining the operation of the ring oscillator of FIG.

FIG. 8 is a circuit diagram showing a ring oscillator according to a fourth embodiment.

FIG. 9 is a configuration diagram showing a configuration of a pulse phase difference encoding circuit of a fifth embodiment.

FIG. 10 is a configuration diagram showing a configuration of a digitally controlled oscillator circuit according to a sixth embodiment.

FIG. 11 is a configuration diagram illustrating a configuration of a frequency conversion device according to a seventh embodiment.

FIG. 12 is an explanatory diagram illustrating a PLL device according to an eighth embodiment.

[Explanation of symbols]

2 ... Delay circuit 4 ... Pulse selector 6 ... Variable delay device 8, 10 ... Ring oscillator 12, 38 ... Pulse phase difference encoding circuit 14, 22 ... Counter 16 ... Pulse selector / encoder circuit 18, 28 ... Data generation circuit 20 ... Digitally controlled oscillator circuit 24 ... Pulse selector 26 ... Output circuit 30 ... Frequency converter 32 ... Arithmetic circuit 34 ... PLL device 40 ... Loop filter

Claims (10)

[Claims] 1. A plurality of first outputs for inverting and outputting an input signal
In the delay circuit in which the pulse signals are sequentially inverted and propagated by each first inversion circuit, and the second inversion circuit is connected to the predetermined first inversion circuit of the delay circuit.
Is provided, the input terminal of the second inverting circuit is connected to the input terminal of the predetermined first inverting circuit, and the output terminal of the second inverting circuit is connected to the delay circuit. In the delay circuit, the predetermined first inverting circuit is connected to the input terminal of the first inverting circuit which is connected three or more and an odd number ahead of the predetermined first inverting circuit. 2. The delay circuit according to claim 1, wherein in the delay circuit, the plurality of first inverting circuits are connected in a ring shape, and the pulse signals are sequentially inverted by each of the first inverting circuits. A delay circuit which is configured as a pulse circulation circuit for circulation. 3. The delay circuit according to claim 2, wherein a specific first inverting circuit among the first inverting circuits forming the delay circuit performs an inverting operation of an input signal from an external control signal. Is configured as a start-up inverting circuit that can be controlled by the delay circuit. 4. The delay circuit according to claim 1, wherein an input signal from the outside is input to a first inverting circuit at a first stage of the delay circuit, and at least one of the first delay circuit and the first delay circuit that constitutes the delay circuit. The output signal output from the inverting circuit is converted from the input signal from the first inverting circuit at the first stage to any one of the first signals.
Is a signal processing device configured to take out as a delayed signal delayed by a delay time determined by the number of connected first inverting circuits up to the inverting circuit of the first inverting circuit. The first to the first inverting circuit that extracts the delayed signal from the first inverting circuit
A signal processing device, comprising: a changing unit that changes the number of connected inversion circuits. 5. The delay circuit according to claim 1, further comprising: a plurality of predetermined first inverting circuits of the first inverting circuit forming the delay circuit. A signal processing device configured to perform a predetermined signal processing with a phase difference time of an output pulse signal as a unit. 6. The signal processing device according to claim 5, wherein the signal processing device encodes a phase difference between pulse signals input from the outside at different timings with the phase difference time of the pulse signal as a unit. And a pulse phase difference encoding device configured as described above. 7. The signal processing device according to claim 5, wherein the signal processing device generates an oscillation signal corresponding to frequency control data input from the outside, with the phase difference time of the pulse signal as a unit, A signal processing device, which is a digitally controlled oscillator configured to output the oscillation signal. 8. The signal processing circuit according to claim 5, wherein the signal processing device includes the delay circuit according to any one of claims 1 to 3, and the first delay circuit includes the delay circuit. An oscillation signal corresponding to frequency control data input from the outside is generated with the phase difference time of pulse signals sequentially output from a plurality of predetermined first inversion circuits of the inversion circuit as a unit, and the oscillation signal is generated. A digitally controlled oscillator for outputting a delay circuit; and a delay circuit according to claim 1, wherein a plurality of predetermined first out of the first inversion circuits constituting the delay circuit are provided. A pulse phase difference encoding device that encodes the cycle of a reference signal input from the outside in units of the phase difference time of the pulse signals sequentially output from the inverting circuit, and the pulse phase difference encoding device that encodes the period. The above Generate frequency control data for outputting an oscillation signal obtained by multiplying the frequency of the reference signal by a predetermined number from the digital control oscillator based on the cycle data of the quasi signal, and output the frequency control data to the digital control oscillator. And a data generating unit that outputs the oscillation signal from the digitally controlled oscillator as an output signal obtained by frequency-converting the reference signal. . 9. The signal processing circuit according to claim 5, wherein the signal processing device includes the delay circuit according to any one of claims 1 to 3, and the first delay circuit constitutes the delay circuit. An oscillation signal corresponding to frequency control data input from the outside is generated with the phase difference time of pulse signals sequentially output from a plurality of predetermined first inversion circuits of the inversion circuit as a unit, and the oscillation signal is generated. A digitally controlled oscillator for outputting a delay circuit; and a delay circuit according to claim 1, wherein a plurality of predetermined first out of the first inversion circuits constituting the delay circuit are provided. A pulse phase difference encoding device for encoding a phase difference between a reference signal input from the outside and the oscillation signal in units of phase difference time of pulse signals sequentially output from the inverting circuit, and the pulse phase difference encoding On the device Frequency control data for phase-synchronizing the reference signal and the oscillation signal is generated based on the encoded phase difference data between the reference signal and the oscillation signal, and the frequency control data is used in the digital control oscillator. And a data generating unit that outputs the signal to the digital control oscillator, and is a PLL device configured to output an oscillation signal from the digitally controlled oscillator as an output signal that is phase-synchronized with the reference signal. . 10. The signal processing device according to claim 8 or 9, wherein the digital control oscillator and the pulse phase difference encoder are configured to share the delay circuit. A signal processing device characterized by the following.