JPH0730429A - Pulse phase difference encoding circuit - Google Patents

Abstract

PURPOSE:To improve the response up to binary encoding by making it possible to deal with the counted values or the like of the upper and lower bits of a binary digital signal expressing a pulse phase difference. CONSTITUTION:A ring oscillator 10 is constituted of a NAND gate NAND1 and 30 inverters INV2 to INV31 and an output from the oscillator 10 is inputted to a delayed pulse generating circuit 20 and counters 41, 43. A start pulse PA starts the oscillating operation of the oscillator and the counting operation of counters 41, 43. Then a binary digital signal to be a counter value obtained when a latch pulse PB is inputted and a binary digital signal from an encoder 33 which indicates the position of a period pulse PCLK in the circuit 20 are respectively set up as an upper bit and a lower bit, so that a binary digital signal expressing a phase difference between the start pulse PA and the latch pulse PB can be directly outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention encodes a phase difference between two pulse signals into a binary digital signal by using a pulse circulator circuit which circulates a pulse edge on a plurality of inverting circuits connected in a ring shape. The present invention relates to a pulse phase difference encoding circuit.

[0002]

2. Description of the Related Art Conventionally, a pulse phase difference encoding circuit for detecting a phase difference between two pulses and encoding the detected phase difference into a binary digital signal is disclosed in, for example, Japanese Patent Laid-Open No. 3-220814. As disclosed in the publication, an odd-numbered ring oscillator (pulse circulating circuit) is used in which an odd number of inverting circuits that invert and output an input signal are connected in a ring shape and a pulse edge is circulated on the ring. It has been known.

The pulse phase difference encoding circuit is
When one pulse signal PA is input, the pulse edge is circulated on the above ring oscillator, and when the other pulse signal PB is input, the pulse edge activated by the pulse signal PA moves on the ring oscillator. The phase difference between the two pulse signals PA and PB is detected by detecting whether the circuit has circulated or which inverting circuit on the ring oscillator has been reached.

[0004]

However, in the above-mentioned conventional pulse phase difference encoding circuit using the odd-numbered ring oscillator, the number of inverting circuits constituting the ring of the ring oscillator is an odd number, and n of 2 is used. Not multiplicative. Therefore, after the pulse signal PA is input, the pulse signal P
The number of revolutions of the pulse edge on the ring oscillator until B is input, and the position on the ring oscillator of the inverting circuit at which the pulse edge arrives are respectively directly represented by the upper part of the binary code representing the pulse phase difference. If the binary coding is performed in correspondence with the bits and the lower bits, a code loss will occur. Therefore, in order to obtain an accurate upper bit, the detected number of rounds of the pulse edge has to be calculated by using a subtracter or the like.

This is because, ^if a ring oscillator is formed by an even number of 2 ⁿ inverting circuits, the input and output signals of each inverting circuit will be at different levels and the entire circuit will be stable, causing the pulse edges to circulate. This is because the ring oscillator could only be configured with an odd number of inverting circuits.

Therefore, in the above-mentioned conventional pulse phase difference encoding circuit, the circuit scale becomes large due to the addition of the subtractor as described above, and it takes time until the detected pulse phase difference is output. Therefore, when the pulse phase difference is continuously detected and encoded, there is a problem that the encoding processing speed is limited.

The present invention has been made in view of the above problems, and uses a pulse circulation circuit in which an odd number of inverting circuits are connected in a ring shape, and uses a count number based on the number of revolutions of the pulse circulation circuit and a subsequent stage of the pulse circulation circuit. The number of inverting circuits in the delay pulse generating circuit provided in the above can be made to correspond to the upper bit and the lower bit of the binary digital signal representing the pulse phase difference as they are, thereby improving the responsiveness up to binary encoding. With the goal.

[0008]

The pulse phase difference encoding circuit of the present invention made to achieve the above object is formed by connecting an odd number of inverting circuits for inverting and outputting an input signal in a ring shape. One of the inverting circuits is configured as a starting inverting circuit whose inverting operation can be controlled by a first input pulse from the outside, and a pulse is generated according to the input of the first input pulse to the starting inverting circuit. As a delay circuit in which 2 ⁿ (n is an integer of 2 or more) sequentially connected a pulse circulation circuit for circulation and a periodic pulse output from the pulse circulation circuit as an input, and inverting and outputting an input signal A delay time for generating a delay pulse sequentially delayed by each delay time due to each inversion circuit through which the periodic pulse has passed from the output terminal. And a pulse generating circuit, the period of the periodic pulse outputted from the pulse circulating circuit, 2 ⁿ of the delay time of the inverter circuit 1 stage in the delayed pulse generating circuit
The delay time of each inversion circuit in the pulse circulation circuit is set so as to be doubled, and the number of times that the pulse generated by the start of the inversion operation of the startup inversion circuit circulates in the pulse circulation circuit is counted. Together with counting means for outputting a binary digital signal representing the count number,
It has an input line for taking in the delay pulse from each output terminal of the delay pulse generating circuit and an output line corresponding to each delay pulse, and has an arbitrary phase difference with respect to the first input pulse. One of the delay pulses having a specific time relation to the input timing of the second input pulse is selected, and the voltage of the output line corresponding to the selected delay pulse is set to the selected delay pulse. And a pulse selector which changes according to the pulse selector, and an encoder which takes in an output from the output line of the pulse selector and outputs a binary digital signal corresponding to the delay pulse selected by the pulse selector. The binary digital signal from the encoder as the high-order bit and the binary digital signal from the encoder as the low-order bit. Wherein the configuration to be such that output binary digital signal representing the phase difference between the force pulse and the second input pulse.

The pulse circulation circuit may have an odd number of inverting circuits. For example, as shown in claim 2, (2 ^n-1 -1) (n is an integer of 2 or more) ring inverting circuits. And one of the inverting circuits is configured as the starting inverting circuit, the delay time of one of the inverting circuits is twice that of the remaining inverting circuit, and the delay time of the remaining inverting circuit is a delay pulse. It is equal to the delay time of the inverting circuit in the generation circuit,
It is conceivable that the counting means is configured to count the number of rounds in the pulse rounding circuit as one round. In this case, most of the inverting circuits can have the same configuration.

[0010]

In the pulse phase difference encoding circuit according to the first aspect of the present invention configured as described above, first, the first input pulse is input from the outside to the inverting circuit for activation,
When the startup inverting circuit starts inverting the input signal, for example, if the input signal at that time is at high level, the output will be low.
The output of the inverting circuit at the next stage changes from the low level to the high level, and the output of the next inverting circuit changes to w level.
Since the output of the inverting circuit is sequentially inverted from the High level to the Low level, the edges of such pulses are sequentially transmitted on the pulse circulation circuit.

Then, the edge of the pulse first generated by the counting means by the start of the inverting operation of the starting inverting circuit of the pulse circulation circuit by the above-mentioned first input pulse is arbitrary with respect to this first input pulse. By the time the second input pulse from the outside is input at the timing, the number of rounds in the pulse circulation circuit is counted, and a binary digital signal indicating the count is output.

Further, a periodic pulse is output from the pulse circulation circuit to the delayed pulse generation circuit in the subsequent stage at a cycle of 2 ⁿ times the delay time of one stage of the inverting circuit in the delayed pulse generation circuit. The delayed pulse generation circuit inputs the periodic pulse output from the pulse circulation circuit, and the sequentially connected inversion circuits invert and output the input signal (in this case, the periodic pulse), whereby the sequentially inverted periodic pulse is generated. It will be transmitted sequentially. Then, from the output terminal, delay pulses are sequentially delayed by each delay time due to each inverting circuit through which the periodic pulse has passed.

A pulse selector which takes in a delayed pulse from its output terminal via an input line has a specific time with respect to the input timing of a second input pulse having an arbitrary phase difference with respect to the first input pulse. One of the related delay pulses is selected and the voltage of the output line corresponding to this selected delay pulse is changed according to the selected delay pulse. Then, the encoder takes in the output from the output line of the pulse selector and outputs a binary digital signal corresponding to the selected delay pulse.

By using the binary digital signal from the counting means as the upper bit and the binary digital signal from the encoder as the lower bit, the phase difference between the first input signal and the second input signal is directly expressed. A binary digital signal can be output. According to another aspect of the pulse phase difference encoding circuit of the present invention, one of the inverting circuits constituting the pulse circulator circuit has a delay time twice as long as the remaining inverting circuit, and the counting means circulates in the pulse circulator circuit. Since the number of times is counted as one time for two rounds, assuming that the delay time of a normal inverting circuit is Td, it takes two to make one round for the pulse rounding circuit.
^It takes ⁿ × Td. Therefore, the counting means counts up in a cycle of 2 ^{n + 1} × Td.

For example, the pulse circulation circuit has (2 ⁵ -1)
If there are 2 ⁶ inverting circuits in the delay pulse generating circuit, the circulating pulse is pulsed between the input of the first input pulse and the input of the second input pulse. The circuit is rotated 5 times (count = 2),
Moreover, in the delay pulse generation circuit, the periodic pulse is 52
If it has reached the inverting circuit at the stage, the counting means outputs a binary digital signal (10) and the encoder outputs a binary digital signal (110011). The phase difference between the first input signal and the second input signal is the binary digital signal (10, 110) obtained directly with the former as the upper bit and the latter as the lower bit.
011).

As described above, according to the pulse phase difference encoding circuit of the present invention, the binary digital signal from the counting means is converted into the binary digital signal from the counting means like the pulse phase difference encoding circuit using the above-mentioned conventional odd-stage ring oscillator. On the other hand, it is not necessary to provide a subtracter or the like for adding calculation, so that the circuit configuration can be simplified and the number of counts of the counting means and the number of inverting circuits in the delay pulse generating circuit can be directly set to the pulse phase difference. Since it is possible to correspond to the upper bit and the lower bit of the binary digital signal representing, it is possible to improve the responsiveness up to the binary encoding of the detected pulse phase difference, and to improve the detection speed thereof. .

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing the configuration of a pulse phase difference encoding circuit which is an embodiment of the present invention. The pulse phase difference encoding circuit is mainly composed of a ring oscillator 10, a delayed pulse generating circuit 20, a pulse selector / encoder circuit 30, and a ring circulation number counting section 40.

As shown in FIG. 1, a ring oscillator 10 according to the present embodiment has a 2-input NAND gate (hereinafter, simply referred to as a NAND gate) NAND1 and 3 serving as a inverting circuit for activation.
A total of 31 consisting of 0 inverters INV2 to 31
It is configured by sequentially connecting the individual inversion circuits in a ring shape.

A start pulse PA as a first input pulse from the outside is input to the input terminal of the NAND gate NAND1 which is not connected to the inverter INV31 (hereinafter, this input terminal is referred to as a start terminal). . This start pulse PA starts from low level
When it changes to the high level, the ring oscillator 10 starts the inversion operation.

In addition, 30 inverters INV2 to 31
Among them, the inverter INV2 indicated by the diagonal lines in FIG.
Since the delay time is set to be twice as long as that of other inverters, the inversion pulse of this ring oscillator 10 is set to 1
The time required for the rotation is the delay time (T
This is 32 times as long as in d). Therefore, the period of the periodic pulse PCLK output from the ring oscillator 10 to the delay pulse generation circuit 20 (details will be described later) connected to the latter stage of the ring oscillator 10 is 64 × Td.

On the other hand, the delay pulse generating circuit 20 is constructed by sequentially connecting 65 inverters D1 to D65, and the outputs of the first to 64th inverters D1 to D64 are respectively sent to the next inverters. In addition to the input, it is input to a pulse selector 31 to be described later from an output terminal for taking out to the outside. That is, the delay pulses P1 to P64 sequentially delayed by the delay times of the first to 64th inverters D1 to D64 are input to the pulse selector 31. The delay time due to each of the inverters D1 to D64 is Td.

The pulse selector / encoder circuit 30 will be described with reference to FIG. As shown in FIG. 2, when the delay pulses P1 to P64 are input and the latch pulse PB as the second input pulse from the outside is input, the periodic pulse on the delay pulse generation circuit 20 is determined by which inverter. A pulse selector 31 that detects whether D1 to D64 has been reached and an output signal from the pulse selector 31 are input, and a 6-bit 2 bit indicating the position of the inverter detected by the pulse selector 31 is located. The encoder 33 outputs the binary digital signals (BD0 to BD5).

The pulse selector 31 is provided with 64 D flip-flops D-FF as shown in FIG. 2, and each delay by the inverters D1 to D64 of the first to 64th stages of the delay pulse generation circuit 20. The delay pulses (P1 to P64) sequentially delayed by the time (Td) are respectively generated by the inverter I.
The data is input as data to each D flip-flop D-FF through one stage of NV. On the other hand, latch pulse P
B is input to each D flip-flop D-FF as a clock.

When the latch pulse PB is input, each output of the D flip-flop D-FF of the pulse selector 31 is output from the inverters D1 to D64 in which the periodic pulse PCLK just propagated in the delay pulse generating circuit 20 is located. The output Q becomes the same level before and after the D flip-flop D-FF which receives the output delayed pulses P1 to P64. That is, 64 D flip-flops DF
Of the outputs Q1 to Q64 from F, the potential becomes the same level in only one place, and the rest has a high level and a low level staggered.

Therefore, in order to detect the position where the output of the D flip-flop D-FF is at the same level (that is, the position where the periodic pulse PCLK has arrived), the odd-numbered D flip-flop D-FF is in front. When the outputs of the even-numbered D flip-flops D-FF are compared later, the outputs of both D-flip-flops D-FF are input to the AND circuit AND, and conversely, the even-numbered D flip-flops D-FF are input. In the case of comparing outputs when -FF is before and odd-numbered D flip-flops D-FF are after, outputs of both D flip-flops D-FF are input to the NOR circuit NOR. ing.

In this way, the encoder 3 to which the output signals from the AND circuit AND and the NOR circuit NOR are input
From 3, the lower bits of the digital code (BD0 to BD
5) is output. In addition, the ring lap number counting unit 40
As shown in FIG. 1, the second counter 43 uses the output from the inverter INV31 immediately before the NAND gate NAND1 as it is as the clock input CLK2, and the inverted version of the clock input CLK2 by the inverter INV as the clock input CLK1. A first counter 41,
It is composed of a first latch circuit 45, a second latch circuit 47, and a selector 49.

The first latch circuit 45 has a latch pulse P
The output from the first counter 41 is latched at the input timing of B, and the second latch circuit 47 latches the output from the second counter 43 at the input timing of the latch pulse PB. The selector 49 receives the output from the first latch circuit 45 and the output from the second latch circuit 47, and outputs the 6-bit binary digital signal (BD0 to BD5) output from the encoder 33. MSB
Based on the value of (BD5: most significant bit), one of the outputs of the first latch circuit 45 and the second latch circuit 47 is selected to select a 5-bit binary digital signal (D6 to D10). ) Is output.

In this embodiment, the output of the second latch circuit 47 is selected when the MSB is at the high level, and the output of the first latch circuit 45 is selected when the MSB is at the low level to output the upper bit of the digital code. To do. MSB
The state of High level occurs when the position of the periodic pulse in the delay pulse generation circuit 20 reaches the inverters at the 32nd stage and thereafter, and the state of Low level indicates that the position of the periodic pulse in the delay pulse generation circuit 20 is 32. It occurs when it is before the stage.

Here, two counters 41 and 43 and two latch circuits 45 and 47 are prepared.
The latch pulse PB is latched by the latch circuit 4 at an arbitrary timing.
This is to select the one whose output is stable when input to 5, 47. In FIG. 1, RGCR input to the first counter 41 and the second counter 43 is a reset pulse for the first and second counters 41 and 43, and after latching the counter output by the latch pulse PB, The counter output is reset to 0 before the start pulse PA is input.

The operation of the pulse phase difference encoding circuit of the present embodiment thus constructed will be described below with reference to FIGS. First, as described above, when the start pulse PA changes from the low level to the high level, the ring oscillator 10 starts the inversion operation. Nand Gate N
The periodic pulse PCLK inverted by AND1 and output from the ring oscillator 10 sequentially passes through the inverters D1 to D64 of the delay pulse generating circuit 20 and is inverted. Then, as shown in FIG. 3, each delay time (Td)
The delayed pulses P1 to P64, which are sequentially delayed by only, are input to the pulse selector 31.

The pulse selector 31 detects which of the inverters D1 to D65 the periodic pulse PCLK has reached on the delay pulse generating circuit 20, and the output signal thereof is input to the encoder 33, whereby the encoder 3
From 3, a 6-bit binary digital signal (BD0 to BD5) indicating the position of the inverter detected by the pulse selector 31 is output.

On the other hand, in the ring oscillator 10,
Since the inverter INV2 is set to have a delay time twice that of other inverters, the ring oscillator 1
The time required for the inversion pulse to make one turn around 0 is 32 × Td
Therefore, the periodic pulse PCLK output from the ring oscillator 10 to the delay pulse generating circuit 20 in the subsequent stage is 64 × T.
It is output in the cycle of d.

When the pulse passes through the inverter INV31 immediately before the NAND gate NAND1, the clock CLK1 is at the high level and the clock CLK2 is at the low level in the first cycle, as shown in FIG. When the pulse passes through the inverter INV31 on the second cycle, the clock CLK1
Is low level, the clock CLK2 becomes high level.

Therefore, when the pulse makes one round in the ring oscillator 10, the first counter 41 counts up,
When the pulse of the second round passes through the inverter INV31, the second counter 43 counts up. After that, one lap is counted alternately. That is, as shown in FIG. 4, the output CD1 of the first counter 41 and the output CD2 of the second counter 43 are pulsed by the ring oscillator 10.
The count is incremented by 1 at a timing that is shifted by the time for one lap.

When the latch pulse PB is input, the first latch circuit 45 latches the output from the first counter 41 at the input timing, and the second latch circuit 47.
Latches the output from the second counter 43. Then, the output from the first latch circuit 45 and the output from the second latch circuit 47 are input to the selector 49, respectively.

On the other hand, the MSB (most significant bit) of the binary digital signal (BD0 to BD5) output from the encoder 33, that is, BD5, is input to the selector 49. In this selector 49, the value of BD5 is 1. At times, the output of the second latch circuit 47 is output as it is as a binary digital signal, and conversely, when the value of BD5 is 0, the output of the first latch circuit 45 is output as it is as a binary digital signal.

For example, if the periodic pulse in the delay pulse generating circuit 20 reaches the 41st stage inverter D41 when the latch pulse PB is input at the timing of t1 shown in FIG. The value of BD5 output is 1, and in this case, the output of the second latch circuit 47 is selected and the selector 49 selects (000
01) is output.

When the latch pulse PB is input at the timing of t2 shown in FIG. 4, the delay pulse generating circuit 2
If the periodic pulse within 0 is at the position of the 25th stage inverter D5, BD5 output from the encoder 33 is
Becomes 0, and in this case, the output of the first latch circuit 45 is selected and the selector 49 outputs (00010).
Is output.

In the pulse phase difference encoding circuit of this embodiment, the two counters 41 and 43 and the two latch circuits 45 and 47 are respectively provided as described above, and the selector 49 controls the delay pulse generating circuit 20. Of the periodic pulse of the first stage to the 32nd stage inverters D1 to D3.
2 is selected, the output of the first latch circuit 45 is selected, and when the periodic pulse is between the 33rd to 64th inverters D33 to D64, the output of the second latch circuit 47 is selected. A description will be given of selecting and outputting.

This is because there is some delay until the outputs of the counters 41 and 43 are stabilized after the clocks CLK1 and CLK2 are input, and the delay pulse generation circuit when the latch pulse PB is input. From the position of the periodic pulse within 20, at least the delayed pulse generation circuit 2
By selecting the counter that uses the output signal of the inverting circuit, which is the previous half of 0, as the clock input, an accurate count value in a stable state is always output from the selector 49. Is there.

Then, the binary digital signals (BD6 to BD10) output from the selector 49 in this way are placed in the upper 5
And the binary digital signal (BD0 to BD5) output from the encoder 33 as the lower 6 bits,
If an 11-bit binary digital signal is formed and the operation delay time per inversion circuit constituting the delay pulse generating circuit 20 is added to this value, the time difference between the input timings of the start pulse PA and the latch pulse PB is obtained. That is, the phase difference is detected.

As described above, according to the pulse phase difference encoding circuit of this embodiment, the binary digital signals (BD6 to BD10) output from the selector 49 are directly supplied to the start pulse PA and the latch pulse PB. Since it can be used as the upper bit of the binary digital signal representing the phase difference of the above, the subtractor for adding the operation to the upper bit like the pulse phase difference encoding circuit using the conventional odd-stage ring oscillator. There is no need to provide the like. Therefore, the circuit configuration can be simplified and the entire circuit can be downsized, and the responsiveness until the detected phase difference is binary coded can be improved, and the detection speed thereof can be improved.

In the above embodiment, the pulse circulation circuit 10 is used.
31 inversion circuits, that is, (2 ^n-1 -1) (n
= 6) and the delay pulse generation circuit 20 has 64
Although the delay pulses P1 to P64 are sequentially delayed by each delay time (Td) from 2 ⁿ (n = 6) inverting circuits, the number of inverting circuits in the pulse circulating circuit 10 is an odd number. And the output periodic pulse P
CLK cycle is 64 × Td, that is, 2 ⁿ (n = 6) × Td
If

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a configuration of a pulse phase difference encoding circuit that is an embodiment of the present invention.

FIG. 2 is a pulse selector / encoder circuit 3 of the embodiment.
It is a block diagram showing the structure of 0.

FIG. 3 is a time chart showing the operation of the delay pulse generation circuit 20 of the embodiment.

FIG. 4 is a time chart showing the operation of the ring circumference number counting unit 40.

[Explanation of symbols]

PA ... start pulse, PB ... latch pulse,
PCLK ... Periodic pulse, P1-P64 ... Delayed pulse,
CLK1, CLK2 ... Clock input, 10 ... Ring oscillator, 20 ... Delayed pulse generation circuit, 30 ... Pulse selector / encoder circuit, 31 ... Pulse selector, 33 ... Encoder, 40 ... Ring circumference number counting unit, 41 ... First counter , 43 ... second counter, 45 ... first latch circuit, 47 ... second latch circuit, 49 ... selector

Claims (2)

[Claims] 1. An inversion circuit for inverting and outputting an input signal, wherein an odd number of the inverting circuits are connected in a ring shape, and one of the inverting circuits is capable of controlling its inverting operation by a first input pulse from the outside. A pulse circulator circuit configured as an inverting circuit, which circulates a pulse in response to the input of the first input pulse to the inverting circuit for activation, and a periodic pulse output from the pulse circulator circuit as an input, There are 2 ⁿ (n
Is an integer greater than or equal to 2) is configured as a sequentially connected delay circuit, has an output terminal for taking out the output signal of each inverting circuit to the outside, and each of the inverting circuits passes the periodic pulse from the output terminal. A delay pulse generation circuit for generating delay pulses sequentially delayed by a delay time, and the period of the periodic pulse output from the pulse circulation circuit is 2 times the delay time of one stage of the inverting circuit in the delay pulse generation circuit. The delay time of each inversion circuit in the pulse circulation circuit is set so that it becomes ⁿ times, and the ^{number of} times that the pulse generated by the start of the inversion operation of the startup inversion circuit circulates in the pulse circulation circuit is counted. At the same time, a counting means for outputting a binary digital signal representing the count number and a means for fetching the delayed pulse from each output terminal of the delayed pulse generating circuit. A power line and an output line corresponding to each of the delay pulses, and has a specific temporal relationship with the input timing of the second input pulse having an arbitrary phase difference with respect to the first input pulse. A pulse selector for selecting one of the delay pulses and changing the voltage of the output line corresponding to the selected delay pulse according to the selected delay pulse; and a pulse selector from the output line of the pulse selector. An encoder which takes in an output and outputs a binary digital signal corresponding to the delay pulse selected by the pulse selector, wherein the binary digital signal from the counting means is used as an upper bit, and the binary signal from the encoder is provided. A binary digital signal representing the phase difference between the first input pulse and the second input pulse is set with the digital signal as the lower bit. Pulse phase difference encoding circuit characterized by being configured to force. 2. The pulse phase difference encoding circuit according to claim 1, wherein the pulse circulation circuit connects (2 ⁿ −1 −1) (n is an integer of 2 or more) ring-shaped inverting circuits in a ring shape. One of the inverting circuits is configured as the starting inverting circuit, and the delay time of one of the inverting circuits is twice as long as the remaining inverting circuit, and the delay time of the remaining inverting circuit is It is equal to the delay time of the inverting circuit in the delay pulse generating circuit,
2. A pulse phase difference encoding circuit, wherein the counting means counts the number of times the circuit has circulated in the pulse circuit as two cycles.