JPH0677791A - Delay device, programmable delay line, and oscillator - Google Patents

Abstract

PURPOSE:To provide the delay device capable of digitally controlling the delay time in a wide range. CONSTITUTION:An oscillation pulse CLK from an oscillator 4 started by a control pulse PT is counted by a down counter 6, and a pulse generating circuit 8 outputs a pulse signal DI when the counted number reaches a prescribed value. Then, a programmable delay line 10 delays the pulse signal DI by a delay time shorter than the oscillation period of the oscillator 4, and an output circuit 12 processes a delay signal PO to output it to the outside. The count value of the down counter 6 and the delay time of the programmable delay line 10 are set by a high order bit CDH and a low order bit CDL of digital control data (binary digital signal) CDI latched by a data latch circuit 2 respectively. As the result, the delay time is controlled in a wide range by the oscillation period of the oscillator 4 and the count value, and further, the delay time is controlled with a high resolution by the programmable delay line 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay device capable of digitally controlling a delay time, a programmable delay line suitable for constructing the delay device, and a digitally controllable oscillation frequency using the delay device. Regarding an oscillator.

[0002]

2. Description of the Related Art Conventionally, as a delay device capable of digital control, as disclosed in, for example, Japanese Patent Application Laid-Open No. 2-296410, a large number of delay elements composed of an integrating circuit and an inverting circuit (inverter) are cascade-connected, There is known a delay device in which a signal to be delayed is input to the first-stage delay element and the output from each delay element is selectively taken out via a data selector.

[0003]

However, in such a conventional delay device, the delay time is changed by selecting the delay element for extracting the delay signal from the cascaded delay elements. As the variable range of 1 is increased, the number of delay elements increases, and there is a limit to increase the variable range of the delay time.

The present invention has been made in view of these problems, and provides a delay device capable of digitally controlling the delay time over a wide range without increasing the number of delay elements, and configures the delay device. It is an object of the present invention to provide a programmable delay line suitable for, and an oscillating device capable of digitally controlling an oscillating frequency by using the delay device.

[0005]

The delay device of the present invention, which has been made to achieve the above object, includes an oscillator which is activated by an input signal and outputs an oscillation pulse at a predetermined time interval, and an oscillation pulse from the oscillator. And counting means for generating a pulse signal when the count value reaches a preset predetermined value, and the pulse signal from the counting means is delayed by a delay time less than the time interval of the oscillation pulse of the oscillator. A programmable delay line that outputs the delay time as a delay signal and that can change the delay time by digital data, and a predetermined number of digital control data representing the delay time of the input signal are received, and the upper bits of the digital control data are counted. Means as a count value and supplies the lower bit of the digital control data to the programmable delay line. It is characterized by and a control data supply means for setting the delay time of the programmable delay line.

The programmable delay line of the present invention also includes
Input either the basic path for passing the input signal, the delay path for passing the input signal with a delay of a predetermined delay time, or the basic path or the delay path according to digital data input from the outside. A plurality of delay stages each including a selector that is selected as a signal path are connected in cascade, and the difference in the passing time of the input signal between the basic path and the delay path in each delay stage is set to 2 with respect to the minimum passing time difference. It is characterized in that it is set so as to be multiplied by n (n: 0, 1, 2, 3, ...).

Next, the oscillator of the present invention is an oscillator that is activated by an input signal and outputs an oscillation pulse at a predetermined time interval, and an oscillation pulse from the oscillator is counted, and the count value is set to a predetermined value. When the value becomes, a counting means for generating a pulse signal and a pulse signal from the counting means are delayed by a delay time less than the time interval of the oscillation pulse of the oscillator and output as a delay pulse. The delay time is digital data. And a programmable delay line that can be changed by a digital control data of a predetermined bit representing the oscillation cycle of the oscillator, and the upper bit of the digital control data is set as the count value of the count generating means. The lower bits of the programmable delay line to set the delay time of the programmable delay line. A control data supply means for stopping the oscillation operation of the oscillator when a pulse signal is output from the count generating means, and a feedback circuit for starting the oscillator when the delay pulse is output from the programmable delay line. , And the delay pulse output from the programmable delay line is output as an oscillation signal.

[0008]

In the delay device of the present invention configured as described above, when the input signal to be delayed is input, the oscillator is activated and the oscillation pulse is output at a predetermined time interval. Then, the counting means counts the oscillation pulses, generates a pulse signal when the count value reaches a preset predetermined value, and a programmable delay line configured to change the delay time by digital data is provided. , The pulse signal is delayed by a delay time less than the time interval of the oscillation pulse of the oscillator.

Further, in the delay device of the present invention, the control data supply means receives the digital control data of a predetermined bit representing the delay time of the input signal, and the upper bit of the digital control data is used as the count value of the count generation means. The delay time of the programmable delay line is set by setting and setting the lower bit of the digital control data to the programmable delay line.

That is, in the delay device of the present invention, the delay time is roughly controlled by the number of oscillation pulses output from the oscillator at predetermined time intervals, and the delay time is finely controlled by the programmable delay line. ing. Therefore, according to the delay device of the present invention, the resolution of the delay time is determined by the minimum variable time of the delay time of the programmable delay line, and the controllable range of the delay time is counted from the minimum delay time of the programmable delay line. The number of oscillation pulses that can be counted by the means is the time obtained by multiplying the time interval of oscillation pulses by the maximum delay time of the programmable delay line, and the delay time can be increased without increasing the delay elements as in the conventional case. The controllable range can be set in a wide range.

Next, the programmable delay line of the present invention is
A plurality of delay stages each including a basic route, a delay route, and a selector are connected in cascade, and the difference in the passing time of the input signal between the basic route and the delay route in each delay stage is 2 n with respect to the minimum passing time difference. It is configured by setting to be a multiplication (n: 0, 1, 2, 3, ...).

Therefore, in the programmable delay line of the present invention, the delay time is minimized when all the selectors in each delay stage select the basic path, and the delay is delayed when all the selectors in each delay stage select the delay path. Time is the maximum.
By directly designating the selector that selects the delay path by the digital data, the delay time can be switched stepwise corresponding to the digital data within the minimum to maximum delay range.

Therefore, when the programmable delay line is applied to the delay device, the delay time can be easily controlled by using the digital control data inputted from the outside. That is, in the delay device according to the first aspect, as the programmable delay line, a large number of delay elements including an integrating circuit and an inverting circuit (inverter) are cascade-connected, and the output from each delay element is passed through the data selector. Although the conventional delay device that selectively takes out can be used as it is, in such a conventional delay device, it is necessary to decode digital data in order for the data selector to determine the delay element from which the delayed signal is taken out. , A decoder for that must be provided. However, in the programmable delay line of the present invention, the delay time can be controlled by directly driving the selector of each delay stage using digital data, so that a signal processing circuit such as a decoder is not required and the delay time is digitally controlled. It is possible to simplify the device configuration for doing so. Further, since it is not necessary to provide a decoder, the size and weight of the device can be reduced, and the power consumption can be reduced.

Next, the oscillation device of the present invention comprises an oscillator,
A delay device similar to the delay device according to claim 1, comprising a counting means, a programmable delay line and a control data supply means, is provided with a feedback circuit, by which the pulse signal from the count generating means is provided. The oscillation operation of the oscillator is stopped when it is output, and the oscillator is activated when the delay pulse is output from the programmable delay line.

Therefore, in the oscillator of the present invention,
A pulse signal is sequentially generated with a delay time controlled by a delay device similar to the delay device according to claim 1 as one cycle, and the generation period of the pulse signal, that is, the oscillation frequency is determined by the programmable delay line. With the time resolution determined by the minimum variable time of the delay time, it becomes possible to change in a wide range.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. First, FIG. 1 is a block diagram showing the overall configuration of a digitally controlled oscillator to which the present invention is applied.

As shown in FIG. 1, the digital control oscillator of the present embodiment has a digital control data (binary digital signal) CDI representing the output cycle of a pulse signal input from the outside.
Data latch circuit 2 for latching the digital control data CDI and outputting the digital control data CDI by dividing it into lower bit data CDL of the lower 5 bits and upper bit data CDH above the lower 6th bit, and a control pulse PT input from the outside. Is Hi
At the gh level, an oscillation pulse C is generated at a predetermined time interval T.
The oscillator 4 that outputs LK and the oscillation pulse CLK output from the oscillator 4 are counted, and when the count value becomes a value corresponding to the upper bit data CDH output from the data latch circuit 2, the detection signal TCP is output. The down counter 6 that outputs and the detection signal TC from the down counter 6
A pulse generation circuit 8 that takes in an oscillation pulse CLK and outputs a pulse signal DI when P is output, and a pulse signal DI from the pulse generation circuit 8 to a data latch circuit 2
A programmable delay line 10 for delaying a delay time corresponding to the lower bit data CDL output from the output circuit 12, an output circuit 12 for outputting the delay pulse PO output from the programmable delay line 10 as it is or by signal processing, and a pulse. The pulse signal DI output from the generation circuit 8 and the delay pulse PO output from the programmable delay line 10 are received, the oscillation operation of the oscillator 4 is stopped when the pulse signal DI is input, and the oscillator 4 of the oscillator 4 is input when the delay pulse PO is input. The feedback circuit 14 restarts the oscillating operation, and the selector 16 that switches whether the device operates as an oscillating device or a delay device.

Here, the feedback circuit 14 is constituted by an RS flip-flop which is set when the power is turned on, reset by the pulse signal DI, and set by the delay pulse PO, and the RS flip-flop is set. The high-level signal output from the RS flip-flop is output as the oscillation operation control signal PS of the oscillator 4.

Further, the selector 16 is composed of a multiplexer, receives the selection signal SEMD for switching the operation mode inputted from the outside, and receives the selection signal SEMD.
Is a high level indicating that the device operates as an oscillating device, the oscillation operation control signal PS output from the feedback circuit 14 is input to the oscillator 4 as a control pulse PT, and the selection signal SEMD causes the device to delay the device. When it is at a low level indicating that the oscillator 4 is operated, the reference pulse PI input from the outside is input to the oscillator 4 as the control pulse PT.

Next, as shown in FIG. 2A, the oscillator 4 is a ring oscillator in which an odd number (15) of inverting circuits for inverting and outputting after inputting an input signal after a delay of a minute time are connected in a ring shape. Is equipped with. This ring oscillator is composed of 14 inverters INV and one NAND gate NAND.
The control pulse PT output from the selector 16 is input to one of the input terminals.

Further, the inverter IN of the third stage of the ring oscillator whose starting point (first stage) is the NAND gate NAND
At the output terminal of V (3), an internal circulating pulse is output to the down counter 6 so that the driving capability thereof is gradually increased so that the counting operation can be executed surely on the down counter 6 side. Three output inverters INV
a, INVb, INVc are connected.

In the oscillator 4 configured as described above, as shown in FIG. 2B, when the high level control pulse PT is input to one input terminal of the NAND gate NAND, the pulse signal is generated in the ring oscillator. Went around,
The oscillation pulse CLK is output from the output inverter INVc in synchronization with the cycle.

The time interval T (rising interval) of the oscillation pulse CLK is twice as long as the delay time for 15 stages of the inverting circuit (inverter, NAND gate) forming the ring oscillator, that is, for 30 stages of the inverting circuit. However, in the present embodiment, the output inverter INV of the first stage connected to the NAND gate NAND and the ring oscillator is
Using the load of a, the time interval T of the oscillation pulse is set to be a delay time of 32 stages (2 ⁵ ) of the inverter INV forming the ring oscillator.

This is the programmable delay line 10 side,
Inverter INV in the ring oscillator, which is the element having the minimum delay time, for the oscillation cycle or delay time of the device.
The lower 5 bits CD of the digital control data CDI, which is a binary digital signal, with the delay time of one stage as the minimum unit.
This is because L can be easily controlled without using a decoder or the like. That is, the number of inverting circuits of the ring oscillator is set in relation to the maximum oscillation frequency of the device and the down counter operating speed, and as a value having a high counter operating speed at a high frequency, 7 or It may be configured with 15 or 31 or 63 pieces.

Next, the oscillation pulse CL from this oscillator 4
The down counter 6 and the pulse generating circuit 8 for counting K correspond to the counting means of the present invention, and are configured as shown in FIG. 3 and operate as shown in FIG. That is, as shown in FIG. 4, the down counter 6 is initialized when the count value n is initially set by the upper bit data CDH of the digital control data CDI, counts down by the oscillation pulse CLK, and when the count value is zero. , The detection signal TCP is generated, and one stage corresponding to each bit of the higher-order bit data CDH has a multiplexer MPX and a D flip-flop D as shown in FIG.
It is composed of a combination of -FF. Then, the down counter 6 is preset by the first oscillation pulse CLK after the detection signal TCP is output, and starts the counting operation.

Although the number of stages of the down counter 6 may correspond to the number of bits of the upper bit data CDH of the digital control data CDI, the number of stages of the down counter 6 and the number of bits of the upper bit data CDH are increased. As a result, the oscillation cycle and delay time of the device can be set in a wider range.

On the other hand, as shown in FIG. 3, the pulse generation circuit 8 delays the detection signal TCP output from the down counter 6 with a delay time of 16 stages of the inverter, and a delay line DL which passes through the delay line DL. It is composed of an AND gate AND which takes the logical product of the signal TCPD and the oscillation pulse CLK, and as shown in FIG. 4, the oscillation pulse CLK is taken in only when the detection signal TCPD is output, and the pulse signal DI Is output.

Next, the programmable delay line 10 is shown in FIG.
The lower bit data CDL (CD1 to CD5) of the digital control data CDI with respect to the pulse signal DI output from the pulse generation circuit 8 is configured as shown in FIG.
And a delay pulse PO is output. The programmable delay line 10 will be described in detail below.

Programmable delay line 1 as shown in FIG.
0 is a basic route K1 for passing an input signal, a delay route K2 for passing an input signal with a delay of a predetermined delay time with respect to the basic route K1, a basic route K1 and a delay route K2.
And a multiplexer MPX that selects one of the two as a path for the input signal, and five delay stages 10a to 10a.
0e are connected in cascade.

In the first delay stage 10a, the difference in passing time of the input signals between the basic route K1 and the delay route K2 is
Two inverters INV are provided in the basic path K1 and eighteen inverters are provided in the delay path K2 so that the time is half the time interval of the oscillation pulse CLK generated by the oscillator 4, that is, the time corresponding to 16 inverters INV. It is configured by providing an INV.

Further, in the second delay stage 10b, the difference in passing time of the input signals between the basic route K1 and the delay route K2 is 1/4 of the time interval of the oscillation pulse CLK generated by the oscillator 4.
The two inverters INV are provided on the basic route K1 so that the time becomes, that is, the time corresponding to eight inverters INV,
It is configured by providing 10 inverters INV on the delay path K2.

Further, in the third delay stage 10c, the difference in passing time of the input signals between the basic route K1 and the delay route K2 is ⅛ of the time interval of the oscillation pulse CLK generated by the oscillator 4.
The two inverters INV are provided in the basic route K1 so that the time becomes, that is, the time corresponding to four inverters INV,
It is configured by providing six inverters INV on the delay path K2.

Further, in the fourth delay stage 10d, the difference in passing time of the input signals between the basic route K1 and the delay route K2 is 1/1 of the time interval of the oscillation pulse CLK generated by the oscillator 4.
Two inverters INV are provided in the basic path K1 and four inverters INV are provided in the delay path K2 so that the time becomes 6 times, that is, the time for two inverters INV.

Finally, the fifth delay stage 10e is
The difference in delay time between the basic route K1 and the delay route K2 is 1/32 of the time interval of the oscillation pulse CLK generated by the oscillator 4.
The three inverters INV are provided on the basic route K1 so that the time becomes, that is, one inverter INV.
The delay path K2 includes two inverters INV and an inverter INV2 having a delay time set to be twice as long as the other inverters INV.

That is, in each of the delay stages 10a to 10e, the minimum difference between the passing times of the input signals of the basic path K1 and the delay path K2 is the inverter INV.
As one delay time, 2 times the nth power (n: 4,
3, 2, 1, 0).

In this way, each delay stage 10a-10
In e, in order to set the passing time difference between the input signals of the basic route K1 and the delay route K2 to be a power of 2 times the delay time of one inverter INV, the inverter INV is set to the basic route K1. Although not required, two inverters INV are inserted in each basic route K1 in this embodiment.

This is because, in each of the delay stages 10a to 10e, the delay time of the inverter INV caused by the branch changes from the delay time when the inverter INV is connected in series and the delay time of the inverter INV caused by the input to the multiplexer MPX. This is because the fluctuation of

That is, one inverter INV is inserted on each of the branch point B1 side and the multiplexer MPX side of the basic path K1, and similarly, one inverter INV is also inserted on the branch point B1 side and the multiplexer MPX side of the delay path K2. The multiplexer MPX allows the basic path K
Input signal transit time and delay path K when 1 is selected
The difference from the passage time of the input signal when 2 is selected is the delay time of the intermediate inverter INV excluding the inverter INV on the branch point B1 side of the delay path K2 and the multiplexer MPX side.

Next, the multiplexer MPX of each of the delay stages 10a to 10e is composed of an n-channel p-channel MOS transistor, and the first delay stage 10a.
The multiplexer MPX of the lower bit data CDL
Of the lower-order bit data CDL to the multiplexer MPX of the second delay stage 10b and the upper-order bit data of the lower-order bit data of the multiplexer MPX of the third delay stage 10c. The upper 3rd bit data of the data CDL is sent to the multiplexer MPX of the fourth delay stage 10d, and the upper 4th bit data of the lower bit data CDL is sent to the multiplexer MPX of the 5th delay stage 10e. Is input with the least significant bit data of the lower bit data CDL, respectively.

Each multiplexer MPX selects the basic route K1 when its input data is "0",
When the input data is "1", the delay path K2 is selected. Therefore, in the programmable delay line 10, the delay time is set to 3 depending on the lower bit data CDL, with the delay time of one inverter INV as one unit.
It becomes possible to switch to two stages.

Next, in the programmable delay line 10 of this embodiment, the signal path from the output terminal of the multiplexer MPX of the delay stages 10a to 10d to the branch points B2 to B5 of the next delay stages 10b to 10e is arranged. The same as the output inverter in the oscillator 4 in which the drive capacity is gradually increased in response to the increase in the load caused by the branching.
Inverters INVa, INVb, INVc are provided.

Therefore, there are five inverters between the branch points B1 to B5 of the delay stages 10a to 10e, and the rising and falling edges of the signals alternate at the branch points B1 to B5. To exist in. Therefore, the delay characteristic of each multiplexer MPX (difference in delay time with respect to rising signal and falling signal) is
The entire programmable delay line 10 can be offset.

Further, one inverter INV is provided on the output side of the fifth delay stage 10e. This inverter INV is connected from the programmable delay line 10
The delay pulse PO is for outputting a signal having the same polarity as the pulse signal DI output from the pulse generation circuit 8. That is, in the present embodiment, by providing one inverter INV on the output side of the fifth delay stage 10e, no matter which path is selected in each of the delay stages 10a to 10e, the input signal (that is, the pulse The number of inverters through which the signal DI) passes is even.

In the fifth delay stage 10e,
The number of the inverters INV on the basic path K1 is three, and the delay path K2 is two inverters INV and IN.
Inverter INV2 having a delay time twice that of V
The reason why it is configured by is for the same reason.

That is, when the passage of the pulse signal DI is switched to either the basic route K1 or the delay route K2 to control the delay time as in this embodiment, each delay stage 10a.about.
In 10e, if the number of inverters forming the basic path K1 and the number of inverters forming the delay path K2 are different from each other, the polarity of the delay pulse PO at the time of path switching is different, and the delay line PO is normally operated. Since it does not operate, in the present embodiment, in the fifth delay stage 10e,
The number of inverters in the basic path K1 and the delay path K2 is set to the same odd number (three) so that signals of the same polarity can be output regardless of which path is selected, and the passage time difference between the input signals of each path is The delay time is one inverter INV.

Next, each of the above-mentioned inverters forming the programmable delay line 10 has the same characteristics as the inverter forming the oscillator 4. Therefore, the output fluctuation of the oscillator 4 and the output fluctuation of the programmable delay line 10 due to the temperature change and the like coincide with each other, and the temperature correction of the oscillation period and the delay time can be easily performed. The correction method and the like will be described later.

On the other hand, the data latch circuit 2, as shown in FIG. 6, has the digital control data C at the rising timing of the delay pulse PO output from the programmable delay line 10.
The delay pulse PO from the programmable delay line 10 via the inverter INV and the latch circuit 2a composed of D flip-flops D-FF corresponding to the number of bits of the digital control data CDI for latching each bit data of DI respectively. D flip-flop D-FF which latches the lower 5 bits of the digital control data CDI in the latch circuit 2a at the falling timing of the delay pulse PO.
D flip-flops D-FF that latch the output of
And 5 D flip-flops D-FF which constitute the latch circuit 2b.
Of the D flip-flop D-FF which forms the latch circuit 2a, and outputs the output of the digital control data CDI as the lower bit data CDL of the digital control data CDI.
Output of the D flip-flop D-FF except for the lower 5 bits of the upper bit data C of the digital control data CDI.
Output as DH.

That is, in the data latch circuit 2, as shown in FIG. 7, the latch circuit 2a latches the digital control data CDI at the rising timing of the delay pulse PO, and the latch circuit 2b latches the falling timing of the delay pulse PO. Then, the digital control data C latched by the latch circuit 2a
By latching the lower bit data CDL of DI, the respective latch circuits 2a and 2b cause the upper bit data CDH and the lower bit data C of the digital control data CDI to be latched.
Output DL respectively.

Next, the output circuit 12 is constructed as shown in FIG. 8A and operates as shown in FIG. 8B. That is,
The output circuit 12 includes a toggle flip-flop T-FF whose output level is inverted by the delay pulse PO from the programmable delay line 10 and a selection signal SE input from the outside.
O delay pulse PO as it is output pulse POUT
Or a selector 12a including a multiplexer for selecting whether to output the signal PQ having a pulse duty of 50% generated by the toggle flip-flop T-FF as the output pulse POUT.

This is because when the delayed pulse PO is output as it is as the output pulse POUT, the pulse width of the output pulse POUT is too small and the rise of the output pulse POUT rises when the circuit load receiving this output pulse POUT is large. This is because the signal may disappear and the signal may disappear. That is, in such a case, by selecting the toggle flip-flop T-FF, the minute pulse width of the delay pulse PO is converted into the pulse signal PQ having a wide pulse width and can be output. .

If the digital control data CDI is changed while the toggle flip-flop T-FF is selected, the pulse width of the pulse signal PQ can be arbitrarily changed according to the digital control data CDI. next,
The operation of the digitally controlled oscillator according to the present embodiment configured as described above will be described with reference to the time chart shown in FIG.

As shown in FIG. 9, when the control pulse PT rises from the initial state (PT = 0), the control pulse PT circulates around the ring oscillator of the oscillator 4 so that 32 oscillators of the inverter INV are generated from the oscillator 4. Oscillation pulse CLK is output at a predetermined time interval corresponding to the delay time of
The down counter 6 counts down this oscillation pulse.

Then, for example, as the digital control data CDI in the device, the high-order bit data is "00011",
When the digital control data “0001100000” whose lower-order bit data is “00000” is input, the down counter 6 receives the value “3” as the count value.
Therefore, the down counter 6 outputs the detection signal TCP when the oscillator 4 outputs three oscillation pulses CLK, and the pulse generation circuit 8 then outputs the oscillation pulse from the oscillator 4. A pulse signal DI synchronized with CLK is output. Since the down counter 6 is preset by the first oscillation pulse CLK after the detection signal TCP is output, it is preset at the timing synchronized with the pulse signal DI.

Next, the pulse signal DI output from the pulse generation circuit 8 is delayed by the programmable delay line 10 for a predetermined time and output as a delay pulse PO. As described above, when the low-order bit data is "00000", all delay stages 10a to 1 of the programmable delay line 10 are
Since the basic path K1 is selected at 0e, the delay time of the programmable delay line 10 is the shortest. The delay pulse PO is input to the output circuit 12 and output to the outside as an output pulse POUT.

On the other hand, the delay pulse PO is also input to the feedback circuit 14. Feedback circuit 14
Is reset by the pulse signal DI output from the pulse generation circuit 8 and set by the delay pulse PO output from the programmable delay line 10, so that the oscillation operation control signal PS output from the feedback circuit 14 is output.
Becomes Low level in synchronization with the rise of the pulse signal DI from the rise of the delay pulse PO.

Then, as shown in FIG.
When the high level selection signal SEMD is input,
That is, when the operation mode of the device is selected as the oscillation device by the selection signal SEMD, the oscillation operation control signal PS from the feedback circuit 14 is input to the oscillator 4 as a control pulse. While PS is at a low level, the oscillation operation of the oscillator 4 is stopped, and after the rise of the delay pulse PO, the same operation as above is executed again.

As described above, according to the digitally controlled oscillator of the present embodiment, the operation mode is set to be an oscillator capable of digitally controlling the output period of the output pulse POUT by the selection signal SEMD input from the outside. The time (delay time) until the output pulse POUT is output after the control pulse PT is input can be switched to a mode that operates as a delay device capable of digital control.

The output period and delay time of the output pulse POUT can be changed by the time resolution of the programmable delay line 10 with the reversing operation time per stage of the inverter INV as one unit, and the down counter 6 It can be controlled over a wide range depending on the number of oscillation pulses CLK to be counted.

Therefore, for example, if the inverting operation time of the inverting circuit (inverter) forming the oscillator 4 and the programmable delay line 10 is set to about 200 ps, the delay time and the oscillation frequency are each 200 ps in time resolution. Several ns
It becomes possible to control in a wide range from to several s or more and from several tens of MHz to several Hz or more.

In the present embodiment, the programmable delay line 10 is configured such that the minimum unit of digitally controllable delay time is the delay time of one inverter INV. And the sixth
As shown in FIG. 10, as the delay stage of the first stage, the basic route K1
Is provided with one inverter INV, and the delay path K2 is provided with one inverter INV3 having a delay time 1.5 times the delay time TD of the inverter INV. If the least significant bit data LSB of the least significant bit data CDL is input to, the minimum unit of the delay time that can be controlled by the programmable delay line can be reduced to 1/2 of the delay time of the inverter INV. It is possible to further reduce the time resolution of. In this case, the lower bit data CDL input to the programmable delay line
Must be the lower 6 bits of the digital control data CDI.

As described above, according to the digital control oscillator of this embodiment, the oscillation frequency and the delay time can be set by the digital control data CDI.
Since the oscillation frequency and the delay time are determined by the operating time of the inverting circuit that constitutes the oscillator 4 and the programmable delay line 10, if the operating time of the inverting circuit changes, it will correspond to the digital control data CDI. The oscillation frequency and delay time cannot be controlled accurately.

However, since the digitally controlled oscillator of this embodiment can digitally control the oscillation period and the delay time, the output period of the output pulse POUT from the device and the output signal from the reference oscillator such as a crystal oscillator are controlled. By comparing with the output cycle and setting the correction data according to the ratio in advance, the digital data CDI input from the outside is corrected by this correction data and input to the data latch circuit 2. The oscillation frequency and delay time can be corrected easily and surely. Hereinafter, an example of the correction data calculation device for obtaining this correction data will be described with reference to FIGS. 11 and 12.

As shown in FIG. 11 (a), this correction data operation device includes pulse phase difference encoding circuits 81 and 82 for encoding the phase difference of the input pulse, and pulse phase difference encoding circuits 81 and 82. Correction data Do based on the encoded data
And a correction value calculation circuit 83 for calculating
A reference pulse PA from a reference oscillator such as a crystal oscillator and an output pulse POUT from the digitally controlled oscillator of the above embodiment are input to one pulse phase difference encoding circuit 81.
The other pulse phase difference encoding circuit 82 has a reference pulse PA from a reference oscillator such as a crystal oscillator and the reference pulse P.
A reference pulse PB obtained by delaying A by a predetermined time is input. The output pulse POUT input to the pulse phase difference encoding circuit 81 is obtained when the digitally controlled oscillator is operated as an oscillator by inputting the digital data CDI so that the oscillation period becomes the same period as the reference pulse PA. Signal.

Further, each pulse phase difference encoding circuit 81,
As shown in FIG. 12, the reference numeral 82 includes a ring delay pulse generation circuit 84 in which an OR gate, a NAND gate, and an even number of inverters are connected in a ring shape, a counter 86, a pulse selector 88, and an encoder 90. The pulse phase difference encoding circuits 81 and 82 are circuits previously proposed by the applicant of the present application in Japanese Patent Application No. 2-15865, etc., and operate as follows.

That is, the pulse phase difference encoding circuits 81,
At 82, the reference pulse PA is applied to the input terminal of the OR gate of the ring delay pulse generating circuit 84. Then, from the middle of the ring delay pulse generation circuit 84, a plurality of delay pulses whose delay time is determined by the number of stages of the inverter through which the reference pulse PA has passed are output and input to the pulse selector 88. Further, another input pulse POUT or PB is input to the pulse selector 88,
When this pulse POUT or PB is input, the pulse selector 88 selects only the input from the ring delay pulse generating circuit 84 of the stage to which the reference pulse PA has reached, and the encoder 90 outputs the signal corresponding to this selected input. Output to. Then, from the encoder 90, 2 corresponding to the input
A decimal digital signal is output. Further, since the output of the final stage inverter of the ring delay pulse generation circuit 84 is connected to the OR gate, the reference pulse PA returns to the OR gate with a delay time due to all the circuits forming the ring, and as a result, the reference pulse PA is returned. The PA circulates in the ring delay pulse generation circuit 84. The counter 86 is connected to the output of the final stage inverter in order to count the number of revolutions, and outputs the count result as the upper bit of the output of the encoder 90.

As a result, as shown in FIG. 11 (b), the time difference between the pulses PA and POUT or the pulses PA and PB is the digital value DAO or DAB due to the outputs from the pulse phase difference encoding circuits 81 and 82. It will be obtained as. Since the configurations of the pulse phase difference encoding circuits 81 and 82 are described in detail in Japanese Patent Application No. 2-15865, the description thereof will be omitted.

In this way, the pulse phase difference encoding circuit 81 obtains the digital value DAO representing the time difference between the output pulse POUT from the digitally controlled oscillator and the reference pulse PA from the reference oscillator such as a crystal oscillator, and the pulse position The phase difference encoding circuit 82 obtains a digital value DAB representing the time difference between the reference pulse PA and the reference pulse PB. Then, of the digital values DAB and DAO thus obtained, the digital value D
AB represents the input time difference between the reference pulses PA and PB having the same period, and the time difference is also known. Therefore, the obtained digital value DAB can be used as reference time data. On the other hand, the digital value DAO simply represents the time difference between the rising edge of the reference pulse PA and the rising edge of the output pulse POUT.
It is not possible to directly obtain the deviation of the cycle between A and the output pulse POUT. Therefore, in the correction value calculation circuit 83, first, by taking the difference between the digital values DAO1 and DAO2 obtained twice by the pulse phase difference encoding circuit 81, it corresponds to the time difference of the cycle of the output pulse POUT with respect to the reference pulse PA. The calculated digital value ΔDAO (= DAO2-DAO1) is obtained. If the digital value ΔDAO is positive, the cycle of the output pulse POUT is longer than that of the reference pulse PA, and conversely, if ΔDAO is negative, the cycle of the output pulse POUT is shorter than that of the reference pulse PA.

Then, using the digital value DAB and the known time TAB represented by the digital value DAB, this digital value ΔDAO is output pulse POUT and reference pulse PA.
Time difference data TAO (= TAB ・ △
DAO / DAB) is obtained, and this time difference data TAO is added to the reference oscillation period TA of the reference pulse PA to output the output pulse POU.
The actual oscillation cycle TO (= TA + TAO) of T is obtained, and the reference oscillation cycle TA is divided by this oscillation cycle TO to obtain the correction data Do (= TA / TO).

As a result, when the digital control oscillator is operated with the oscillation cycle of 1000 nsec. By the digital data CDI in order to obtain the correction data using the reference oscillator with the oscillation frequency of 1 MHz (oscillation cycle of 1000 nsec.), When the oscillation cycle of is 800 nsec., -200 nsec. Is obtained as the time difference data TAO, and the oscillation cycle TO is the value TAO and the reference oscillation cycle TA (=
1000 nsec.) To 800 nsec., And 1.25 (= 1000/800) is obtained as the correction data Do.

Therefore, when the digital control oscillator is operated thereafter, a value CCDI (= Do.CD) obtained by correcting the digital data CDI with the correction data Do is obtained.
By inputting I) to the data latch circuit 2, the output pulse POU is generated at the oscillation cycle corresponding to the digital data CDI.
Can generate T.

Further, since the digital control oscillator of the present embodiment can digitally control the oscillation frequency up to a high frequency range of several tens of MHz by the digital control data DCI input to the data latch circuit 2, it controls the communication device and the motor. The present invention can also be applied to a high frequency PLL used in a device or the like. For example, as shown in FIG. If the pulse phase difference encoding circuit shown in FIG. 12 is used to form a PLL by using a well-known digital filter for the loop filter 96, a high frequency digital PLL that does not require an A / D converter or the like can be formed. it can.

Incidentally, FIG. 13B shows this digital PL.
7 is a time chart showing the operation of L. The phase difference between the output pulse POUT from the variable frequency oscillator 92 and the reference pulse PC input from the outside is obtained as a digital value DA by the phase comparator 94, and the digital value DA is obtained. Is converted into a digital value DB by the loop filter 96 and input to the frequency variable oscillator 92. As a result, the output pulse P
It indicates that OUT is controlled by the reference pulse PC.
In such a PLL, since the inversion time variation of the inversion circuit that constitutes the oscillator 4 and the programmable delay line 10 of the digitally controlled oscillator is automatically corrected (because of feedback), the digital control data No correction is necessary.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of a digitally controlled oscillator according to an embodiment.

FIG. 2 is an explanatory diagram showing a configuration of an oscillator 4 and its operation and its operation.

FIG. 3 is a circuit diagram showing configurations of a down counter 6 and a pulse generation circuit.

FIG. 4 is an explanatory diagram showing operations of a down counter 6 and a pulse generation circuit.

FIG. 5 is a circuit diagram showing a configuration of programmable delay line 10.

FIG. 6 is a circuit diagram showing a configuration of a data latch circuit 2.

FIG. 7 is an explanatory diagram showing an operation of the data latch circuit 2.

FIG. 8 is a circuit diagram showing a configuration of an output circuit 12.

FIG. 9 is a time chart showing the operation of the entire digitally controlled oscillator.

FIG. 10 is an explanatory diagram illustrating another configuration example of the programmable delay line 10.

FIG. 11 is an explanatory diagram showing the configuration and operation of a correction data calculation device that obtains correction data for correcting the oscillation period and delay time of the digitally controlled oscillator.

FIG. 12 is a circuit diagram showing a configuration of pulse phase difference encoding circuits 81 and 82 of the correction data operation device.

FIG. 13 is a digital PL using a digitally controlled oscillator.
It is explanatory drawing showing the structure of L, and its operation.

[Explanation of symbols]

2 ... Data latch circuit 4 ... Oscillator 6 ... Down counter 8 ... Pulse generation circuit 10 ... Programmable delay line 10a, 10b, 10c, 10d, 10e, 10f ... Delay stage K1 ... Basic path K2 ... Delay path MPX ... Multiplexer 12 ... Output circuit 14 ... Feedback circuit
16 ... Selector

Claims (3)

[Claims] 1. A delay device capable of digitally controlling a delay time, comprising an oscillator activated by an input signal to output an oscillation pulse at a predetermined time interval, and an oscillation pulse from the oscillator is counted, and a count value is Counting means for generating a pulse signal when it reaches a preset predetermined value, and a pulse signal from the counting means is delayed by a delay time less than the time interval of the oscillation pulse of the oscillator and output as a delay signal. A programmable delay line whose delay time can be changed by digital data and a predetermined bit of digital control data representing the delay time of the input signal are received, and the upper bit of the digital control data is set as the count value of the count generating means. , The lower bit of the digital control data is supplied to the programmable delay line to enable the programmable Delay apparatus characterized by comprising: a control data supply means for setting the delay time of the extension line, the. 2. A basic path for passing an input signal, a delay path for passing an input signal with a delay of a predetermined delay time, and a basic path and a delay path according to digital data input from the outside. A plurality of delay stages consisting of a selector that selects one of them as an input signal route are connected in cascade, and the difference in the transit time of the input signal between the basic route and the delay route in each delay stage is calculated as the minimum transit time difference. Is a power of 2 to the power of n (n: 0, 1, 2, 3 ...) And a programmable delay line. 3. An oscillating device capable of digitally controlling an oscillating frequency, the oscillator being activated by an input signal to output an oscillating pulse at a predetermined time interval, and counting the oscillating pulse from the oscillator, Counting means for generating a pulse signal when it reaches a preset predetermined value, and a pulse signal from the counting means is delayed by a delay time less than the time interval of the oscillation pulse of the oscillator and output as a delayed pulse. A programmable delay line whose delay time can be changed by digital data and a predetermined number of digital control data representing the oscillation cycle of the oscillator are received, and the upper bit of the digital control data is set as the count value of the count generating means. Supplying the low order bits of the digital control data to the programmable delay line Control data supply means for setting the delay time of the active delay line; and when the pulse signal is output from the count generating means, the oscillation operation of the oscillator is stopped, and the delay pulse is output from the programmable delay line. An oscillating device comprising: a feedback circuit for activating the oscillator; and outputting the delay pulse output from the programmable delay line as an oscillation signal.