DE10149585C2 - Integrable, controllable delay device, use of a delay device and method for operating a delay device - Google Patents

Description

The invention relates to an integrable, controllable Delay device with an input connection for a delaying input signal, an output connection for a delayed output signal and a control connection for a control signal controlling the delay time. The invention also relates to the use of such an inte grizable, controllable delay device. Finally The invention relates to a method of making a taktsi gnal to delay, such a delay device is used.

Such integrable, controllable delay devices are often used to delay a clock signal in inte gried semiconductor circuits used. A special attraction application of the delay device lies in a delay control loop. Delay control loops are in digi tal working circuits used to clock signals with generate predetermined phase position. For example, in synchronously operated integrated semiconductor memories that work according to the double data rate principle, so-called DDR SDRAMs (Double Data Rate Synchronous Dynamic Random Access Memories) used a delay locked loop to taking into account internal signal propagation times Generate clock signal on the output side, the data to be output synchronized with a scarf integrated elsewhere device supplied input clock signal.

A delay locked loop compares that of the delay unit supplied on the input side clock signal with the delayed clock signal generated on the output side and provides the  Delay depending on the phase difference so far after that the phase difference is corrected to zero if possible becomes. It is particularly important that the output side present clock is as stable as possible and jitter free lies. For example, the output clock should be as possible be unaffected by fluctuations in the supply voltage and independent of the modulation of the delay unit regarding their currently set delay time.

A delay device according to the post-published German patent application 101 30 122.7-42 is known as Tapped delay line executed. There are inverters in series on. The signal delayed along the delay chain is via signal paths branching off the delay chain tapped. The signal paths are on the output side on a ge coupled knot. These branching signal paths each contain a tristate inverter that either forwards the signal to be delayed or switched to high resistance is. The output node has a high capacity proportional to the number of inverter stages in the delay chain is. The tristate inverters switch relatively long sam. After tapping the signal from the chain the inverter is additionally the one by the tristate inverter and one optionally downstream inverter caused signal ver delay to take into account. After all, an inverter has the Delay chain two connected to it on the output side To drive input loads, namely the downstream In verter the delay chain and the input of the tapping Tri-state inverter.

DE 693 27 612 T2 describes a circuit for generating egg stable clock signal based on frequency multiplication shown. The circuit contains a delay stage with adjustable delay time in which two multiplexers out are connected in series. The multiplexers are input on the one hand a signal without delay, on the other hand via Delay elements are additionally supplied with a delay.  

DE 199 12 967 A1 includes a delay control loop a delay line shown in the multiplexer are seen, whose input connections are flip-flops are connectable. All multiplexers become the same either from a UP control signal or a DOWN Control signal driven.

DE 43 27 116 A1 describes a programmable delay line shown where multiplexers are used, which on the input side an input signal directly and additionally ver hesitates to be fed.

An object of the invention is to provide an integrable, controllable delay device to specify a possible has exactly adjustable delay time, so that largely when used in a delay locked loop stable, jitter-free output clock can be generated. Insbeson The output clock should be as independent as possible of the manufacturer fluctuations in the parameters of the components due to Fluctuations in the supply voltage or temperature fluctuations be kungen.

According to the invention, this object is integrier solvable, controllable delay device, comprising: an input connection for an input to be delayed signal, an output connector for a delayed output signal, a control connection for a delay time controlling control signal; a variety of multiplexers with a first and a second input connection and an output port, the multiplexers in series are switched by the second connection of a downstream th multiplexer with the output of an upstream Multi plexers is connected and the first connections of all Multiplexers are coupled to the input terminal, the second connection of one of the multiplexers with a connection for  a reference potential is connected and the output one on the multiplexer of which is coupled to the output terminal.

Use of such a delay device in a delay control loop is given in claim 11 ben.

One method of delaying a clock signal includes Steps: Provide an integrable, controllable Delay device as indicated above; ready Stel len of the clock signal to be delayed at the input connection and Provide the comprising a number of several bits Control signal at the control connection; Setting the switch position of two multiplexers connected in series in Ab dependence on the bits of the control signal such that each a connection forwarding the clock signal to be delayed between their first signal input and their output conclusion is made; Setting the switch position of all other multiplexer such that a signal connection between their second input port and their output port conclusion is made; Generate a delayed clock gnals at an output terminal of the in the series circuit last arranged multiplexer; and forming a phase difference between a signal that makes up the delay Signal is derived, and from another signal that is derived from the delayed clock signal; and generating the control signal depending on the determined Pha sendifferenz.

In the delay device according to the invention are for Formation of the signal acting on the signal to be delayed runtime multiplexer provided. All multiplexers are regarding one of their inputs and one output in series switched to each other. The other input is the multiplexer  jointly coupled to a node and with which to delay gerenden input signal providing connection.

Depending on the required delay time, this will be delayed input signal at one of the multiplexers in the rows circuit coupled. According to the number of effective multiple from the signal to the output xerstufen has a different delay time on. The output signal is at the output of the last one in the Tapped multiplexers tapped. one of the inputs of the first multiplexer of the series circuit connected to a constant potential, preferably ground.

The design of the delay device with multiple xern has the advantage that the output side capacitive loading of the multiplexers and also of the off the last multiplexer stage regardless of the set delay time remains the same. The depending Va formed by the set delay time riation is available on the input side. As a result, kapaziti ve fluctuations in the capacitive load on the input side can by a suitably well-trained driver who provides the input signal to be delayed, balanced become. The delay unit according to the invention has the Advantage that the signal to be delayed none of the delay capacitive load fluctuation and terliegt. This driver can be a conventional inverter be compared to a tristate inverter in one Tapped delay line switches faster. The exit of a Mul tiplexers is only at the entrance of one more downstream multiplexer connected. Compared to A tapped delay line switches through a multiplexer formed delay unit faster than the corresponding one Unit in the Tapped Delay Line.

The delay unit is preferably used for processing of differential signals. This means that  a complementary, inverted signal for each signal Signal is processed. Thereby the influence of Versor voltage fluctuations compensated for the delay time chen. Each of the multiplexers has a particularly advantageous one circuit design on that for the processing device differential signals is suitable. When using the ser delay unit in a delay locked loop a relatively jit under different operating conditions get the free output clock signal.

Each of the multiplexers expediently comprises four current paths de, which are connected at one end to a power source and via this to a first pole of a supply voltage, for example mass, are coupled. The other ends of the four current paths are paired to respective resistance elements elements coupled. The signal coupling into the four current paths takes place differentially. To an even better Independent maintain fluctuations in the supply voltage, a capacitor is connected in parallel to the power source, the corresponding fluctuations due to switching from Currents between the four branches equalize and dampen. The resistance elements are preferably ge as diodes switched transistors formed, preferably as so-called called MOS diodes. The diodes are on the second pole of the Supply voltage connected. This is the electricity branches also from the second pole of the supply voltage decoupled. The diode is even more advantageous than Current source switched MOS transistor connected in parallel. This transistor is connected to one of its control terminals controlled constant potential. The parallel connection off MOS diode and MOS current source can act as an active resistor or linearized transistor.

In detail, the current paths each contain two with their ge controlled routes in series connected MOS transistors. ever one of the switches of the first and second current path is from a line of the tax setting the delay time  signals controlled together. The comparable transistors the third and fourth current path are shared by the complementary signal portion of the control signal switched. The other of the transistors of the first and second current paths are in the ket with the complementary signal outputs te of the delay elements previously switched multi plexers connected. The other transistors of the third and fourth current path are from the complementary signal part len of the input signal, i.e. from the common input finally controlled. The boarded up with the active resistance The ends of the current paths are cross-connected prevented. The first and third current paths are on an active one Resistor connected, the second and fourth current path connected the other active resistance.

Depending on the delay time to be set, one the multiplexer set so that its output with its first of the two input connections is connected. At this Place the clock signal to be delayed in the chain of coupled multiplexer coupled. All other multiplexers, both the upstream and the downstream, are set so that their output with whose respective second input establishes a signal connection provides.

In a particularly advantageous embodiment of the setting of the Delay device two of the multiplexers are turned on represents that their output with their respective first input is connected to form a signal connection. Zweckmäßi these multiplexers are sometimes in direct succession switched, d. H. the exit of the first of these two behind mutually connected multiplexer is immediate - without intermediate circuit of another multiplexer - with the second Input connection of the downstream of this multiplexer ver prevented. In this case, the clock signal to be delayed still the same as the second one switched multiplexers into the multiplexer chain for delays  coupling coupled in. The clock signal to be delayed is at hand at the same time directly on the first of the two connected multiplexer on the output side for ver addition. However, the second of the multiplexers is not yet forwarded. Only when the delay time is one To increase the partial step, the second of the multiplexers switched and already at the second input The clock signal to be delayed can be directly connected to its Output to be forwarded. The waveform of the output signals of the delay device is improved. It ent there are in particular no glitches.

Appropriately, the ones considered above, immediate multiplexers connected in series in the multiple xerkette upstream multiplexer turned off to power to save. This is particularly the case with the above routing of the multiplexers as at least four current paths and a power switch comprising a power source advantageous.

The invention based on the in the drawing illustrated embodiment explained in detail. Ent speaking elements in different figures are the same Chen provided reference numerals. Show it:

Fig. 1 is a block diagram of a delay unit according to the invention;

FIG. 2 shows a detailed circuit diagram at transistor level for a multiplexer which can be used in the delay device of FIG. 1;

Fig. 3 is a block diagram of a delay locked loop; and

Fig. 4 is a block diagram of a delay unit according to an advantageous operating setting.

The circuit in Fig. 1 shows a delay unit 1 , which can advantageously be used in the delay control loop shown in Fig. 3. The input clock signal CLKIN is thus supplied as a differential, complementary signal to parts CLKIN and / CLKIN comprehensive signal. The delay unit 1 is fed to inputs 9 , 11 to delay the input clock signal CLKIN, and the input clock signal / CLKIN complementary thereto. On the output side, a differential, delayed output clock signal with in-phase component CLKOUT and counter-phase component / CLKOUT can be tapped off at connections 12 , 13 . The delay time present between an input clock signal and an output clock signal is controlled as a function of a signal SLC. The signal SLC has a multiplicity of bits, SLC10, SLC20, etc., each comprising normal component and complementary component and on a multiplicity of Bitleitun comprehensive port 14 are supplied. All signal processing in the delay unit 1 is therefore done differentially. The voltage swing of the inputs and outputs of a delay stage 10 is limited. The signals SLC, / SLC are full-level signals and therefore quasi-static.

The delay unit has a multiplicity of multiplexers connected in series, of which the multiplexers 10 , 20 , 30 , 40 , 50 are shown by way of example. All multiplexers have the same internal structure. As an example, the multiplexer 30 is also explained in detail in connection with the detailed implementation in FIG . A first respective differential signals leading signal input 33 , 34 , of the multiplexer 30 is coupled, like all other ver comparable inputs of the other multiplexers, to the connections 9 , 11 for supplying the differential input signal CLKIN, / CLKIN. The second differential input 35 , 36 of the multiplexer is connected to the differential output of the upstream multiplexer 20 . The diffe economic outputs 37 , 38 are closed in a corresponding manner to the second input of the downstream multiplexer 40 . The corresponding bit of the control signal SLC30, / SLC30 is fed differentially at the differential control connections 31 , 32 .

The output of the last multiplexer 50 arranged in the series circuit is connected to the outputs 12 , 13 of the delay unit 1 . The second input of the first multiplexer 10 arranged in the series circuit of the multiplexers is connected to ground potential VSS.

The size of the delay time, which is effective between the differential inputs 9 , 11 and the differential outputs 12 , 13 for the supplied differential input clock signal CLKIN, / CLKIN, is determined by the number of multiplexers that the clock signal between input and output passes through the delay unit 1 . In the case shown, the input clock signal CLIKIN, / CLKIN is fed to the multiplexer 30 and passes through all subsequent multiples 40 , 50 . The signal path is shown in dashed lines and labeled 60. For this purpose, all the multiplexers upstream of the multiplexer 30 , that is to say the multiplexers 10 , 20 , 50, are set such that the signal path set in the respective multiplexer connects the respective output to the second input, that is to say shown in the drawing below. The same switching setting have the downstream multi plexers 40 , 50 , so that they direct the signal supplied to them at the second input, shown below, to their output. Only the multiplexer 30 has a different setting of its signal path. The outputs 37 , 38 are connected to the first differential input 33 , 34 . The input clock signal CLKIN is thus fed to the multiplexer 30 at the first input and passes through all the downstream multiplexers 40 , 50 in order to arrive at the differential output 12 , 13 , as indicated by the signal path 60 shown in broken lines in FIG. 1.

This circuit has the advantage that the input 9 , 11 largely has the same capacitive load regardless of the switching state. Any capacity variations can be compensated for by a correspondingly large driver driving the input 9 , 11 . The output 12 , 13 also provides the same driver power for downstream circuits.

The switching setting of the respective multiplexer is done by corresponding bits of the control signal SLC set. The ever bits are called the multiple as complementary signals xern fed.

All of the multiplexers 10 ,. , ., 50 executed in detail as shown in Fig. 2. The multiplexer 30 shown there by way of example has 4 current paths 310 , 311 , 312 , 313 . At the ground end of the current paths, these are jointly coupled to a current source 322 . Current source 322 connects the current paths to ground potential VSS. Each of the current paths has two N-channel MOS transistors connected in series with their drain-source paths. The current source transistors 316 , 317 of the first and second current paths 310 , 311 are differentially controlled by the output signal PRE, / PRE of the previous multiplexer. The gates of these transistors 316 , 317 form the second differential input of the multiplexer. The other transistors 314 , 315 in the first and second current paths 310 , 311 are driven by the complementary partial signal / SLC30 of the control signal SLC that sets the delay time. In the third and fourth current paths, the transistors 320 , 321 on the current source side are driven differentially by the clock signal CLKIN, / CLKIN supplied on the input side. The other transistors 318 , 319 of the third and fourth current paths 312 , 313 are activated by the in-phase component SLC30 of the Control signal SLC setting the delay time. The current paths 310 , 312 and 311 , 313 are each coupled in pairs on the supply potential side. The coupling nodes 320 and 329 are connected via respective active resistors to the other pole VDD of the supply voltage. The nodes 328 , 329 simultaneously form the complementary outputs of the multiplexer 30 .

In order to compensate for fluctuations when the current supplied by the current source 322 is switched between the four current paths 310 , 311 , 312 , 313 , a capacitance 323 formed by a MOS transistor is connected in parallel with the current source 322 . The capacitance 323 connects the common node to ground potential VSS.

The active resistor connecting node 328 with supply potential VDD comprises a P-channel MOS transistor 325 connected as a current source. The gate of transistor 325 is connected to a constant potential VP. Parallel to the drain-source path of transistor 325 is a transistor 324 connected as a MOS diode. The gate of transistor 324 is connected to node 328 to form the MOS diode function. The connected to the node 329 ne active resistor includes the appropriate P-channel MOS transistors 326 , 327 , the parameters of which are technically better controllable than resistive resistors. The active resistors cause the potential difference between 328, 329 to be as independent as possible of fluctuations in the supply voltage VDD, VSS. In principle, the active resistors could also be replaced by resistive resistors.

In Fig. 4 are deviating from Fig. 1 in the two UNMIT telbar cascaded multiplexers 30, 40, the first inputs 33, 34 and 41, respectively connected to the input terminals 9, 11 for feeding the to be delayed clock signal CLKIN, / CLKIN. The clock signal CLKIN, / CLKIN is fed to the multiplexer 40 in the delay chain and passed along the signal curve 61 . The multiplexer 30 passes the clock signal CLKIN, / CLKIN on to its output 37 , 38 . There it is blocked and not forwarded from the input terminal 42 of the multiplexer 40 , since its output 43 is connected to its first input 41 to form a signal path and not to its second input 42 .

The described setting of the multiplexers 30 , 40 ensures that the clock signal CLKIN / CLKIN to be delayed is already prepared at the output 37 , 38 of the multiplexer 30 . If now the delay to be caused by the delay device 1 is to be increased by a delay time increment, the signal introduction into the delay chain being advanced from the multiplexer 40 to the multiplexer 30 , then the multiplexer 40 switches over, so that its output 43 now forms a Signal path is connected to its input 42 . The clock signal CLKIN, / CLKIN is already present at the output 42 due to the presetting described above and can be passed on immediately to the output 43 of the multiplexer 40 . A possible, uncontrolled signal state within the multiplexer 40 in which Störim pulses or glitches would possibly occur is avoided. The clock signal CLKCUT, / CLKCUT on the output side is therefore free of interference even when switching operations newly set the delay time.

In the operating state shown in FIG. 1, the second input terminal 15 of the first multiplexer 10 is connected to ground VSS. Both of the corresponding switching transistors, for example transistors 315 , 317 in FIG. 2, are connected to ground VSS. As a result, the output 16 of the multiplexer 10 is pulled to the high level VDD. The second input of the downstream multiplexer 20 is driven by this high level. The output-side level of the multiplexers is approximately in the middle of the level swing between a possible high and low level at the multiplexer outputs, since the base-side current is divided equally between the two current branches 310 and 311 . The constant base current flows through the multiples, although they do not contribute to the formation of the delay time.

In FIG. 4, it is therefore provided that the multiplexers 30, 40 upstream of multiplexer 10, to disable the twentieth This is achieved in that the corresponding inputs for the control signal / SLC10, SLC10, / SLC20, SLC20 controlling the switching setting of the multiplexers 10 , 20 are set to a low level or to logic "0". As a result, all current paths within the multiplexers 10 , 20 are switched off. The power loss of the delay device 1 is thereby reduced without loss of functionality.

In the embodiment shown in Fig. 4 embodiment of the differential multiplexer 10. , ., 50 of the delay device 1 , the following control signals are to be applied to the control inputs which control the setting of the respective multiplexer: Those multiplexers which forward the clock signal CLKIN, / CLKIN to their respective output, the multiplexers 30 , 40 in FIG. 4, are each from complementary bits "01" controlled their control signal connections. This connects their output to their first input. The multiplexers connected downstream of these two multiplexers, for example the multiplexer 50 , are controlled by the complementary signal state “10”. As a result, their output 54 is connected to the respective second input 52 . The multiplexers 30 , 40 connected upstream of the multiplexers, for example the multiplexers 10 , 20, are in turn also driven by the same signal combination “00”. As a result, all current paths in these multiplexers 10 , 20 are switched off.

In the delay locked loop shown in FIG. 3, the clock signal CLK supplied on the input side is to be converted to a clock signal CLK ′ which can be tapped off on the output side and which has a fixed phase shift with respect to the clock signal CLK. The central element of the delay control loop is the delay line. The delay line comprises a first delay unit 2 and a second delay unit 1 connected downstream thereof, which is realized accordingly in FIG. 1. The first delay unit 2 causes a short delay and is used to fine-tune the total delay time. The downstream delay unit 1 causes a greater delay and serves to roughly set the total delay time between the signals CLK ", CLKOUT.

A phase detector 4 detects the phase difference between the delay chain 2, 1 on the input side the input clock signal CLK "and there on the output side tapped clock signal CLKOUT. If necessary, a circuit block with a fixed delay time 7 in the feedback path tet geschal. Depending on the phase difference control means 3 produces a control signal SLC., that for each of the multiplexers 10,., in the delay device 1 provides 50 a bit having complementary signal components. as in connection with FIG., only one bit is illustrated 1 in the operation of the circuit the maximum set so that a multi-plexer transmits the signal present at its first input terminal to its output. All other multiplexers are set to the exactly complementary switching state. Moreover, all circuit blocks 5 , 6 , 7 have a constant delay time.

The phase-locked loop in FIG. 3 has a very linear control range due to the use of the delay device shown in FIG. 1. The output signal is generated jitter-free, regardless of temperature, parameter fluctuations of the components due to tolerances in the manufac turing process, fluctuations in the supply voltage or momentarily set size of the delay time. In the architecture shown, the delay control loop can cover a wide control range, up to very high clock frequencies.

LIST OF REFERENCE NUMBERS

1

delay means

2

Fine delay

3

control device

4

phase detector

5

.

6

.

7

circuit blocks

9

.

11

input terminals

12

.

13

output terminals

14

control terminal

10

.

20

.

30

.

40

.

50

multiplexer

21

.

41

.

51

first input connections of multiplexers

22

.

42

.

52

second input connections of multiplexers

23

.

43

.

54

Output connections from multiplexers

33

.

34

first input terminal of a multiplexer

35

.

36

second input connection of a multiplexer

37

.

38

output terminal

31

.

32

control terminal

60

.

61

waveform

310

.

311

.

312

.

313

signal paths

314

,. , .,

321

transistors

324

,. , .,

327

transistors

322

power source

323

capacitor
VDD supply voltage
VSS ground potential
SLC control signal
CLKIN input signal to be delayed
CTKOUT delayed output signal
PRE input signal
VN, VP reference potentials
OUT output signal

Claims (15)

1. Integrable, controllable delay device ( 1 ), comprising:
an input connection ( 9 , 11 ) for an input signal to be delayed (CLKIN, / CLKIN), an output connection ( 12 , 13 ) for a delayed output signal (CLKOUT, / CLKOUT) a control connection ( 14 ) for a control signal (SLC) controlling the delay time ;
a multiplicity of multiplexers ( 10 , 20 , 30 , 40 , 50 ) each with a first ( 33 , 34 ) and a second ( 35 , 36 ) an input connection and an output connection ( 37 , 38 ), whereby
the multiplexers are connected in series by the second connection ( 35 , 36 ) of a downstream multiplexer ( 30 ) being connected to the output of an upstream multiplexer ( 20 ) and the first connections ( 33 , 34 ) of all multiplexers being connected to the input connection ( 9 , 11 ) are coupled, whereby
the second connection of one of the multiplexers ( 10 ) is connected to a connection for a reference potential (VSS) and the output of another of the multiplexers ( 50 ) is coupled to the output connection ( 12 , 13 ). 2. Delay device according to claim 1, characterized in that the second input of the first in the series circuit NED multiplexer ( 10 ) with the reference potential (VSS) is connected and the output of the last arranged in the series circuit multiplexer ( 50 ) with the output terminal ( 12 , 13 ) is connected. 3. Delay device according to claim 1 or 2, characterized in that the control connection ( 14 ) comprises a plurality of control bits, one of which (SLC30, / SLC30) one of the multiplexers ( 30 ) can be fed to control its switching state. 4. Delay device according to one of claims 1 to 3, characterized in that one of the multiplexers ( 30 ) comprises:
a first, a second, a third and a fourth current path ( 310 , 311 , 312 , 313 ) which each contain a switch ( 316 , 317 , 320 , 321 ) which is connected to one of the inputs ( 33 , 34 , 35 , 36 ) of the multiplexer, and each egg nen switch ( 314 , 315 , 318 , 319 ), which is connected to a bit line (SLC30, / SLC30) of the control connection ( 14 ), wherein
the current paths ( 310 , 311 , 312 , 313 ) are connected on the one hand to a current source ( 322 ) and
the current paths ( 310 , 311 , 312 , 313 ) on the other hand are coupled to a resistor element ( 324 , 325 , 326 , 327 ). 5. Delay device according to claim 4, characterized in that one of the switches ( 314 , 315 ) of the first and second current paths ( 310 , 311 ) together on a signal bit (SLC30) leading signal line ( 31 ) of the control signal (SLC) is connected and each of the other switches ( 316 , 317 ) of the first and second current paths ( 310 , 311 ) is connected to complementary signals (PRE, / PRE) leading signal lines of the second connection ( 35 , 36 ) of the multiplexer ( 30 ) , 6. Delay device according to claim 5, characterized in that one of the switches ( 318 , 319 ) of the third and fourth current path ( 312 , 313 ) together to a complementary signal bit (SLC30) leading further signal line ( 32 ) of the control signal (SLC) is connected and that another switch ( 320 , 321 ) of the third and fourth current path ( 312 , 313 ) to complementary signals (CLKIN, / CLKIN) leading signal lines ( 33 , 34 ) of the first connection of the multiple xers is connected. 7. Delay device according to one of claims 4 to 6, characterized in that the resistance elements ( 324 , 327 ) are designed in the form of transistors connected as diodes. 8. Delay device according to one of claims 4 to 7, characterized in that each of the resistance elements contains a first transistor ( 324 , 327 ), the controlled path of which is coupled on the one hand to a connection for a supply potential (VDD) and on the other hand to one of the current paths ( 310 , 312 , 311 , 313 ) that the control connection of the first transistor ( 324 , 327 ) is coupled to one of the current paths ( 310 , 312 , 311 , 313 ) and that the controlled path of the first transistor ( 324 , 327 ) is in each case the controlled route of another Transi stors ( 325 , 326 ) is connected in parallel, the Steueran circuit is coupled to a connection for a constant potential (VP). 9. Delay device according to one of claims 4 to 7, characterized in that the terminals of the current paths ( 310 , 311 , 312 , 313 ) connected to the current source ( 322 ) are coupled to a capacitor ( 323 ). 10. Delay device according to claim 9, characterized in that the current source ( 322 ) and the capacitor ( 323 ) are connected to a connection to a further supply potential (VSS), and that the capacitor ( 323 ) parallel to the current source ( 322 ) is switched. 11. Use of an integrable, controllable delay device ( 1 ) according to one of Claims 1 to 10 in a delay control loop in which, depending on a phase difference between a clock signal that can be supplied to the delay device (CLK ") and a signal (CLKOUT) that can be picked up on the output side. the delay time of the delay device ( 1 ) is adjusted. 12. A method for delaying a clock signal, comprising the steps:

• - Providing an integrable, controllable delay device according to one of claims 1 to 10;
• - Providing the clock signal to be delayed (CLKIN, / CLKIN) at the input connection ( 9 , 11 ) and providing the control signal (SLC) comprising a number of several bits (SLC10, / SLC10, SLC20, / SLC20,...) At the control connection ( 14 );
• - Setting the switching position of two series-connected ge multiplexers ( 20 , 30 ) in dependence on the bits of the control signal such that in each case a connection to be forwarded to the clock signal to be delayed between their first signal input ( 33 , 34 , 41 ) and their output connection ( 37 , 38 , 43 );
• - Setting the switching position of all other multiplexers in such a way that a signal connection between their second input port ( 22 , 52 ) and their output port ( 23 , 54 ) is established;
• - Generation of a delayed clock signal (CLKOUT, / CLKOUT) at an output terminal of the last in the series connection to ordered multiplexer; and
• Forming a phase difference between a signal (CLK ") from which the signal to be delayed (CLKIN, / CLKIN) is derived and another signal which is derived from the delayed clock signal (CLKOUT); and
• - Generating the control signal (SLC) as a function of the phase difference determined.

13. The method according to claim 12, characterized in that in the step of setting the switch position at least two multiplexers connected in series directly without the interposition of a further multi plexer are controlled by the bits of the control signal (SLC) and the output connection ( 37 , 38 ) one upstream ( 30 ) of this multiple xer is connected to the second input ( 42 ) of a downstream ( 40 ) of this multiplexer. 14. The method according to claim 12 or 13, characterized in that the two series-connected multiplexers ( 30 , 40 ) upstream multiplexers ( 10 , 20 ) are switched off to save electricity. 15. The method according to claim 14, characterized in that the multiplexers ( 10 , 20 , 30 , 40 , 50 ) for the processing of differentially feedable bits of the control signal (SLC) are formed that the upstream multiplexers ( 10 , 20 ) each Weil driven by a same first value ("00") of the control signal (SLC) that the at least two multiplexers ( 20 , 30 ) connected in series are each driven by two different bits ("01") and that the downstream switches Multiplexers ( 50 ) each of two different bits ("10") of the control signal (SLC) are driven, which are complementary to this.