DE102005046740A1 - Current mirror circuit for integrated circuit technology has current mirror with supply current of reference transistor impressed on control electrodes of mirror transistor - Google Patents

Abstract

The circuit has a current mirror with a reference transistor (T0) connected as a diode and at least one mirror transistor. The control electrodes (S0-Sn) of the transistors are coupled to a reference current source, their reference electrodes (B0-Bn) are coupled together, respective connecting lines via which the reference and control electrodes are connected together, have non-negligible resistances (R1-Rn, RG1-RGn). The supply current of the reference transistor is impressed on the control electrodes of the mirror transistor.

Description

The The present invention relates to a current mirror circuit and a Using the same.

In the integrated circuit development cause process fluctuations high deviations of the absolute values of device parameters, relative deviations, on the other hand, occur much less. The relative Tolerance then plays an important role when circumstances from sizes to Wear come. Is appropriate it therefore, if relevant sizes of a integrated circuit in fixed resistance, capacitance or geometry ratios depend.

An important relevant size in integrated circuits is constant current sources as a power supply to other circuit elements. The implementation of multiple constant current sources is usually carried out in integrated circuit technology by a current bank, which is based on the principle of a current mirror. Here, a reference current is impressed in a diode-connected transistor and converted into a voltage proportional to the reference current, which in turn is applied to the input of the mirror transistor. Such a basic circuit is, for example, from Tietze, Schenk "Halbleiterschaltungstechnik", 12th edition, page 284, 4.14a and b. If both transistors have the same dimensions, in particular their width and length ratios, the same current flows through both transistors and thus through the output path containing the mirror transistor. The literature speaks of a current bank when the reference voltage of the input circuit generated from the reference current is supplied to a plurality of output circuits.

Such a power bank can be used to realize the current sources of the multiplexer in the DE 101 49 585 A1 be applied shown controllable delay chain. It should be noted that each multiplexer stage is provided exactly the pre-calculated optimum current. If, as realized in a current bank, in the conventional current mirror arrangement a plurality of mirror transistors are provided, which are driven by the reference transistor, then it can be observed that due to the flowing currents and the non-negligible resistance of the ground line an undesired increase in potential takes place along the ground track. The reference potential generated by the reference current is the same for all reference electrodes of the mirror transistors, since no or only little current flow takes place via the control electrodes. In the case of the above-mentioned multistage delay chain, as a result of this, inaccurate signal propagation times or reduced modulation behavior will considerably impair the properties of the circuit.

When derkbare remedy often broader dimensions of the mass paths used to lower the resistance. This effort claimed valuable chip area and solve the problem is only imperfect. Likewise, it can be tried outgoing from a locally central node, the lines to the reference potential to execute the same length. In complex large-scale integrated circuits can be based on this realization lack of placement opportunity but not used become. It is also common not possible, to run the supply as a compact separate block to output currents lossless over long distances to distribute the chip.

The The object of the present invention is to provide a current mirror arrangement with little implementation effort for the circuit technology the Mirrored stream as possible set exactly and the deviation of the reference potential due the voltage drop along the line to the reference potential clearly or completely to eliminate.

The The object is achieved by a current mirror circuit according to features of independent Patent claim 1 solved. Further embodiments of the inventive concept are characterized in the subclaims.

According to the invention, the current bank is formed by a current mirror circuit arrangement with a current mirror of a diode-connected reference transistor and at least one mirror transistor, wherein the control electrodes of the transistors are coupled to a reference current source, the reference electrodes of the transistors are coupled together, connecting lines through which the Reference electrodes and the control electrodes are connected to each other, with non-negligible resistances are afflicted, and the supply current of the reference transistor is impressed in the control electrode of the mirror transistor.

A Use of such a circuit device is, for example specified in claim 9.

In a particular embodiment of the power bank is in a variety of mirror transistors, their control electrodes and reference electrodes are each connected to each other, which is one end of the arrangement of Mirror transistors connected to the reference transistor and another end of the arrangement of the mirror transistors to the reference current source connected. It is particularly advantageous by largely negligible Implementation effort in the design technique a complete compensation or very good partial compensation of the potential increase along the line, to which the reference potentials of the transistors are connected, to achieve. In the current mirror circuit according to the invention, the impressed reference current flows along the entire line to which the gate or control electrodes are connected are. This also causes a potential increase along this Conduction, the potential increase along the line at which the Reference electrodes are connected, partially or completely compensate.

In In another advantageous embodiment, the transistors are placed on the integrated chip such that the connections the reference electrodes and the control electrodes each have the same length and are the same width. Due to the symmetrical arrangement same long and equal sections a line for the Connection of the gate or Source electrodes can with little computational effort the partial compensation the voltage drop along the reference potential line done.

In a further advantageous embodiment of the current mirror circuit according to the invention All mirror transistors have the same channel width to channel width ratio. Of particular advantage here is that an influence of manufacturing tolerances is minimized in the realization of the transistors and the design of the cuts a line for compensating voltage drop along the reference potential line considerably simplified.

The Realization of a partial or complete compensation of the reference potential is not on any particular technology of the manufacturing process of the Transistor limited. Particularly advantageous is the use of bipolar transistors at Applications in high-speed logic and high-frequency engineering, whose Properties, such as dynamics, in particular of the Depend on operating point settings, which are preferably determined by current sources.

In an advantageous embodiment the current mirror circuit according to the invention All mirror transistors are realized with the same emitter surface Service. Of particular advantage here is that an influence of Manufacturing tolerances in the realization of the transistors minimized and the determination of the sections of a line leading to Compensation of voltage drop along the reference potential line considerably simplified.

following The invention is based on a preferred embodiment with reference to the accompanying drawings explained in detail. Show it:

1 a circuit diagram of a preferred embodiment of a current bank according to the invention, realized with n-channel MOS transistors;

2 the application of a current mirror circuit according to the invention in a controllable delay chain;

3 for a current bank according to the invention, the graphical representation of the deviation of the drain current from its target value as a function of the number of mirror transistors used in the case of complete compensation, in the case of partial compensation and in the case of a conventional previous implementation;

4 a schematic representation of a conventional power bank; the drawn resistors correspond to the resistance values occurring on the conductor track sections.

The circuit arrangement in 4 shows a conventional current mirror assembly. Schematically and simplified, a typical embodiment of a current bank consisting of N-channel MOS transistors is shown. According to the 4 are all the partial resistances R _{1 ... n of} the conductor track, to which the source electrodes of the mirror transistors are connected, the same size. One end of the mirror transistor arrangement is connected to the reference transistor T ₀ , which is designed as a diode and is connected via the control electrode to the reference _current source I _REF . At the drain electrodes of the mirror transistors T _{1... N} , the operating point-determining output currents I _{D1... Dn of} the integrated circuit to be supplied, for example for the multiplexers 10 . 20 . 30 . 40 . 50 the in 2 illustrated delay chain 1 , made available.

According to 4 In this case, the output currents I _D1 to I _{Dn are} in the ideal case to the reference current I _REF in a constant gear ratio, which results from the channel width to channel length ratios of the transistors. In the in 4 realized known current mirror arrangement applies this assumption, however, only under the condition if all line resistances R ₁ to R _{n have} an extremely low resistance, that is R ₁ = 0 to R _n = 0, and all transistor designs are implemented according to the Laynutkriterien. Due to unavoidable asymmetries in real transistors, it is known that in practice a more or less large random error that can be reduced by special measures in the layout of the transistors.

Im as described here. In the case of a current bank with mirror transistors T _{1... N} distributed over the chip, an additional frequently underestimated further systematic error is added. The converging on the trace of the reference potential currents I _{D1 ... Dn of} the distributed across the chip mirror transistors T _{1 ... n} cause a potential increase along this trace due to the not insignificant line resistances R _{1 ... n} . How out 4 can be seen, therefore, take the line resistances R ₁ to R _n values greater than zero and consequently set at the mirror _transistors T _{1 ... n} different gate-source voltages U _GS1 to U _GSn . This is because, in contrast to the reference potential at the source electrodes of the mirror transistors, the potential U _REF on all the control electrodes for all transistors T ₀ to T _n is the same due to the high input resistance of the n-channel transistors. This potential difference causes a deviation of the output-side drain currents I _{D1 ... Dn} from their desired values. Since the voltage drop along a trace to which the reference electrodes of the transistors are connected increases with the current, the deviation from the target value is greater the higher the output currents or the larger the number of mirror transistors. In 4 are entered simulation values that show a constant potential U _REF at the control electrodes for all transistors T ₀ to T _n and show the course of the voltage drop at the reference potentials of the mirror transistors T ₁ to T _n .

In the 1 illustrated current mirror circuit arrangement according to the invention includes a reference transistor T ₀ .

This is designed as an n-channel MOS Transistoz. Its drain and gate connections are interconnected. The source terminal of the reference transistor T ₀ is connected to a terminal for the ground potential GND. Connected to the gate and drain terminals of the reference transistor T ₀ is a connection line which leads to the gate terminals of a plurality of further transistors T ₁ , T ₂ , ... T _n . The transistors T ₁ , T ₂ , ... T _n are all connected in the same way. By way of example, the source terminal of the transistor T ₂ with the connecting line having the resistor R ₂ is connected to the source terminal of the transistor T ₁ , the gate terminal of the transistor T ₂ is connected to the connecting line, the resistor R _G2 has, connected to the gate terminal of the transistor T ₁ . At the drain electrode Q _{2 of} the transistor T ₂ , the constant current I _{D2 is provided on the} output side. The gate terminal of the transistor T _n is connected to the reference _current source I _REF .

In a preferred embodiment of the current bank according to the invention 1 are all transistors T ₀ to T _n type N-MOS and all output currents I _D1 to I _Dn are the same size, ie all the mirror transistors T _{1 ... n} have the same channel-to-channel length ratio. In addition, all partial resistors R _{1... N of} the conductor track, to which the source electrodes of the mirror transistors are connected, have the same size. The wiring length to the individual gate electrodes is always the same length and realized with a constant width. One end of the mirror transistor arrangement is connected to the reference transistor T ₀ , which is designed as a diode. The gate at the other end of the mirror _{transistor array is} connected to a reference _current source I _REF . At the drain electrodes of the mirror transistors T _{1... N} , the operating point-determining output currents I _D1 to I _{Dn of} the integrated circuit to be supplied, for example for the in 2 shown delay chain provided.

The realized current bank according to the invention 1 causes the reference potential U _REF to be _varied by the amounts of voltage drops along the conductor lines R _G1 to R _Gn to which the gate electrodes are connected. As a result, depending on the dimensioning of the gate conductor resistors R _G1 to R _Gn, the increase in the corresponding source potentials U _GS1 to U _{GSn can be} partially or completely compensated. The gate-source voltages U _GS1 to U _{GSn of} the mirror _transistors T ₁ to T _n thus vary less strongly or not at all. There are also no fundamental difficulties in layout design.

If all the wiring paths to which the gates of the mirror transistors T ₁ to T _{n are} connected are each selected to be the same length and the same width, then R _G1 = R _G2 =... = R _G. If, in addition, as mentioned in the assumptions above, equally sized transistors T ₁ to T _n with the same channel width-to-channel length ratio are used, ideally all drain currents I _D = I ₁ = I ₂ = ... = I _Dn amount. A complete compensation is not possible in this case, since the potential increase at the gates of the mirror transistors T ₁ to T _{n is} linear, the potential increase at the source terminals B _{0 ... n,} however, not. While it is not possible to specify an exact solution in the form of a closed mathematical expression, it is possible with the aid of the following simplified consideration to provide a first approximation value for determining the gate trace resistance R _G , which is subsequently determined with the aid of a circuit analysis program, for example SPICE, can be further optimized.

The voltage drop .DELTA.U _k, the n track resistors, which connects the kth source electrode of n source electrodes, falls on the k-th path resistance is then .DELTA.U _k = R · I _D · (1 + n - k). The potential U _n which drops at the source of the n-th mirror transistor is equal to the sum of all the voltage drops across the n resistors connected by n mirror transistors. For this, the following closed expression can be specified:

. Theoretisch erreicht hierbei nur die Gate-Source-Spannung U_GSn des letzten Spiegeltransistors den Referenzwert U_GS0 der Diode T₀, was bedeutet, dass nur I_Dn dem Sollwert entspricht. Für alle anderen Ausgangsströme der Spiegeltransistoren fallen aufgrund von Unterkompensation die Drainströme niedriger aus. Da dies offensichtlich im Widerspruch zu der getroffenen Annahme gleich großer Ströme steht, liefert

in Wirklichkeit nur einen groben Näherungswert, der lediglich eine Abschätzung der zu erwartenden Größenordnung für R_G zulässt. Als Faustregel für die praktische Dimensionierung kann gelten, dass R_G in der Nähe des Optimums liegt, wenn der Verlauf der Funktion I_D(k) dem Graphen gemäß 3 für den teilkompensierten Fall entspricht. Hierbei ergibt sich für die ersten etwa 2/3 der Spiegeltransistoren eine leichte Unterkompensation, die Ausgangsströme sind dementsprechend kleiner als der Sollwert, während für etwa 1/3 der letzen Spiegeltransistoren eine Überkompensation vorliegt. Die Fehlersumme ergibt etwa Null. Der optimale Wert für R_G wird am besten mit Hilfe eines Schaltungssimulators durch Probieren ermittelt. Die Breite der Leiterbahn, die die Gates verbindet, kann anschließend dementsprechend festgelegt werden. In 1 sind Simulationswerte eingetragen, die aufgrund erfolgter Teilkompensation die Abweichungen des Referenzpotentials U_REF an den Steuerelektroden für alle Transistoren T₁ bis T_n zeigen und den Verlauf des Spannungsabfalls an den Bezugspotentialen der Spiegeltransistoren T₀ bis T_n zeigen.Assuming first of all the condition to be met, the potential U _Gn at the gate of the nth transistor should increase by the same amount as the potential at the source, ie U _Gn = n * R _G * I _REF = U _n Immediately the relationship

, Theoretically, only the gate-source voltage U _{GSn of} the last mirror _{transistor reaches} the reference value U _{GS0 of} the diode T ₀ , which means that only I _Dn corresponds to the desired value. For all other output currents of the mirror transistors, the drain currents are lower due to under-compensation. Since this obviously contradicts the assumption of equally large currents, supplies

in reality only a rough approximation, which allows only an estimate of the expected order of magnitude for R _G. As a rule of thumb for the practical dimensioning, it can be said that R _{G is} close to the optimum, if the course of the function I _D (k) is according to the graph 3 for the partially compensated case. This results in the first about 2/3 of the mirror transistors, a slight undercompensation, the output currents are accordingly smaller than the desired value, while for about 1/3 of the last mirror transistors over-compensation is present. The error sum is approximately zero. The optimum value for R _G is best determined by trial and error using a circuit simulator. The width of the track connecting the gates can then be determined accordingly. In 1 are entered simulation values that show due to partial compensation the deviations of the reference potential U _REF at the control electrodes for all transistors T ₁ to T _n and show the course of the voltage drop at the reference potentials of the mirror transistors T ₀ to T _n .

A full Compensation can be achieved, for example, by adding the parts of the Gate interconnects of different sizes resistors can be realized. One potential Design idea is, the length of the cuts the tracks that connect the gates have the same length, the width of the tracks, however, to be determined by simple calculation.

. In 4 ist beispielhaft der auf I_REF normierte Verlauf I_D(k) für den Fall der vollständigen Kompensation als konstante Funktion dargestellt.The exact calculation of the width of the gate lead resistances is relatively simple, the practical Realization of the layout requires a slightly increased realization effort. There, as in 1 represented, flows through the track resistance R _1, the current n · I _D , R _G1 must accordingly be n times of R ₁ accordingly. The last, that is, the nth, gate trace resistance is the smallest and corresponds to the value of R. The general rule is for the kth gate trace resistance

, In 4 _{By way of} example, the course I _D (k) normalized to I _{REF is} shown as a constant function in the case of complete compensation.

For the in 2 illustrated delay chain 1 can supply the power by a 1 corresponding current mirror arrangement can be realized. The current source I10 is, for example, through the transistor T _{1 of} the circuit in

1 educated. The input clock signal CLKIN is supplied as a differential, complementary signal components CLKIN and / CLKIN comprehensive signal. The delay unit 1 will be at the entrances 9 . 11 an input clock signal CLKIN to be delayed as well as the complementary input clock signal / CLKIN. Output side is at the terminals 12 . 13 a turn differentially delayed output clock signal with in-phase component CLKOUT and antiphase component / CLKOUT tapped. The delay time between the input clock signal and the output clock signal is controlled in response to a signal SLC. The signal SLC has a plurality of bits, SLC10, SLC20, etc., each comprising normal and complementary components, and a terminal comprising a plurality of bit lines 14 be supplied. All signal processing in the delay line 1 is therefore differentially. The voltage swing of the inputs and outputs of a delay stage 10 is limited. The signals SLC, / SLC are full signals and therefore quasi static. The delay unit comprises a plurality of multiplexers connected in series, of which, for example, the multiplexers 10 . 20 . 30 . 40 . 50 are shown. All multiplexers have the same internal structure. Exemplary is the multiplexer 30 explained in detail. A first respective differential signals leading signal input 33 . 34 of the multiplexer 30 is as well as all other comparable inputs of the remaining multiplexers to the ports 9 . 11 coupled to perform the differential input signal CLKIN, / CLKIN. The second differential input 35 . 36 of the multiplexer is connected to the differential output of the upstream multiplexer 20 connected. The differential outputs 37 . 38 are in a similar manner to the second input of the downstream multiplexer 40 connected. At the differential control terminals 31 . 32 For example, the corresponding bit of the control signal SLC30, / SLC30 is differentially supplied. The output of the last multiplexer arranged in series 50 is with the outputs 12 . 13 the delay unit 1 connected. The second input of the first in the series connection of the multiplexer arranged multiplexer 10 is connected to the ground potential VSS. The size of the delay time between the differential inputs 9 . 11 and the differential outputs 12 . 13 for the supplied differential input signal CLKIN, / CLKIN is determined by the number of multiplexers that the clock signal between input and output of the delay unit 1 passes. In the case shown, the input clock signal CLKIN, / CLKIN becomes the multiplexer 30 supplied and passes through all the downstream multiplexer 40 . 50 , The signal path is shown in dashed lines and with 60 designated. These are all, the multiplexer 30 upstream multiplexer, so the multiplexer 10 . 20 , Set so that the signal path set in the respective multiplexer is connected to the respective output with the second, that is shown in the drawing below input. The same switching setting has the downstream multiplexer 40 . 50 so that they forward the signal supplied to them at the second input, that is to say below, to their output. Only the multiplexer 30 has a different setting of its signal path. With him are the exits 37 . 38 with the first differential input 33 . 34 connected. The input clock signal CLKIN thus becomes the multiplexer 30 supplied at the first input and passes through all the downstream multiplexer 40 . 50 to get to the differential output 12 . 13 to arrive, as by the dashed signal path 60 is registered. This circuit has the advantage that the input 9 . 11 largely independent of the switching state always has the same capacitive load. By a correspondingly large, the entrance 9 . 11 Controlling drivers can be compensated for any capacity variations. The exit 12 . 13 also provides the same driver power for downstream circuits. The switching setting of the respective multiplexers is determined by corresponding bits of the control signal SLC. The respective bits are supplied as complementary signals to the multiplexers.

The delay device in 2 has by using the in 1 In the basic structure illustrated current mirror assembly a very linear and accurate control area.

3 shows simulated courses of drain currents related to I _REF as a function of the number k of the mirror transistors used for three cases: the course of the drain current with respect to the reference current I _D (k) / I _REF for the case of a nonexistent compensation (curve by diamond symbols marked), for the case of partial compensation (gradient marked by rectangle symbols) and the case of complete compensation (gradient marked by triangle symbols).

U _DD

supply voltage

T ₀

reference transistor

T _{1 ... n}

Mirror transistors T _{k = 1 ... k = n} , running index k, maximum number n

U _REF

reference voltage

I _REF

reference current

U _GS0

Gate source voltage of T ₀

U _{GS1 ... GSn}

Gate source voltage of a transistor T _{k = 1 ... k = n}

R _{1 ... n}

Conductor resistance of the supply line to the reference electrode of a transistor T _{k = 1 ... k = n}

R _{G1 ... Gn}

Conductor resistance of the supply line to the control electrode of a transistor T _{k = 1 ... k = n}

I _{D1 ... Dn}

Output current of a transistor T _{k = 1 ... k = n}

S _{0 ... n}

Control electrodes of a transistor T _{k = 0 ... k = n}

B _{0 ... n}

Reference electrodes of a transistor T _{k = 0 ... k = n}

Q _{1 ... n}

Output electrode of a mirror transistor T _{k = 1 ... k = n}

GND

ground potential U = 0 volts

1

delay means

9 11

input terminals

12 13

output terminals

14

control connection

10 20, 30,

40 50

multiplexer

33 34

first Input terminal of a multiplexer

35, 36

second Input terminal of a multiplexer

37, 38

output port

31 32

control connection

VDD

supply voltage

VSS

ground potential

SLC

control signal

CLKIN

to retarding input

CLKOUT

delayed output signal

PRE

input

OUT

output

I10, I20,

I30, I40,

I50

Power source for multiplexer 10 . 20 . 30 . 40 . 50

Claims (9)

Current mirror circuit arrangement comprising a current mirror with a diode-reference transistor (T ₀₎ and at least one mirror transistor (T _1), wherein the control electrode (S _0, S ₁₎ of the transistors (T _0, T ₁₎ having a reference current source (I _REF ), the reference electrodes (B ₀ , B ₁ ) of the transistors (T ₀ , T ₁ ) are coupled together, respective connecting lines, by which the reference electrodes and the control electrodes are connected to each other, with non negligible resistors (R _G1 , R ₁ ), characterized in that the supply _current (I _REF ) of the reference transistor (T ₀ ) in the control electrode (S ₁ ) of the mirror transistor (T ₁ ) is impressed. Current mirror circuit arrangement according to claim 1, characterized in that a plurality of mirror transistors (T _{1 ... n} ) is provided, the control electrodes (S _{0 ... n} ) verbun together and their reference electrodes (B _{0 ... n} ) are connected together so that a mirror transistor arrangement is formed, that one end of the control electrode connection of the mirror transistor arrangement is connected to the reference transistor (T ₀ ) and another end of the control electrode connection of the mirror transistor arrangement to the Reference _current source (I _REF ) is connected. Current mirror circuit arrangement according to claim 1 or 2, characterized in that the transistors (T ₀ ... T _n ) are arranged on an integrated semiconductor chip and the mirror transistors (T _{1 ... n} ) are arranged equidistant from each other. Current mirror circuit arrangement according to one of claims 1 to 3, characterized in that the transistors (T ₀ ... T _n ) are formed as bipolar transistors. Current mirror circuit arrangement according to one of claims 1 to 3, characterized in that the transistors (T ₀ ... T _n ) are formed as field effect transistors. Current mirror circuit arrangement according to one of claims 1 to 5, characterized in that the reference transistor (T ₀ ) and the mirror transistor (T _{1 ... n} ) are of the same conductivity type. Current mirror circuit arrangement according to one of claims 1 to 6, characterized in that that the mirror transistors (T _{1 ... n} ) have the same channel width to channel length ratio. Current mirror circuit arrangement according to claim 4, characterized in that that the mirror transistors (T _{1 ... n} ) have the same emitter area. Use of the current mirror circuit arrangement according to one of the preceding claims in a circuit arrangement which comprises a delay device ( 1 ) equipped with multiplexers ( 10 . 20 . 30 . 40 . 50 ), wherein multiplexers each contain current sources (I10, I20, I30, I40, I50), which are each realized by a mirror transistor.