CN109194313B - Storage unit access control system, method and device - Google Patents
Storage unit access control system, method and device Download PDFInfo
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- CN109194313B CN109194313B CN201810936410.5A CN201810936410A CN109194313B CN 109194313 B CN109194313 B CN 109194313B CN 201810936410 A CN201810936410 A CN 201810936410A CN 109194313 B CN109194313 B CN 109194313B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
Abstract
The embodiment of the invention provides a system, a method and equipment for controlling access to a storage unit, wherein the system comprises the following components: the clock deviation adjuster is configured with a delay time of a first trigger signal corresponding to the controller and a delay time of a second trigger signal corresponding to the storage unit; the clock crystal oscillator outputs a clock signal to the clock deviation regulator; the first output end of the clock deviation regulator is connected with the controller through a first path, and the second output end of the regulator is connected with the storage unit through a second path; the clock deviation regulator is used for carrying out delay processing on the clock signal according to the first path delay time so as to output a first trigger signal to the controller at a first moment; and performing delay processing on the clock signal according to the second path delay time to output a second trigger signal to the storage unit at a second time. By the scheme for adjusting the clock signal based on the clock skew, the efficiency of accessing the memory unit can be effectively improved.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a system, method, and device for controlling access to a storage unit.
Background
In the application of data transmission and access to the storage unit, the specific access period is fixed; the receiving unit, the transmitting unit and the storing unit for the controller are all performed according to the same access cycle.
In the prior art, clock skew occurs due to errors in data routing (e.g., PCB routing) between units at the time of design, etc. Due to the occurrence of the clock skew problem, data access and data transmission cannot be performed synchronously, so that the access efficiency for the memory unit is low. In order to avoid the occurrence of the problems, the product is usually detected in the product production detection stage, and if the time offset of the product is detected to exceed the preset time offset threshold, the product is determined to be a defective product, so that the product reject ratio is high.
Based on this, a scheme for improving the access efficiency to the memory unit is needed.
Disclosure of Invention
In view of this, embodiments of the present invention provide a system, a method, and a device for controlling access to a storage unit.
In a first aspect, an embodiment of the present invention provides a storage unit access control system, including: the clock skew adjuster comprises a clock crystal oscillator, a clock skew adjuster, a controller and a storage unit;
the clock skew adjuster is configured with a delay time of a first trigger signal corresponding to the controller and a delay time of a second trigger signal corresponding to the memory cell;
the clock crystal oscillator outputs a clock signal to the clock deviation regulator;
a first output terminal of the clock skew regulator is connected to the controller via a first path, and a second output terminal of the clock skew regulator is connected to the memory unit via a second path;
the clock deviation regulator is used for carrying out delay processing on the clock signal according to the first path delay time so as to output a first trigger signal to the controller at a first moment; and carrying out delay processing on the clock signal according to the second path delay time so as to output a second trigger signal to the storage unit at a second moment.
Further, the clock offset regulator includes: a clock adjustment control unit and a delay selector;
the clock crystal oscillator is connected with the delay selector and used for providing the clock signal for the delay selector;
the clock regulation control unit is connected with the delay selector;
the first output end of the delay selector is connected with the controller and used for providing a first trigger signal for the controller;
the second output terminal of the delay selector is connected to the storage unit, and is configured to provide a second trigger signal to the storage unit.
Further, the controller includes: a receiving unit and a transmitting unit;
the first output terminal includes: a first transmitting output terminal connected to the transmitting unit and a first receiving output terminal connected to the receiving unit;
transmitting a first transmission trigger signal to the transmission unit through the first transmission output terminal; the first receiving output end is connected with the receiving unit and used for sending the first receiving trigger signal.
In a second aspect, an embodiment of the present invention provides an electronic device, including the storage unit access control system described in any one of the first aspects.
In a third aspect, an embodiment of the present invention provides a method for controlling access to a memory unit,
acquiring a clock signal provided by a clock crystal oscillator;
the clock signal is subjected to delay processing based on preset delay time to obtain a first trigger signal and a second trigger signal, so that the first trigger signal is sent to a controller at a first moment and the second trigger signal is sent to a storage unit at a second moment;
wherein the first time and the second time are different times.
Further, the delaying the clock signal based on the preset delay time to obtain the delayed first trigger signal and the delayed second trigger signal, so as to send the first trigger signal to the controller at the first time and send the second trigger signal to the storage unit at the second time, includes:
based on the clock signal, sending a first trigger signal to the controller at a first moment; the first trigger signal delays the clock signal according to a first path delay time, and determines a first moment for triggering the first trigger signal;
sending a second trigger signal to the storage unit at a second moment based on the clock signal; the second trigger signal delays the clock signal according to a second path delay time, and determines a second moment for triggering the second trigger signal;
wherein a difference between the first time and the second time is equal to a difference between the first path delay time and the second path delay time.
Further, the delaying the clock signal based on the preset delay time includes:
and taking a first difference value between the first path delay time and the second path delay time as the preset delay time, and carrying out delay processing on the first trigger signal or the second trigger signal.
Further, if the first path delay time and/or the second path delay time is greater than a preset delay time threshold, the clock signal is delayed based on the preset delay time threshold, and the delayed first trigger signal and/or the delayed second trigger signal are/is output.
An embodiment of the present invention provides a computer storage medium, which is used to store a computer program, and the computer program enables a computer to implement the method for controlling access to a storage unit in the first aspect when executed.
According to the memory unit access method provided by the embodiment of the invention, a plurality of trigger signals aiming at different memory units and controllers are respectively set based on the same clock cycle, and the trigger time of each trigger signal is adjusted according to the delay time of each path, so that each trigger signal can be ensured to reach an accessed unit at the same time. By the scheme for adjusting the clock signal based on the clock skew, the efficiency of accessing the memory unit can be effectively improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a storage unit access system according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of another memory cell access system according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of another memory unit access system according to an embodiment of the present invention;
fig. 4 is a flowchart illustrating a method for accessing a memory cell according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, and "a" and "an" generally include at least two, but do not exclude at least one, unless the context clearly dictates otherwise.
It should be understood that the term "and/or" as used herein is merely a relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B, may represent: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
The words "if", as used herein, may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to a detection", depending on the context. Similarly, the phrases "if determined" or "if detected (a stated condition or event)" may be interpreted as "when determined" or "in response to a determination" or "when detected (a stated condition or event)" or "in response to a detection (a stated condition or event)", depending on the context.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a good or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such good or system. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of additional like elements in the article of commerce or system in which the element is comprised.
In addition, the sequence of steps in each method embodiment described below is only an example and is not strictly limited.
When data access is performed to the memory cell, the data access is performed based on the same clock crystal, and the system or the apparatus has the same clock signal cycle. However, the path delay times are different from each other due to the difference in the signal transmission routes of the respective units. Therefore, in order to ensure that signals can be transmitted and processed synchronously, the influence of path delay on signal transmission needs to be minimized, and the influence of time offset can be eliminated.
Fig. 1 is a schematic structural diagram of a storage unit access control system according to an embodiment of the present invention, including: a clock crystal 10, a clock deviation adjuster 20, a controller 30 and a storage unit 40;
the clock skew adjuster 20 is configured with a delay time of a first trigger signal corresponding to the controller 30 and a delay time of a second trigger signal corresponding to the storage unit 40; the clock crystal 10 outputs a clock signal to the clock deviation adjuster 20; a first output of the clock skew adjuster 20 is connected to the controller 30 via a first path, and a second output of the clock skew adjuster 20 is connected to the storage unit 40 via a second path; the clock deviation adjuster 20 is configured to delay the clock signal according to a first path delay time, so as to output a first trigger signal to the controller 30 at a first time; and performing delay processing on the clock signal according to the second path delay time to output a second trigger signal to the storage unit 40 at a second time.
It should be noted that, in the storage system, a plurality of units to be accessed may be simultaneously included, for example, the controller may simultaneously include the receiving unit and the sending unit. Different units have different data access paths, each access path corresponding to a clock signal. Therefore, in practical applications, it is also possible to include a plurality of clock signals, such as a third clock signal, a fourth clock signal, corresponding to a third path delay time, a fourth path delay time, and so on. The first trigger signal, the second trigger signal, the first path delay time, and the second path delay time mentioned herein are understood as examples, and do not limit the implementation manner of the technical solution of the present application.
The first path delay time refers to the time required for the clock signal to reach the controller from the clock signal clock regulation control unit; for the sake of distinction, the signal sent to the controller may be referred to as a first trigger signal. The second path delay time refers to the time required for the clock signal to reach the memory cell from the clock signal clock adjustment control unit; for ease of distinction, the signal sent to the controller may be referred to as the second trigger signal. The relationship between the first path delay time and the second path delay time as referred to herein may be understood as the magnitude relationship between the time consumed by the two paths.
The delay time of the first trigger signal or the delay time of the second trigger signal may be zero or may not be zero.
For the sake of easy understanding, it is assumed herein that the first path delay time is 40 microseconds and the second path delay time is 60 microseconds, the first time to trigger the first trigger signal T1 for the controller is T1, and the second time to trigger the second trigger signal T2 for the memory cell is T2, for specific examples. In order to enable the first trigger signal T1 and the second trigger signal T2 to reach the controller and the memory cell, respectively, at the same time, the trigger time of T2 may be 20 μ s earlier than the trigger time of T1, so that the controller and the memory cell can be simultaneously connected to their respective clock signals even though T1 and T2 remain unchanged.
A plurality of trigger signals aiming at different storage units and controllers are respectively set based on the same clock period, and the trigger time of each trigger signal is adjusted according to the delay time of each path, so that each trigger signal can be ensured to reach an accessed unit at the same time. By the scheme of adjusting the clock signal based on the clock skew, the efficiency of accessing the storage unit can be effectively improved; and the influence on the detection performance of the product due to path delay can be avoided, so that the yield of the product is improved.
In one or more embodiments of the present disclosure, as shown in fig. 2, the clock skew adjuster 20 includes: a clock adjustment control unit 21 and a delay selector 22;
the clock crystal 10 is connected to the delay selector 22, and is configured to provide the clock signal to the delay selector 22; the clock adjustment control unit 21 is connected to the delay selector 22, and configured to assign a port connection relationship to the delay selector 22; a first output terminal of the delay selector 22 is connected to the controller 30 for providing a first trigger signal to the controller 30; a second output of the delay selector 20 is connected to the memory unit 40 for providing a second trigger signal to the memory unit 40.
In practical applications, a clock crystal 10 is generally required in a control system of a storage unit, so as to ensure that the frequency or period of data processing of each unit is consistent.
The same clock skew adjuster 20 may correspond to multiple controllers 30 and multiple storage units 40 at the same time, and in order to implement that the clock skew adjuster 20 can send the specified delayed clock signal to the designated unit, the clock adjustment control unit 21 is required to provide an accurate port connection relationship for the delay selector 22. For example, a first trigger signal is sent to controller 30 via a first output port and a second trigger signal is sent to memory unit 40 via a second output port.
In one or more embodiments of the present disclosure, as shown in fig. 3, the controller 30 includes: a receiving unit 31 and a transmitting unit 32;
the first output terminal includes: a first transmission output terminal connected to the transmission unit 32 and a first reception output terminal connected to the reception unit 31;
the first transmission output terminal transmits a first transmission trigger signal to the transmission unit; the first receive output terminal sends a first receive trigger signal to the receive unit.
Among the controllers 30 in the storage unit, a receiving unit 31 for receiving the first trigger signal and a transmitting unit 32 for receiving the second trigger signal are often included. In practical applications, although the receiving unit 31 and the transmitting unit 32 are in the same controller 30, two different paths are required to implement the transmission of the clock signal, and therefore, in order to implement the precise control of the clock signal, the first trigger signal needs to be divided into a first receiving trigger signal and a first transmitting trigger signal for respectively transmitting signals to the receiving unit 31 and the transmitting unit 32.
Based on the same idea, an embodiment of the present specification further provides a storage unit access control method, as shown in fig. 4, the specific method steps include:
step S402: and acquiring a clock signal provided by a clock crystal oscillator.
As can be seen from the foregoing, only one clock crystal is often required to provide a clock signal in the same memory cell access control system.
For example, assuming that the period of the clock signal of the clock crystal is T, in order to ensure that the system can synchronously implement data processing, the clock periods for different units (e.g., controllers, memory units) are all the same. Therefore, T, T1 and T2 are generally the same. The delay or adjustment referred to herein is adjustment of the trigger timing of each clock signal, and is not adjustment of the clock cycle extension or shortening.
Step S404: the clock signal is subjected to delay processing based on preset delay time to obtain a first trigger signal and a second trigger signal, so that the first trigger signal is sent to a controller at a first moment and the second trigger signal is sent to a storage unit at a second moment; wherein the first time and the second time are different times.
It should be noted that the execution subject of the method may be a clock offset regulator, which is used to process the received clock signal, for example, delay the clock signal, so as to change the triggering time of the clock signal, and ensure that both the memory unit and the controller can receive the triggering signal in the current cycle at the same time.
Based on the above embodiment, the delaying the clock signal based on the preset delay time to obtain the delayed first trigger signal and the delayed second trigger signal, so as to send the first trigger signal to the controller at the first time and send the second trigger signal to the storage unit at the second time, includes:
based on the clock signal, sending a first trigger signal to the controller at a first moment; the first trigger signal delays the clock signal according to a first path delay time, and determines a first moment for triggering the first trigger signal;
sending a second trigger signal to the storage unit at a second moment based on the clock signal; the second trigger signal delays the clock signal according to a second path delay time, and determines a second moment for triggering the second trigger signal;
wherein a difference between the first time and the second time is equal to a difference between the first path delay time and the second path delay time.
For example, assume that the first path delay time is T1, the second path delay time is T2, and T1 is less than T2; then, T3 is the time difference between T1 and T2, i.e., T3 — T2-T1; assuming that the first time is t1 and the second time is t2, t3 is t2-t 1; further, T3 ═ T3. Specifically, if the first path delay time is smaller than the second path delay time, the trigger time (second time t2) of the second trigger signal needs to be triggered earlier. In practical application, T1 may be delayed by a time length of T3; alternatively, T1 is delayed by one-half of the time length of T3 while T2 is advanced by one-half of the time length of T3.
Based on the foregoing embodiment, the performing delay processing on the clock signal based on the preset delay time specifically may include: and taking a first difference value between the first path delay time and the second path delay time as the preset delay time, and carrying out delay processing on the first trigger signal or the second trigger signal.
If the first path delay time is longer than the second path delay time, setting a first time for triggering the first trigger signal aiming at the controller to be earlier than a second time for triggering the second trigger signal aiming at the storage unit in the same clock signal period;
and if the first path delay time is less than the second path delay time, setting a first time point of triggering the first trigger signal aiming at the controller to be behind a second time point of triggering the second trigger signal aiming at the storage unit in the same clock signal period.
When the first time and the second time are adjusted, the relationship between the delay time of the first path and the delay time of the second path and the preset delay time threshold value needs to be comprehensively considered. It is assumed that the first case is that the first path delay time T1 and the second path delay time T2 both exceed the preset delay time threshold Tr; the second case is that the first path delay time T1 and the second path delay time T2 are not assumed to exceed the preset delay time threshold Tr; a third case is to assume that only one delay time exceeds a preset delay time threshold Tr. Since the solution of the third case is similar to the first case, the following description focuses on the distance between the first case and the second case.
In the first case: assume T1 is 40 microseconds, T2 is 60 microseconds, Tr is 35 microseconds; in order to pass both the first path delay time T1 and the second path delay time T2, it is necessary to advance at least the trigger time T1 of the first path delay time T1 by 5 microseconds (40-35-25-microseconds), and the trigger time T2 of the second path delay time T2 by 25 microseconds (60-35-25-microseconds). In practical applications, to avoid the influence of unstable factors (such as signal interference or temperature influence) on the path delay time, t1 may be advanced by 6 microseconds or 10 microseconds, and t2 may be advanced by 26 microseconds or 30 microseconds. It should be noted that the difference between the time length of the T1 advance and the time length of the T2 advance is the same as the difference between T2 and T1.
In the second case: assume that the first path delay time T1 is 40 microseconds, the second path delay time T2 is 60 microseconds, Tr is 65 microseconds; because both T1 and T2 have passed, only consideration needs to be given to how to maintain synchronization of the first trigger signal with the second trigger signal. Therefore, the triggering time of the second trigger signal, the second time T2, needs to be advanced by 20 microseconds (i.e., T2-T1 ═ 20 microseconds). Of course, the triggering time of the first trigger signal may be delayed by 10 microseconds from the first time t1, and the triggering time of the second trigger signal may be advanced by 10 microseconds from the second time t 2.
Based on the above embodiment, if the first path delay time and/or the second path delay time is greater than a preset delay time threshold, the clock signal is delayed based on the preset delay time threshold, and the delayed first trigger signal and/or second trigger signal are/is output.
In practical applications, particularly in the product testing and production stages, the time shift condition of the product needs to be detected and judged. A delay time threshold is usually set, for example, assuming that the delay time threshold is Tr. If T1 and/or T2 is greater than the delay time threshold Tr, the difference between T1 and/or T2 and Tr needs to be calculated, assuming Tr1 or Tr 2. To pass the product test, the triggering times T1 and/or T2 of T1 and/or T2 may be advanced by Tr1 and/or Tr 2.
It should be noted that if neither T1 nor T2 exceeds Tr, the signal trigger timing does not need to be adjusted according to the threshold.
Based on the above embodiments, it can be understood that a plurality of trigger signals for different memory cells and controllers are respectively set based on the same clock cycle, and the trigger time of each trigger signal is adjusted according to the delay time of each path, so that it can be ensured that each trigger signal can reach the accessed unit at the same time. By the scheme of adjusting the clock signal based on the clock skew, the access efficiency of the storage unit can be effectively improved, and the influence on the detection performance of the product due to path delay can be avoided, so that the yield of the product is improved; meanwhile, if the signal frequency requirement is not very high, the clock signal trigger frequency can be reduced, the clock power supply voltage is reduced, and the effect of reducing power consumption can be achieved.
The internal functions and structures of the memory cell access control system are described above, and in one possible design, the structure of the memory cell paradigm control system can be implemented as an electronic device, such as a computer, a single chip, and the like, including: the clock skew adjuster comprises a clock crystal oscillator, a clock skew adjuster, a controller and a storage unit;
the clock skew adjuster is configured with a delay time of a first trigger signal corresponding to the controller and a delay time of a second trigger signal corresponding to the storage unit;
the clock crystal oscillator outputs a clock signal to the clock deviation regulator;
a first output terminal of the clock skew regulator is connected to the controller via a first path, and a second output terminal of the clock skew regulator is connected to the memory unit via a second path;
the clock deviation regulator is used for carrying out delay processing on the clock signal according to the first path delay time so as to output a first trigger signal to the controller at a first moment; and carrying out delay processing on the clock signal according to the second path delay time so as to output a second trigger signal to the storage unit at a second moment.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by adding a necessary general hardware platform, and of course, can also be implemented by a combination of hardware and software. With this understanding in mind, the above-described solutions and/or portions thereof that are prior art may be embodied in the form of a computer program product, which may be embodied on one or more computer-usable storage media having computer-usable program code embodied therein (including but not limited to disk storage, CD-ROM, optical storage, etc.).
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable coordinate determination device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable coordinate determination device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable coordinate determination apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable coordinate determination device to cause a series of operational steps to be performed on the computer or other programmable device to produce a computer implemented process such that the instructions which execute on the computer or other programmable device provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.
Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (8)
1. A storage unit access control system, comprising: the clock skew adjuster comprises a clock crystal oscillator, a clock skew adjuster, a controller and a storage unit;
the clock skew adjuster is configured with a delay time of a first trigger signal corresponding to the controller and a delay time of a second trigger signal corresponding to the memory cell;
the clock crystal oscillator outputs a clock signal to the clock deviation regulator;
a first output terminal of the clock skew regulator is connected to the controller via a first path, and a second output terminal of the clock skew regulator is connected to the memory unit via a second path;
the clock deviation regulator is used for carrying out delay processing on the clock signal according to the first path delay time so as to output a first trigger signal to the controller at a first moment; and carrying out delay processing on the clock signal according to the second path delay time so as to output a second trigger signal to the storage unit at a second moment.
2. The system of claim 1, wherein the clock skew adjuster comprises: a clock adjustment control unit and a delay selector;
the clock crystal oscillator is connected with the delay selector and is used for providing the clock signal for the delay selector;
the clock regulation control unit is connected with the delay selector;
the first output end of the delay selector is connected with the controller and used for providing a first trigger signal for the controller;
the second output end of the delay selector is connected with the storage unit and used for providing a second trigger signal for the storage unit.
3. The system of claim 1, wherein the controller comprises: a receiving unit and a transmitting unit;
the first output terminal includes: a first transmitting output terminal connected to the transmitting unit and a first receiving output terminal connected to the receiving unit;
transmitting a first transmission trigger signal to the transmission unit through the first transmission output terminal; the first receive output terminal sends a first receive trigger signal to the receive unit.
4. An electronic device, characterized in that it comprises at least one memory unit access control system according to any one of claims 1 to 3.
5. A memory cell access control method, characterized in that,
acquiring a clock signal provided by a clock crystal oscillator;
the clock signal is subjected to delay processing based on preset delay time to obtain a first trigger signal and a second trigger signal, so that the first trigger signal is sent to a controller at a first moment and the second trigger signal is sent to a storage unit at a second moment;
wherein the first time and the second time are different times.
6. The method according to claim 5, wherein the delaying the clock signal based on the preset delay time to obtain the delayed first trigger signal and the delayed second trigger signal, so as to send the first trigger signal to the controller at a first time and send the second trigger signal to the storage unit at a second time comprises:
based on the clock signal, sending a first trigger signal to the controller at a first moment; the first trigger signal delays the clock signal according to a first path delay time, and determines a first moment for triggering the first trigger signal;
sending a second trigger signal to the storage unit at a second moment based on the clock signal; the second trigger signal delays the clock signal according to a second path delay time, and determines a second moment for triggering the second trigger signal;
wherein a difference between the first time and the second time is equal to a difference between the first path delay time and the second path delay time.
7. The method of claim 6, wherein the delaying the clock signal based on the preset delay time comprises:
and taking a first difference value between the first path delay time and the second path delay time as the preset delay time, and carrying out delay processing on the first trigger signal or the second trigger signal.
8. The method according to claim 6, wherein if the first path delay time and/or the second path delay time is greater than a preset delay time threshold, the clock signal is delayed based on the preset delay time threshold, and the delayed first trigger signal and/or second trigger signal is output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| CN107168163A (en) * | 2017-05-27 | 2017-09-15 | 西安工业大学 | A kind of submicrosecond Multi-path synchronous triggering device and its triggering method |
| CN107888172A (en) * | 2016-09-30 | 2018-04-06 | 瑞萨电子株式会社 | The control method of semiconductor device, semiconductor system and semiconductor device |
| CN108022610A (en) * | 2016-10-28 | 2018-05-11 | 芯成半导体有限公司 | Time-controlled type command timing adjustment in synchronous semiconductor integrated circuit |
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| CN107888172A (en) * | 2016-09-30 | 2018-04-06 | 瑞萨电子株式会社 | The control method of semiconductor device, semiconductor system and semiconductor device |
| CN108022610A (en) * | 2016-10-28 | 2018-05-11 | 芯成半导体有限公司 | Time-controlled type command timing adjustment in synchronous semiconductor integrated circuit |
| CN107168163A (en) * | 2017-05-27 | 2017-09-15 | 西安工业大学 | A kind of submicrosecond Multi-path synchronous triggering device and its triggering method |
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